Preliminary Data Sheet Subject to Change without Notice November 4, 2005 A3950 DMOS Full-Bridge Motor Driver Designed for PWM (pulse width modulated) control of dc motors, the A3950 is capable of peak output currents to ±2.8 A and operating voltages to 36 V. Package LP, 16-pin TSSOP with Exposed Thermal Pad NFAULT 1 16 NC Fault MODE 2 15 VREG PHASE 3 GND 4 SLEEP 5 ENABL 6 PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied PWM control signals. Internal synchronous rectification control circuitry is provided to lower power dissipation during PWM operation. 14 VCP Control Logic 13 GND Charge Pump OUTA 7 SENSE 8 12 CP2 11 CP1 10 OUTB 9 Internal circuit protection includes motor lead short-to-supply / short-toground, thermal shutdown with hysteresis, undervoltage monitoring of VBB and VCP, and crossover-current protection. The A3950 is supplied in a thin profile (<1.2 mm overall height) 16-pin TSSOP package with exposed thermal pad (package LP). It is lead (Pb) free with 100% matte tin leadframe plating. VBB FEATURES Approximate Scale 1:1 ABSOLUTE MAXIMUM RATINGS Load Supply Voltage, VBB............................................. 36 V Output Current, IOUT....................................................... 2.8 A Sense Voltage, VSENSE.................................±500 mV VBB to OUTx .................................................... 36 V OUTx to SENSE ................................................ 36 V Logic Input Voltage, VIN ..........................–0.3 to 7 V Operating Temperature Range Ambient, TA, Range S .................... –20°C to 85°C Junction Temperature, TJ(MAX)............................ 150°C Storage Temperature, TS ................. –40°C to 125°C Low RDS(on) outputs Overcurrent protection Motor lead short-to-supply protection Short-to-ground protection Sleep function Synchronous rectification Diagnostic output Internal UVLO Crossover-current protection Use the following complete part numbers when ordering: Part Number A3950SLP-T A3950SLPTR-T A3950DS Packing 96 pieces / tube 13-in. reel, 4000 pieces / reel Preliminary Data Sheet Subject to Change without Notice November 4, 2005 A3950 DMOS Full-Bridge Motor Driver Functional Block Diagram 0.1 µF CP2 CP1 VCP Charge Pump 0.1 µF VREG Load Supply VBB Low-Side Gate Supply 22 µF 25 V Bias Supply 0.1 µF 100 µF MODE PHASE OUTA Control Logic OUTB ENABLE SENSE SLEEP NFAULT UVLO STB STG TSD Warning Motor Lead Protection Pad GND VBB OUTA OUTB SENSE RSENSE GND Control Logic Table1 Pin Function PHASE ENABLE MODE SLEEP OUTA OUTB 1 1 X 1 H L Forward 0 1 X 1 L H Reverse X 0 1 1 L L Brake (slow decay) 1 0 0 1 L H Fast Decay Synchronous Rectification2 0 0 0 1 H L Fast Decay Synchronous Rectification2 X X X 0 Z Z Sleep Mode 1X iindicates “don’t care,” Z indicates high impedence. 2To prevent reversal of current during fast decay synchronous rectification, outputs go to the high impedance state as the current approaches 0 A. 2 A3950DS Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Preliminary Data Sheet Subject to Change without Notice November 4, 2005 A3950 DMOS Full-Bridge Motor Driver ELECTRICAL CHARACTERISTICS at TJ = 25°C, VBB = 8 to 36 V, unless noted otherwise Characteristics Symbol Test Conditions fPWM < 50 kHz Motor Supply Current IBB Charge pump on, outputs disabled Sleep mode VIH PHASE, ENABLE, MODE Input Voltage VIL VIH SLEEP Input Voltage VIL IIH VIN = 2.0 V PHASE, MODE Input Current1 IIL VIN = 0.8 V IIH VIN = 2.0 V ENABLE Input Current IIL VIN = 0.8 V IIH VIN = 2.7 V SLEEP Input Current IIL VIN = 0.8 V Isink = 1.0 mA NFAULT Output Voltage VOL Input Hysteresis, except SLEEP VIHys Source driver, IOUT = -2.8 A, TJ=25°C Source driver, IOUT = -2.8 A, TJ=125°C Output On Resistance RDS(on) Sink driver, IOUT = 2.8 A, TJ=25°C Sink driver, IOUT = 2.8 A, TJ=125°C PWM, change to source or sink ON Propagation Delay Time tpd PWM, change to source or sink OFF Crossover Delay tCOD Protection Circuitry VBB increasing UVLO Threshold VUV UVLO Hysteresis VUVHys Overcurrent Threshold2 IOCP Overcurrent Protection Period tOCP Thermal Warning Temperature TJW Temperature increasing Thermal Warning Hysteresis TJWHys Recovery = TJW – TJWHys Thermal Shutdown Temperature TJTSD Temperature increasing Thermal Shutdown Hysteresis TJTSDHys Recovery = TJTSD – TJTSDHys 1For Min. Typ. Max. Units – 6 8.5 mA – 3 4.5 mA – – 10 μA 2.0 – – V – – 0.8 V 2.7 – – V – – 0.8 V – <1.0 20 μA – <–2.0 –20 μA – 40 100 μA – 16 40 μA – 27 50 μA – <1 10 μA – – 0.4 V 100 150 200 mV – 0.35 0.48 Ω – 0.55 0.8 Ω – 0.3 0.43 Ω – 0.45 0.7 Ω – 600 – ns – 100 – ns – 500 – ns – – 3 – – – – – 6.5 250 – 1.2 160 15 175 15 – – – – – – – – V mV A ms °C °C °C °C Value Units 4-layer PCB based on JEDEC standard 34 ºC/W 2-layer PCB with 3.8 in.2 copper both sides, connected by thermal vias 43 ºC/W input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. protection is tested at 25°C in a restricted range and guaranteed by characterization. 2Overcurrent THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Package Thermal Resistance Symbol RθJA Test Conditions* *Additional thermal data available on the Allegro Web site. 3 A3950DS Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Preliminary Data Sheet Subject to Change without Notice November 4, 2005 A3950 DMOS Full-Bridge Motor Driver Timing Diagram: PWM Control SLEEP ENABLE PHASE MODE VBB VOUTA 0 VBB VOUTB 0 IOUTX 0 A 1 2 3 4 5 6 7 VBB 8 9 VBB 1 5 6 OutA OutB 3 2 4 7 OutA OutB 8 9 A Charge pump and VREG power-on delay (≈200 µs) 4 A3950DS Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Preliminary Data Sheet Subject to Change without Notice November 4, 2005 A3950 DMOS Full-Bridge Motor Driver Timing Diagram: Overcurrent Control VOUTA VOUTB High-Z IPEAK IOUTx IOCP ENABLE, Source or Sink BLANK Charge Pump Counter tBLANK tOCP NFAULT Motor lead short condition Normal dc motor capacitance 5 A3950DS Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Preliminary Data Sheet Subject to Change without Notice November 4, 2005 A3950 DMOS Full-Bridge Motor Driver Functional Description VREG. This supply voltage is used to run the sink-side DMOS outputs. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. The VREG pin should be decoupled with a 0.22 μF capacitor to ground. Charge Pump. The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates. A 0.1 μF ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1 μF ceramic monolithic capacitor should be connected between VCP and VBB to act as a reservoir to run the high-side DMOS devices. The VCP voltage level is internally monitored and, in the case of a fault condition, the outputs of the device are disabled. Shutdown. In the event of a fault due to excessive junction temperature, or low voltage on VCP or VREG, the outputs of the device are disabled until the fault condition is removed. At power-on the UVLO circuit disables the drivers. Sleep Mode. Control input SLEEP is used to minimize power consumption when the A3950 not in use. This disables much of the internal circuitry, including the regulator and charge pump. A logic low setting puts the device into Sleep mode, and a logic high setting allows normal operation. After coming out of Sleep mode, provide a 1 ms interval before applying PWM signals, to to allow the charge pump to stabilize. MODE. Control input MODE is used to toggle between fast decay mode and slow decay mode. A logic high puts the device in slow decay mode. Synchronus rectification is always enabled. Braking. The braking function is implemented by driving the device in slow decay mode via the MODE setting and applying an enable chop command. Because it is possible to drive current in both directions through the DMOS switches, this configuration effectively shorts out the motor generated BEMF as long as the ENABLE chop mode is asserted. The maximum current can be approximated by VBEMF/RL. Care should be taken to insure that the maximum ratings of the device are not exceeded in worse case braking situations: high speed and high-inertia loads. Overcurrent Protection. The voltage on the output pins relative to supply are monitored to ensure that the motor lead is not shorted to supply or ground. If a short is detected, the full-bridge outputs are turned off, flag NFAULT is driven low, and a 1.2 ms fault timer is started. After this 1.2 ms period, tOCP , the device will then be allowed to follow the input commands and another turn-on is attempted. If there is still a fault condition, the cycle repeats. If, after tOCP expires, it is determined that the short condition is not present, the NFAULT pin is released and normal operation resumes. Diagnostic Output. The NFAULT pin signals a problem with the chip via an open drain output. A motor fault, undervoltage condition, or TJ > 160°C will drive the pin active low. This output is not valid when SLEEP puts the device into minimum power dissipation mode. TSD. Two die temperature monitors are integrated on the chip. As die temperature increases towards the maximum, a thermal warning signal will be triggered at 160°C. This fault drives the NFAULT low, but does not disable the operation of the chip. If the die temperature increases further, to approximately 175°C, the full-bridge outputs will be disabled until the internal temperature falls below a hysteresis of 15°C. 6 A3950DS Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Preliminary Data Sheet Subject to Change without Notice November 4, 2005 A3950 DMOS Full-Bridge Motor Driver Applications Information Power Dissipation. First order approximation of power dissipation in the A3950 can be calculated by first examining the power dissipation in the full-bridge during each of the operation modes. The A3950 features synchronous rectification, a feature that effectively shorts out the body diode by turning on the low RDS(on) DMOS driver during the decay cycle. This significantly reduces power dissipation in the full-bridge. In order to prevent shoot-through, where both source and sink driver are on at the same time, the A3950 implements a 500 ns typical crossover delay time. For this period, the body diode in the decay current path conducts the current until the DMOS driver turns on. This does affect VBB 1 3 2 1 Drive current 2 Fast decay with synchronous rectification (reverse) 3 Slow decay with synchronous rectification (brake) Figure 1. Current Decay Patterns power dissipation and may need to be considered in high current, high ambient temperature applications. In addition, motor parameters and switching losses can add power dissipation that could affect critical applications. Drive Current. This current path is through source DMOS driver, motor winding, and sink DMOS driver. Power dissipation is I2R loses in one source and one sink DMOS driver, as shown in the following equation: PD = I 2 ( RDS(on)Source + RDS(on)Sink ) (1) Fast Decay with Synchronous Rectification. This decay mode is equivalent to a phase change where the opposite drivers are switched on. When in fast decay, the motor current is not allowed to go negative (direction change). Instead, as the current approaches zero, the drivers turn off. The power calculation is the same as the drive current calculation, equation 1: Slow Decay SR (Brake Mode). In this decay mode, both sink drivers turn on, allowing the current to circulate through the sink drivers and the load. Power dissipation is I2R loses in the two sink DMOS drivers: PD = I 2 ( 2 × RDS(on)Sink ) (2) Layout. The printed circuit board should include a heavy ground plane. For optimum electrical and thermal performance, the exposed thermal pad of the device should be soldered directly to an exposed copper area directly under the device. The load supply pin, VBB, should be decoupled with an electrolytic capacitor (typically 100 μF) in parallel with a ceramic capacitor placed as close as possible to the device. The ceramic capacitors between VCP and VBB, connected to VREG, and between CP1 and CP2, should be as close to the pins of the device as possible, in order to minimize lead inductance. 7 A3950DS Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Preliminary Data Sheet Subject to Change without Notice November 4, 2005 A3950 DMOS Full-Bridge Motor Driver Ground. A star ground should be located as close to the A3950 as possible. The copper ground plane directly under the exposed thermal pad makes a good location for the star ground point. The exposed pad can be connected to ground for this purpose. level, the current sensing resistor should have an independent ground return to the star ground point. This trace should be as short as possible. For low value sense resistors, the IR drops in the PCB can be significant, and should be taken into account. SENSE Pin. A low value resistor can be placed between the SENSE pin and ground for current sensing purposes. To minimize ground-trace IR drops in sensing the output current When selecting a value for the sense resistor be sure not to exceed the maximum voltage on the SENSE pin of ±500 mV. Terminal List Table Name Number Description NFAULT 1 Fault output, open drain MODE 2 Logic input PHASE 3 Logic input for direction control GND 4 Ground SLEEP 5 Logic input ENABLE 6 Logic input OUTA 7 DMOS full-bridge output A SENSE 8 Power return VBB 9 Load supply voltage OUTB 10 DMOS full-bridge output B CP1 11 Charge pump capacitor terminal CP2 12 Charge pump capacitor terminal GND 13 Ground VCP 14 Reservoir capacitor terminal VREG 15 Regulator decoupling terminal NC 16 No connection Pad – Exposed pad for thermal dissipation connect to pins 4,13 8 A3950DS Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Preliminary Data Sheet Subject to Change without Notice November 4, 2005 A3950 DMOS Full-Bridge Motor Driver LP Package, 16-Pin TSSOP with Exposed Thermal Pad 5.1 4.9 16 .201 .193 8º 0º A B 0.20 .008 0.09 .004 Preliminary dimensions, for reference only Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only (reference JEDEC MO-153 ABT) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 4.5 4.3 B 3 .118 NOM A Terminal #1 mark area B Exposed thermal pad (bottom surface) .177 .169 6.6 6.2 .260 .244 1 .039 REF A 1 2 3 .118 NOM 16X 0.25 .010 SEATING PLANE 0.10 [.004] C 16X 0.75 .030 0.45 .018 0.30 .012 0.19 .007 C SEATING PLANE GAUGE PLANE 1.20 .047 MAX 0.10 [.004] M C A B 0.65 .026 0.15 .006 0.00 .000 The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright©2005 AllegroMicrosystems, Inc. 9 A3950DS Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com