A8450 Automotive Multioutput Voltage Regulator Package LB 24-pin SOIC Buck Converter VBB 1 CP2 2 CP1 3 VCP 4 VREG11 5 GND 6 GND 7 ENB 8 CPOR 9 CLADJ 10 VADJBD 11 FB 12 Charge Pump Soft Start 3.3 V Lin Reg Control 5V Dig/Anlg Lin Reg 1.2 V to 3.3 V Lin Reg Control 5 V Reg Track Control 24 LX 23 ENBAT 22 V33 21 V33BD 20 CL33 19 GND 18 GND 17 VREG 16 V5D 15 NFAULT 14 NPOR 13 V5A The A8450 is a multioutput power supply intended for automotive applications. The A8450 operates from a wide input supply range and is designed to satisfy the requirements of high ambient temperature environments. Four regulated voltage outputs provide multiple options. The 3.3 V regulator and the 1.2 to 3.3 V adjustable regulator can be used to power microcontroller or DSP cores, or for I/O, sensing, and A-to-D conversion. Two 5 V outputs, one digital and the other analog, feature output tracking within 0.5% of each other over the operating temperature range. In addition, the analog regulator is protected against short-tobattery conditions. All four regulators feature foldback current limit protection. The device can be enabled or disabled using two input pins. The high voltage input, on the ENBAT pin, allows enable/disable using an engine ignition or battery switch signal. The logic-level input, on the ENB pin, allows enable/disable by microcontroller or DSP signals. When disabled, the A8450 draws less than 10 µA of current. A POR (power-on-reset) block monitors the supply voltages and provides a reset signal, with an adjustable delay, for microcontroller or DSP resets. A separate fault pin signals TSD (thermal shutdown), 5 V analog shortto-supply, and 5 V analog or digital undervoltage. The A8450 is supplied in a 24-pin SOIC package (part number suffix LB) with fused power ground pins for enhanced thermal performance. This provides an RθJA of 35°C/W on a 4-layer board (see chart on p. 4). Approximate Scale 1:1 FEATURES ABSOLUTE MAXIMUM RATINGS Load Supply Voltage, VBB ..................................45 V Analog Output, Pin V5A........................–1 V to 45 V Logic Input Signal Pin ENBAT .................................–0.3 V to 45 V Pin ENB .....................................–0.3 V to 6.5 V Pin LX.................................................... –2 V to VBB Operating Temperature Range Ambient Temperature, TA ............ –40°C to 135°C Junction Temperature, TJ(MAX) ..................... 150°C Storage Temperature, TS .................... –55°C to 150°C A8450KLB-DS, Rev. 1 6 V to 45 V input range dc-to-dc buck converter with 5.7 V output Overcurrent protection with foldback, and undervoltage lockout (UVLO) Dual 5 V outputs – Digital 5 V ±2%, 200 mA – Analog 5 V, 200 mA – Short-to-supply protection on analog regulator – Analog to digital regulator output tracking < 0.5%, throughout operating temperature range 3.3 V linear regulator, with foldback current limit Adjustable 1.2 V to 3.3 V linear regulator, adjustable foldback current limit Ignition switch enable; Sleep mode 100% duty cycle operation for low input voltages Power OK output –40°C to 135°C ambient operating temperature range Use the following complete part number when ordering: Part Number Package Description A8450KLB 24-pin, SOIC Webbed Leadframe A8450 Automotive Multioutput Voltage Regulator Functional Block Diagram D2 C8 High Voltage Switch CP1 VCP L1 D1 CIN C7 CP2 VIN COUT LX VBB VREG R3 CL33 VREG11 C10 Buck Converter with Switching Regulator Charge Pump 3.3 V Linear Regulator Control V33BD Q1 V33 Soft Start CPOK VREG VBB C3 R4 ENBAT High V Protection Internal Reference VREF CLADJ 1.2 V to 3.3 V Adjustable Linear Regulator Control ENB VADJBD Q2 R1 FB R2 VADJ C4 NPOR VREG 5 V Digital Linear Regulator VUVLOREG VUVLOADJ VUVLO33 CPOR C9 C1 Adjustable Delay Current Limiting POR Block V5D 5V Analog Linear Regulator and V5D to V5A Tracking Control V5A NFAULT C2 GND ID C1, C2, C3, C4 COUT CIN C7, C8 C10 D1, D2 L1 Q1, Q2 pass transistors Fault TSD Warning V5A Short to Supply UVLO V5D, V5A Short-to-Supply Protection Characteristics 1 µF, 25 V ceramic X7R 100 µF, 35 V low-ESR electrolytic 47 µF, 63 V electrolytic 0.1 µF, 50 V ceramic X7R (for 14 V applications), or 0.1 µF, 100 V ceramic X7R (for 42 V applications) 0.22 µF, 10 V X7R 1 A, 40 V Schottky (for 14 V applications) 100 µH, 1.2 A npn transistor, hFE > 50 Representative Device UHC1V101M, Nichicon EKO4, Sanken D03316HT, Coilcraft MPSW06 2 A8450KLB-DS, Rev. 1 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A8450 Automotive Multioutput Voltage Regulator ELECTRICAL CHARACTERISTICS at TA = –40ºC to 135°C, VBB = 6 to 45 V, VENB = 5 V, unless otherwise noted Characteristics Supply Quiescent Current Regulated Output Voltage Symbol IBB VREG Buck Switch On-Resistance RDSON Buck Switch Current Limit IDSLIM Test Conditions Enabled mode: VENBAT or VENB = HIGH, IOUT = 0 mA: VBB = 14 V Enabled mode: VENBAT or VENB = HIGH, IOUT = 0 mA; VBB = 6 V Disabled mode: VENBAT and VENB = LOW ILOAD = 550 mA = ILOADV5D + ILOADV5A + ILOADV33 + ILOADVADJ; VBB > 6.5 V Dropout: 6 V ≤ VBB < 6.5 V TJ = 25°C TJ = 135°C Min. Typ. Max. Units – 6 10 mA – 10 15 mA – – 10 µA 5.50 – 5.80 V 5.00 – – 1.0 – 415 650 1.2 5.80 500 750 1.8 V mΩ mΩ A dc-to-dc Fixed Off-Time tOFF VBB = 14 V – 4.75 – µs Soft Start Time Logic Inputs tSS VBB = 14 V 5 10 15 ms HIGH input level LOW input level HIGH input level, VENBAT = 45 V HIGH input level, VENBAT = 14 V LOW input level, VENBAT = 0.8 V HIGH input level LOW input level HIGH input level, VENB ≥ 2.7 V LOW input level, VENB ≤ 0.8 V 2.7 –0.3 – – –1 2.7 –0.3 – –1 – – – – – – – – – 45 0.8 300 70 10 6.5 0.8 50 10 V V µA µA µA V V µA µA 1 mA ≤ ILOADV5D ≤ 200 mA 1 mA ≤ ILOADV5A ≤ 200 mA 4.9 5.0 5.1 4.9 5.0 5.1 3.234 3.300 3.366 ENBAT Logic Input Voltage VENBAT ENBAT Input Current IENBAT ENB Logic Input Voltage VENB ENB Input Current IENB Linear Regulator Outputs* V5D Output Voltage V5A Output Voltage V33 Output Voltage V5A to V5D Tracking VOUTV5D VOUTV5A VOUTV33 VTRACK V5D Current Limit IOUTV5DLIM V5A Current Limit IOUTV5ALIM Base Drive Output Current Feedback Voltage Feedback Input Bias Current IBD VFB IFB 50 mA ≤ ILOADV5A, ILOADV5D ≤ 200mA; VBB > 6.5 V 1 V ≤ VOUTVADJ, VOUTV33 ≤ 4 V V V V –25 – 25 mV 200 300 – mA 200 300 – mA 5.0 1.16 –400 10.0 1.20 –100 16.0 1.24 100 mA V nA Continued on next page 3 A8450KLB-DS, Rev. 1 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A8450 Automotive Multioutput Voltage Regulator ELECTRICAL CHARACTERISTICS (continued) at TA = –40ºC to 135°C, VBB = 6 to 45 V, VENB = 5 V, unless otherwise noted Characteristics Protection Symbol NFAULT, NPOR Output Voltage VERRON NFAULT, NPOR Leakage Current POR Delay IERROFF tPOR V33 Undervoltage Threshold VUVLOV33 V33 Hysteresis VHYSV33 V5A, V5D Undervoltage Threshold VUVLOV5 V5A, V5D Hysteresis Test Conditions Fault asserted; INFAULT, INPOR = 1 mA VNFAULT, VNPOR = 5 V C9 = 0.47 µF V33 rising V33 falling VREG rising VREG falling VHYSV5 VADJ Undervoltage Threshold VUVLOVADJ VFB rising VFB falling At FB pin VADJ Hysteresis VHYSVADJ VADJ, V33 Overcurrent Threshold VOC VREG Undervoltage Threshold VUVLOVREG Thermal Warning Threshold TJTW TJ rising Thermal Shutdown Threshold TJTSD TJ rising Thermal Shutdown Hysteresis THYSTSD Recovery period = TJTSD – TJTW *Linear regulator output specifications are only valid when VREG is in regulation (VBB ≥ 6.5). Min. Typ. Max. Units – – 400 mV – 65 2.80 2.75 – 4.36 4.24 – 1.02 0.97 – 175 4.94 – – – – 100 2.95 2.90 80 4.50 4.38 125 1.07 1.02 70 200 5.15 160 175 15 1 135 3.10 3.05 – 4.75 4.63 – 1.12 1.07 – 225 5.36 – – – µA ms V V mV V V mV V V mV mV V °C °C °C Power Dissipation Versus Ambient Temperature 4.5 Power Dissipation, PD (W) 4.0 3.5 4-Layer PCB* (RθJA = 35 ºC/W) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 20 40 60 80 100 120 140 160 Ambient Temperature (°C) *In still air; mounted on PCB based on JEDEC high-conductance standard PCB (JESD51-7; High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages); data on other PCB types is provided on the Allegro Web site. 4 A8450KLB-DS, Rev. 1 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A8450 Automotive Multioutput Voltage Regulator Timing Diagrams VREG VHYSV33 VOUTV33 VUVLOV33 VHYSVADJ VOUTVADJ VUVLOVADJ VNPOR tPOR tPOR AB Slope of VOUTV33 and VOUTVADJ from A to B determined by ILOAD and output capacitor (C3, C4). Figure 1a. NPOR fault due to undervoltage lockout on the V33 or FB pins VBB VREG VUVLOVREG VOUTV33 VUVLOV33 VREG Monitor VOUTVADJ VENBAT VENB VNPOR tPOR tPOR POR event initiates V33 can sustain regulation with normal load by bulk capacitor (COUT) on VREG. Figure 1b. Power-off using VBB +7 V VCP VBB > 6 V VREG VREG = 1.8 V VOUTV5A/V5D VUVLO(33) VOUTV33 VOUTVADJ VNPOR VENBAT VENB ENBAT signals power-on Charge pump ramping Charge pump OK flag set tSS tPOR VUVLOV33 exceeded; VADJ enabled ENB signals power-off A Slope of VREG (which controls VOUTV5A/V5D, VOUTV33, and VOUTVADJ) from A to B determined by ILOAD and COUT. B Figure 1c. Power-on using ENBAT, followed by power-off using ENB 5 A8450KLB-DS, Rev. 1 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A8450 Automotive Multioutput Voltage Regulator Load Transients Diagrams VIN = 12 V; ILOAD = 100 mA; TA = 25°C; ac-coupled; C1, C2, C3 and C4 = 1 µF 3.3 V Regulator 90% 10% tRISE VOUT (50 mV / Div.) ILOAD = 5 to 100 mA ILOAD t (50 µs/Div.) t (0.2 µs/Div.) Adjustable Regulator, at 1.8 V* VOUT (50 mV / Div.) VOUT (50 mV / Div.) V5D Regulator t (50 µs/Div.) V5A Regulator *For the adjustable regulator, the transient load response is improved as the voltage is reduced. This is due to the ability of the regulator to provide more base drive (VADJBD) because of more available voltage. When the adjustable regulator approaches 3.3 V, its transient load response is equivalent to the response of the V33 regulator. VOUT (50 mV / Div.) t (50 µs/Div.) t (50 µs/Div.) For all regulators, load transients can be improved by increasing the output capacitance (C1, C2, C3, and C4). In order to keep ESR down it is best to use ceramic type capacitors. However, large values in ceramic type capacitors are either not available or very expensive. If larger values are needed, above 22 µF, electrolytic capacitors with low ESR ratings can be used. Performance can be improved further by adding a 1 µF ceramic in parallel with the electrolytic. 6 A8450KLB-DS, Rev. 1 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A8450 Automotive Multioutput Voltage Regulator Functional Description The converter employs a soft-start feature. This ramps the converter output voltage and limits the maximum demand on VREG by controlling the inrush current required at power-on to charge the external capacitor, COUT, and any dc load. tOFF by VBB 5.5 5.0 4.5 4.75 µs 12 V 4.0 3.5 tOFF (µs) Buck Converter with Switching Regulator. A current-mode, variable frequency buck dc-to-dc converter and switching regulator are integrated in the A8450, as shown in figure 2. This feature allows the device to efficiently handle power over a wide range of input supply levels. The dc-to-dc converter outputs 5.7 V typical, and has an overcurrent limit of 1.2 A typical. 3.0 2.5 2.0 1.5 1.0 An internal charge pump provides gate drive for the N-channel MOSFET buck switch. A 100% duty cycle is implemented when using low VBB input voltages. 2.05 µs 11 V 0.58 µs 6.02 V 0.5 0.0 5 7 9 11 13 15 VBB (V) At VBB lower than 12 V, off-time, tOFF, is reduced, as shown in figure 3. This reduction keeps the switching frequency, fPWM, within a reasonable range and lowers the ripple current. Lowering the ripple current at low VBB levels prevents degradation of linear regulator headroom due to VREG ripple voltage. Figure 3. When VBB falls below 12 V, tOFF decreases L1 100 µH 5 V Linear Regulators. Two 5 V medium-power linear regulators are provided. These low-dropout regulators feature foldback current limiting for short-to-supply protection. When a direct D1 COUT 100 µF LX VBB Buck Converter Buck Switch tOFF VCP Switching Regulator Control ENB IDEMAND Clock Counter 1.2 A Limit Soft Start Ramp Generation IPEAK Compensation Error Bandgap 1.22 V Clamp VREG Figure 2. Buck converter with switching regulator 7 A8450KLB-DS, Rev. 1 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A8450 Automotive Multioutput Voltage Regulator short is applied to the regulator output, either V5A or V5D, the current folds back to 0 V at 50 mA, as shown in figure 4a. The voltage recovers to its regulated output when the short is removed. tors from a short-to-ground condition. The current limit setting, ICL (mA), is calculated using the formula ICL = VOC ⁄ RRCL The V5A and V5D regulators track each other during poweron, and when the device is enabled and ramped up out of disabled mode, the regulators will start to track when VREG reaches approximately 1.8 V. These regulators are guaranteed to track to within 0.5% of each other under normal operating conditions. where RCL (Ω) is the current-limiting resistor corresponding to that regulator (R3 for the 3.3 V regulator, and R4 for the adjustable regulator). When ICL is exceeded, the maximum load current through that regulator is folded back to 40% of ICL ±10%, as shown in figure 4b. If current limiting is not needed, the CL33 and CLADJ pins should be shorted to the VREG pin. 3.3 V and Adjustable Linear Regulators. Two additional linear regulators, one that outputs at 3.3 V, and another that has a 1.2 V to 3.3 V adjustable output, can be implemented using external npn pass transistors. The output voltage of the adjustable regulator, VOUTVADJ (V), is set by the values of the output resistors, R1 and R2 (Ω). It can be calculated as Disabled Mode. When the two input signal pins, ENBAT and ENB, are pulled low, the A8450 enters disabled mode. This is a sleep mode, in which all internal circuitry is disabled in order to draw a minimal current from VBB. When either of these pins is pulled high, the device is enabled. When emerging from disabled mode, the buck converter switching regulator does not operate until the charge pump has stabilized (≈ 300 µs). VOUTVADJ = VFB (1+R1 ⁄ R2) where VFB (V) is the voltage on the feedback pin, FB. Additional pins, CL33 and CLADJ, are provided for setting current limits. These are used to protect the external pass transis- Enabled Mode. When one or both of the signal input pins, ENBAT and ENB, are in the high state, the A8450 is enabled. 5V Regulators Overcurrent Foldback 3.3 V and Adjustable Regulators Overcurrent Foldback 6 6 5 5 0.4 ICL ±10% 4 VOUT (V) VOUT (V) 4 ICL 3 2 VOUTV33 and VOUTVADJ(max) 3 2 IOUTV5DLIM and IOUTV5ALIM VOUTVADJ(min) 1 1 0 0 0 50 100 150 200 250 300 1600 IOUT (mA) Figure 4a. Linear foldback to 50 mA. Foldback occurs at the typical current limit for the 5 V regulator. 0 1600 IOUT (mA) Figure 4b. Linear foldback to a percentage of ICL . Foldback occurs at the current limit setting for the regulator. 8 A8450KLB-DS, Rev. 1 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A8450 Automotive Multioutput Voltage Regulator ENBAT is an edge-triggered enable (logic 1 ≥ 2.7 V), which is used to enable the A8450 in response to a high-voltage signal, such as from an automobile ignition or battery switch. In this capacity, ENBAT is used only as a momentary switch to wake up the device. If there is no need for a high-voltage signal, ENBAT can be pulled low continuously. ENB is used to initiate the reset of the device. If ENBAT is pulled low, ENB acts as a single reset control. Diagnostics. An open drain output, through the NFAULT pin, is pulled low to signal to a DSP or microcontroller any of the following fault conditions: • V5A, the 5 V analog regulator output, is shorted to supply • Either or both of the V5A and the V5D regulator outputs are below their UVLO threshold, VUVLOV5 • Device junction temperature, TJ, exceeds the Thermal Warning threshold, TJTW Charge Pump. The charge pump generates a voltage above VBB in order to provide adequate gate drive for the N-channel buck switch. A 0.1 µF ceramic monolithic capacitor, C7, should be connected between the VCP pin and the VBB pin, to act as a reservoir to run the buck converter switching regulator. VCP is internally monitored to ensure that the charge pump is disabled in the case of a fault condition. In addition, a 0.1 µF ceramic monolithic capacitor, C8, should be connected between CP1 and CP2. Power On Reset Delay. The POR block monitors the supply voltages and provides a signal that can be used to reset a DSP or microcontroller. A POR event is triggered by any of the following conditions: • Either V33 or VADJ is pulled below its UVLO threshold, VUVLOV33 or VUVLOVADJ. This occurs if the current limit on either regulator, VOC , is exceeded. It also occurs if the VREG voltage falls below VREGMON, due to current exceeding IDSLIM. • Both input signal pins, ENB and ENBAT, are pulled low. This immediately pulls the NPOR pin low, indicating that the device is beginning a power-off sequence. In addition, the buck converter switching regulator is disabled, and the VREG supply begins to ramp down. The rate at which VREG decays is dependent on the total current draw, ILOAD, and value of the output capacitors (C1, C2, C3, and C4). • VREG drops below its UVLO threshold, VUVLOVREG. • During any normal power-on, VOUTVADJ falls below VUVLOVADJ, triggering a POR. An open drain output, through the NPOR pin, is provided to signal a POR event to the DSP or microcontroller. The reset occurs after an adjustable delay, tPOR, set by an external capacitor, C9, connected to the CPOR pin. The value of tPOR (ms) is calculated using the following formula tPOR = 2.13×105 × CCPOR where CCPOR (µF) is the value of the C9 capacitor. A POR can be forced without a significant drop in the supply voltage, VREG, by pulsing low both the ENB and the ENBAT pins. However, pulse duration should be short enough so that VREG does not drop significantly. Thermal Shutdown. When the device junction temperature, TJ, is sensed to be at TJTSD (≈15°C higher than the thermal warning temperature, TJTW), a fault is indicated at the NFAULT pin. At the same time, a thermal shutdown circuit disables the buck converter, protecting the A8450 from damage. 9 A8450KLB-DS, Rev. 1 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A8450 Automotive Multioutput Voltage Regulator Application Information Component Selection VL1OFF = 5.8 + 0.8 + (0.550 Output Inductor (L1). This inductor must be rated to handle the total load current, ILOAD. In addition, the value chosen must keep the ripple current to a reasonable level. A typical selection is a power inductor rated at 100 µH and 1.3 A. The worse case ripple current, IRIPPLE(max) (mA), can be calculated as IRIPPLE(max) = VL1OFF × tOFF ⁄ LL1 where LL1 (µH) is the inductance for the selected component, and VL1OFF is the voltage (V) through the inductor when the A8450 is in the quiescent state VL1OFF = VREG(max) + VD1 + (ILOAD × RL1) where VD1 (V) is the voltage drop on diode D1, ILOAD (mA) is the total load current, and RL1 is the specified dc resistence (Ω) for the selected inductor at its rated temperature. The frequency, fPWM (Hz), of the switching regulator in the buck converter can then be estimated by fPWM = 1/(tON + tOFF) where tON (µs) is calculated as tON = IRIPPLE(max) × LL1 ⁄ VL1ON and VL1ON (V) as VL1ON = VBB – (ILOAD × RDSON(max)) – (ILOAD × RL1) – VREG(max) Example Given a typical application with VBB = 14 V, tOFF = 4.75 µs, and ILOAD = 550 mA. (Note that the value for tOFF is constant for VBB > 12 V, as shown in figure 3.) Given also a 100 µH power inductor rated at 400 mΩ for 125ºC. (Note that temperature ratings for inductors may include self-heating effects. If a 125ºC rating includes a selfheating temperature rise of 20ºC at maximum current, then the actual ambient temperature, TA, cannot exceed 105ºC.) × 0.400) = 6.821 V VL1ON × 4.75 ⁄ 100 = 0.324 A = 14 – (0.550 × 0.750) – (0.550 × 0.400) tON = 0.324 IRIPPLE(max) = 6.821 – 5.8 = 7.56 V × 100 ⁄ 7.56 = 4.3 µs fPWM = 1/(4.3 + 4.75) = 111 kHz In the case of a shorted output, the buck converter could reach its internal current limit, IDSLIM , of 1.2 A typical. To ensure safe operation, the ISAT rating for the selected inductor should be greater than 1.4 A. However, if the external current limit resistors, R3 and R4, selected for the 3.3 V and adjustable (1.2 V to 3.3 V) regulators, are rated such that the total inductor current, ILOAD, could never reach that internal current limit, then an inductor can be selected that has an ISAT rating closer to the calculated output current of the device, ILOAD, plus the maximum ripple current, IRIPPLE(max). Higher inductor values can be chosen to lower IRIPPLE. This may be an option if it is desired to increase the total maximum current that is drawn from the switching regulator. The maximum total current available, ILOAD (mA), is calculated as ILOAD = IDSLIM – (IRIPPLE(max) ⁄ 2) Catch Diode (D1). The Schottky catch diode should be rated to handle 1.2 times the maximum load current, ILOAD, because the duty cycle at low input voltages, VBB, can be very close to 100%. The voltage rating should be higher than the maximum input voltage, VBB(max), expected during any operating condition. VREG Output Capacitor (COUT). Voltage ripple in the VREG output is the main consideration when selecting the VREG output capacitor, COUT. The peak-to-peak output voltage ripple, VRIPPLE(p-p) (mV), is calculated as VRIPPLE(p-p) = IRIPPLE × ESRCOUT with ESR in ohms. It is recommended that the maximum level of VRIPPLE(p-p) be less than 200 mV. 10 A8450KLB-DS, Rev. 1 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A8450 Automotive Multioutput Voltage Regulator For electrolytic output capacitors, a low-ESR type is recommended, with a minimum voltage rating of 10 V. However, because ESR decreases with voltage, the most cost-effective choice may be a capacitor with a higher voltage rating. Regulator Output Capacitors (C3 and C4). The output capacitors used with the 3.3 V regulator (C3) and the 1.2 V to 3.3 V adjustable regulator (C4), should be 1 µF or greater X7R (5% tolerance) ceramic or equivalent capacitors, with a maximum capacitance change of ±15% over a temperature range of –55ºC to 125ºC. The ESR of these capacitors does not affect the outputs of the corresponding regulators. If a greater capacitance is used, the regulators have improved ripple rejection at frequencies greater than 100 kHz. Pass Transistors (Q1 and Q2). The pass transistors used to implement the 3.3 V regulator and the 1.2 V to 3.3 V adjustable regulator must ensure the following: • Stable operation. The cutoff frequency for the control loops of the regulators is 100 kHz. Transistors must be selected that have gain bandwidth product, fT (kHz), and beta, hFE (A), ratings such that fT ⁄ hFE > 100 kHz For a typical application where VREG = 5.8 V, VOUT = 2.5 V, and ILOAD = 190 mA PD = (5.8 – 2.5) Adjusting Pass Transistor Power Dissipation Transistors are manufactured in a wide variety of package types, and the thermal dissipation efficiencies of the packages can vary greatly. In general, increasing thermal efficiency can also increase cost substantially. Selecting the package to closely match operating conditions is important to optimizing application design and cost. Even when using a thermally-enhanced package, it remains difficult to provide high current to a load at high ambient operating temperatures. Depending on the load requirements, using drop resistors, as shown in figure 5, may be necessary to protect the pass transistor from overheating. The output current-limiting resistors, RCL (corresponding to R3 and R4), will drop between 175 mV and 225 mV at the highest current output, ILOAD. Assuming no additional resistance, the voltage dropped, VDROP (mV), on each pass • Adequate base drive. It is acceptable to use a lower level of current gain, hFE, for lower total load currents, ILOAD. The lower limit for ILOAD is limited by the minimum base current for the A8450, IBD(min), and the minimum hFE of the pass transistor, such that ILOAD = IBD(min) × 190 = 627 mW VREG RCL CL33 × hFE(min) Note that hFE is dependant on operating temperature. Lower temperatures decrease hFE, affecting the current capacity of the transistor. • Packaged for sufficient power dissipation. In order to ensure appropriate thermal handling, the design of the application must take into consideration the thermal characteristics of the PCB where the A8450 and pass transistors are mounted, the ambient temperature, and the power dissipation characteristics of the transistor packages. In general, the power dissipation, PD (mW), is estimated by PD = (VREG – VOUT) × ILOAD ILOAD A8450 V33BD V33 VCE VDROP VOUTV33 Figure 5. Placement of drop resistors for thermal protection; example shown is for the 3.3 V regulator. 11 A8450KLB-DS, Rev. 1 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A8450 Automotive Multioutput Voltage Regulator transistor is VDROP = VREG – VRCL – VOUT This can be substituted into the power dissipation formula PD = VDROP × ILOAD Given a typical application where VREG = 5.8 V, VRCL = 0.175 V, VOUT = 3.3 V, and ILOAD = 350 mA, then PD is approximately 814 mW. PD can be used to estimate the minimum required operating temperature rating for the transistor. The ability of a package to dissipate heat is approximated by the thermal resistance from the die (junction) to the ambient environment, RθJA (°C/W). This includes the significant effect of dissipation through the package leads and the PCB on which the transistor is mounted, and the state of the ambient air. The typical rating for a DPAK package is 32˚C/W. The expected self-induced temperature rise in the package, ∆TJ (°C), given PD = 0.814 W, is approximated as ∆TJ = PD In order to determine the resistance values for the currentlimiting and drop resistors, VRCL and VDROP can be expressed in terms of ILOAD(lim) × RCL) VRDROP = (ILOAD(lim) × RRDROP) VRCL = (ILOAD(lim) Assume a typical ILOAD = 350 mA. However, under normal operating conditions, the current limit set by RCL would be higher than the expected normal current, so assume ILOAD(lim) = 0.400 A and RCL = 44 Ω. Substituting to determine VRCL VRCL = 0.400 For a selected transistor, VCE can change depending on current, temperature, and transistor beta. Typically, transistors are rated at a minimum beta at a defined VCE. However, VCE should be calculated with some margin so there is always enough headroom to drive the device at the desired load. To provide an operating margin, or if a lower-value RCL is required, voltage drop resistors, RDROP, can be added to the circuit, between the RCL and the transistor (figure 5). It is also important to consider tolerances in resistance values and VREG. The level of VREG(min) is 5.6 V, at which level PD is reduced, but also the voltage available for VCE is reduced. Calculating maximum and minimum voltage drops is useful in determining the values of the drop resistors. The required drop resistor value, RRDROP , can be determined in terms of the voltage drops across each component of the circuit, as shown in the following formula VDROP ≥ VOUT VDROP = VREG – VRCL – VRDROP – VCE × 0.44 = 0.176 V We can now solve for RRDROP and then VDROP × RRDROP) – VCE ≥ VOUT 5.8 – 0.176 – (0.4 × RRDROP) – 1 ≥ 3.30 V VREG – VRCL – (ILOAD × RθJA= 26°C In automotive applications, where under-the-hood ambient temperatures can exceed 125˚C, the pass transistor would have to be rated to provide the required beta at ≥ 151°C, plus a safe operating margin. where Assume that VREG(max) = 5.8 V and VOUT(max) = 3.3 V. Assume also that TA = 125°C, and VCE = 1V (as specified for the MPSW06 npn transistor, beta = 300 at 125˚C). therefore RRDROP ≥ 3.31 Ω and VRDROP = 0.4 × 3.31 = 1.3 V Using four 0.25 W resistors valued at 14.7 Ω in parallel will drop 1.3 volts. Using the drop resistors as calculated above, the power dissipation in the transistor, PD (W) is reduced to PD = ILOAD(lim) = 0.400 × (VREG – VRCL – VRDROP – VOUT) × (5.8 – 0.176 – 1.3 – 3.3) = 0.410 W and ∆TJ = PD × RθJA= 13°C The power dissipated in the transistor is significantly reduced. A transistor in a power package with an RθJA of 32˚C/W at 400 mA (a 50 mA margin) undergoes a temperature rise of 13˚C with the drop resistors, as opposed to a similar transistor at 350 mA rising 26˚C without drop resistors. At high output currents, properly selected drop resistors can protect the external pass transitor from overheating. 12 A8450KLB-DS, Rev. 1 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A8450 Automotive Multioutput Voltage Regulator A8450 Power Dissipation. The A8450 is designed to operate in applications with high ambient temperatures. The total power dissipated in the device must be considered in conjunction with the thermal dissipation capabilities of the PCB where the A8450 is mounted, as well as the capabilities of the device package itself. The ability of a package to dissipate heat is approximated by the thermal resistance from the die (junction) to the ambient environment, RθJA (°C/W). This includes the significant effect of dissipation through the package leads and the PCB on which the package is mounted, and the temperature of the ambient air. Test results for this 24-lead SOIC are approximately 35 °C/W when mounted on a high-thermally conductive PCB (based on the JEDEC standard PCB, having four layers with buried copper areas). The total power that can be applied to the device, PD(lim) (W), is affected by the maximum allowable device junction temperature, TJ(max) (°C), RθJA , and the ambient air temperature, TA (°C), as shown in the following formula PD(lim) = (TJ(max) – TA) ⁄ RθJA PD(lim) can be estimated based on several parameters, using the following formula PD(lim) = PD(Ibias) + PD(V5A) + PD(V5D) + PD(buckdc) + PD(buckac) + PD(BD) where PD(Ibias) = VBB × IBB × ILOAD(V5A) PD(V5D) = (VREG – 5 V) × ILOAD(V5D) PD(buckdc)= ILOAD2 × RDSON(TJmax) × DC PD(buckac)= ILOAD × [VBB( 5 ns ⁄ 14 V) × VBB] ×0.5 fPWM PD(BD) = IV33BD(max) × (VREG – 4 V) + IVADJBD(max) × (VREG – VADJ – 0.7 V) PD(V5A) = (VREG – 5 V) and ILOAD = ILOAD(V33) + ILOAD(VADJ) + ILOAD(V5D) + ILOAD(V5A) RDSON is a function of TJ. For the purposes of estimating PD(lim), the relationship can be assumed to be linear throughout the practical TJ operating range (see test conditions for RDSON in the Electrical Characteristics table). DC (duty cycle) is a function of VBB and VREG. This can be calculated precisely as DC = VREG(off) ⁄ (VREG(on) + VREG(off) ) A rough estimate for DC is DC = (VREG + VLX) ⁄ VBB IV33BD(max) is the maximum current drawn on the V33BD pin. It is dependent on IOUTV33 and the hFE of the pass transistor. IADJBD(max) is the maximum current drawn on the VADJBD pin. It is dependent on IOUTVADJ and the hFE of the pass transistor. Overcurrent Protection The current supplied by the 3.3 V and the 1.2 to 3.3 V adjustable regulators is limited to ICL. Current above ICL is folded back linearly, as shown in figure 4b. In the case of a shorted load, the collector current is reduced to 40% of ICL ±10% , to ensure protection of the pass transistors. After the short is removed, the voltage recovers to its regulated level. The maximum power dissipated in the transistor during a shorted load condition is: PD ≈ (VREG – VOUT) × (0.4 × ICL) where VOUT = 0 V. Low Input Voltage Operation When the charge pump has ramped enough to enhance the buck switch, the buck converter switching regulator is enabled. This occurs at VBB ≈ 5.7 V. At that point, the duty cycle, DC, of the A8450 can be forced to 100% until VIN is high enough to allow the switch to begin operating normally. The point at which normal switching begins is dependent on ambient temperature, TA. Increases in TA cause RDSON to increase. Other significant factors are ILOAD, VREG, the ESR of the output inductor (L1), and the forward biasing voltage for the output Schottky diode (D1). 13 A8450KLB-DS, Rev. 1 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A8450 Automotive Multioutput Voltage Regulator Regulator Bypass Some applications may not require the use of all four regulators provided in the A8450. For the regulators that are not used, the corresponding external components are not needed. If either or both of the two 5 V regulators are not required by the application, bypass an unused regulator by not connecting its output terminal, V5D or V5A. Also, the corresponding output capacitor, C1 or C2, is not used. regulator, if either or both are not needed, the corresponding external components are not used. In addition, if the 3.3 V regulator is not used, CL33 and V33 are not connected. If the adjustable regulator is not used, CLADJ and FB are not connected. However, to ensure stability of the A8450, the base drive pin, V33BD or VADJBD, of any unused regulator must be shorted to VREG. For the 3.3 V regulator and the 1.2 V to 3.3 V adjustable Pin List Table Name Description Number VBB Supply input 1 CP2 Charge pump capacitor, positive side 2 CP1 Charge pump capacitor, negative side 3 VCP Charge pump output used to drive N-channel buck converter transistor 4 Internal reference 5 GND Power ground 6 GND Power ground 7 VREG11 Logic control 8 CPOR ENB Connection for POR adjustment 9 CLADJ Current limit for adjustable regulator 10 Base drive for adjustable regulator pass transistor 11 FB Feedback for adjustable regulator 12 V5A 5 V analog regulator output 13 NPOR Power on Reset logic output 14 Diagnostic output; open drain; low during fault condition 15 5 V digital regulator output 16 dc-to-dc converter supply output 17 GND Power ground 18 GND Power ground 19 CL33 Current limit for 3.3 V regulator 20 Base drive for 3.3 V regulator pass transistor 21 3.3 V regulator output 22 VADJBD NFAULT V5D VREG V33BD V33 ENBAT LX High voltage logic control 23 Buck converter switching regulator output 24 14 A8450KLB-DS, Rev. 1 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A8450 Automotive Multioutput Voltage Regulator 24-Pin SOIC 15.40 BSC 24 8º 0º 19 18 0.33 0.20 7.50 BSC 1.27 0.40 10.30 BSC 1 0.51 0.31 2 6 7 2.65 2.35 0.64 BSC 1.27 BSC 0.30 0.10 Dimensions in millimeters Conform to JEDEC MS-013AD Actual dimensions may vary at vendor discretion Leads 6, 7, 18, and 19 are internally fused ground leads, for enhanced thermal dissipation. Exact external appearance subject to vendor discretion. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright©2004 AllegroMicrosystems, Inc. 15 A8450KLB-DS, Rev. 1 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com