ALLEGRO UCN5811

Data Sheet
26182.20B
5811
BiMOS II 12-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
OUT 11
1
20
OUT 10
OUT 12
2
19
OUT 9
BLANKING
3
18
OUT 8
SERIAL
DATA OUT
4
17
OUT 7
SERIAL
DATA IN
5
LOGIC
SUPPLY
6
VDD
CLOCK
7
STROBE
8
OUT 1
OUT 2
LATCHES
REGISTER
BLNK
VBB 16
LOAD
SUPPLY
15
GROUND
CLK
14
OUT 6
ST
13
OUT 5
9
12
OUT 4
10
11
OUT 3
Dwg. PP-029-5
Designed primarily for use with vacuum-fluorescent displays, the
UCN5811A smart power BiMOS II driver features low-output saturation
voltages and high output switching speed. These devices contain CMOS shift
registers, data latches, and control circuitry, and bipolar high-speed sourcing
outputs with DMOS active pull-down circuitry. The high-speed shift register
and data latches allow direct interface with microprocessor-based systems. A
CMOS serial data output enables cascade connections in applications requiring additional drive lines.
The UCN5811A features 60 V and -40 mA output ratings, allowing it to
be used in many other peripheral power driver applications. It can be used as
an improved replacement tor the SN75512B. The Allegro devices do not
require special power-up sequencing.
The UCN5811A has been designed with BiMOS II logic for improved
data entry rates. With a 5 V supply, it will operate to at least 3.3 MHz. At
12 V, higher speeds are possible. Use of this device with TTL may require
the use of appropriate pull-up resistors to ensure a proper input logic high.
This device is supplied in a 20-pin plastic dual in-line package. It can be
operated over the ambient temperature range of -20°C to +85°C. Copper lead
frames and low output saturation voltages allow all outputs to be operated at
25 mA continuously at ambient temperatures of up to 76°C.
FEATURES
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage,VDD ..................... 15 V
Driver Supply Voltage, VBB ................... 60 V
Continuous Output Current,
■
■
■
■
■
■
To 3.3 MHz Data Input Rate
Low-Power CMOS Logic and Latches
High-Speed Source Drivers
Active Pull-Downs
Low-Output Saturation Voltages
Improved Replacement for SN75512B
IOUT ......................... -40 mA to +25 mA
Input Voltage Range,
VIN ....................... -0.3 V to VDD + 0.3 V
Package Power Dissipation,
PD ........................................ See Graph
Operating Temperature Range,
TA ................................. -20°C to +85°C
Storage Temperature Range,
TS ............................... -55°C to +150°C
Always order by complete part number:
UCN5811A .
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
5811
BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FUNCTIONAL BLOCK DIAGRAM
2.5
2.0
V DD
CLOCK
1.5
SERIAL
DATA IN
SERIAL-PARALLEL SHIFT REGISTER
STROBE
LATCHES
LOGIC
SUPPLY
SERIAL
DATA OUT
R
θJ
A
=
55
°C
/W
BLANKING
1.0
MOS
BIPOLAR
0.5
VBB
0
25
50
75
100
125
AMBIENT TEMPERATURE IN °C
150
GROUND
OUT 1 OUT 2 OUT 3
OUT N
LOAD
SUPPLY
Dwg. FP-013-1
Dwg. GS-004-1
TYPICAL INPUT CIRCUIT
VDD
IN
TIMING WAVESHAPES
Dwg. EP-010-5
TYPICAL OUTPUT DRIVER
Dwg. W-184
Dwg. W-182
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2000 Allegro MicroSystems, Inc.
5811
BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 60 V (unless otherwise noted).
Limits @ VDD = 5 V
Characteristic
Symbol
Output Leakage Current
Output Voltage
Output Pull-Down Current
Input Voltage
Input Current
Serial Data Output Voltage
Limits @ VDD = 12 V
Test Conditions
Mln.
Typ.
Max.
Min.
Typ.
Max.
Units
ICEX
VOUT = 0 V, TA = +70°C
—
-5.0
-15
—
-5.0
-15
µA
VOUT(H)
IOUT = -25 mA, VBB = 60 V
58
58.5
—
58
58.5
—
V
VOUT(L)
IOUT = 1 mA
—
2.0
3.0
—
—
—
V
IOUT = 2 mA
—
—
—
—
2.0
3.0
V
VOUT = 10 V to VBB
2.5
4.0
—
—
—
—
mA
VOUT = 40 V to VBB
—
—
—
15
18
—
mA
VIN(1)
3.5
—
5.3
10.5
—
12.3
V
VIN(0)
-0.3
—
+0.8
-0.3
—
+0.8
V
IOUT(L)
IIN(1)
VIN = VDD
—
0.05
0.5
—
0.1
1.0
µA
IIN(0)
VIN = 0.8 V
—
-0.05
-0.5
—
-1.0
-1.0
µA
VOUT(H)
IOUT = -200 µA
4.5
4.7
—
11.7
11.8
—
V
VOUT(L)
IOUT = 200 µA
—
200
250
—
100
200
mV
3.3*
—
—
—
—
—
MHz
Maximum Clock Frequency
fclk
Supply Current
IDD(H)
All Outputs High
—
3.0
5.0
—
15
20
mA
IDD(L)
All Outputs Low
—
2.5
4.0
—
7.0
10
mA
IBB(H)
Outputs High, No Load
—
7.5
12
—
7.5
12
mA
IBB(L)
Outputs Low
—
10
100
—
10
100
µA
tPHL
CL = 30 pF
—
300
550
—
125
150
ns
tPLH
CL = 30 pF
—
250
450
—
170
200
ns
Output Fall Time
tf
CL = 30 pF
—
1000
1250
—
250
300
ns
Output Rise Time
tr
CL = 30 pF
—
150
170
—
150
170
ns
Blanking to Output Delay
Negative current is defined as coming out of (sourcing) the specified device pin.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
www.allegromicro.com
5811
BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS
CLOCK
A
B
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
D
DATA IN
E
F
C
STROBE
BLANKING
G
OUTN
Dwg. No. 12,649A
TIMING REQUIREMENTS
(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) .......................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................. 75 ns
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width ............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
Information present at any register is transferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the BLANKING input be high during
serial data entry.
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON, the information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
Output Transistion ......................................................................... 500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
Serial
Data Strobe
Output Input
Latch Contents
I1
I2
I3
...
IN-1
Output Contents
IN Blanklng
H
H
R1 R2 ...
RN-2 RN-1
RN-1
L
L
R1 R2 ...
RN-2 RN-1
RN-1
X
R1 R2 R3 ...
RN-1 RN
RN
X
X
X
L
R1 R2 R3 ...
RN-1 RN
PN
H
P1 P2 P3 ...
X X X ...
PN-1 PN
X
X
X
X
...
P1 P2 P3 ...
X
PN-1 PN
PN
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
L
H
R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
I1 I2 I3 ... IN-1 IN
P1 P2 P3 ... PN-1
L L L ... L
L
5811
BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS
UCN5811A
Dimensions in Inches
(controlling dimensions)
20
0.014
0.008
11
0.430
MAX
0.280
0.240
0.300
BSC
1
0.070
0.045
0.100
1.060
0.980
10
BSC
0.005
MIN
0.210
MAX
0.150
0.115
0.015
MIN
0.022
0.014
NOTES: 1.
2.
3.
4.
Exact body and lead configuration at vendor’s option within limits shown.
Lead spacing tolerance is non-cumulative.
Lead thickness is measured at seating plane or below.
Supplied in standard sticks/tubes of 18 devices.
www.allegromicro.com
Dwg. MA-001-20 in
5811
BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS
UCN5811A
Dimensions in Millimeters
(for reference only)
0.355
0.204
11
20
10.92
MAX
7.11
6.10
7.62
BSC
1
1.77
1.15
2.54
26.92
24.89
10
BSC
0.13
MIN
5.33
MAX
3.81
2.93
0.39
MIN
0.558
0.356
NOTES: 1.
2.
3.
4.
Dwg. MA-001-20 mm
Exact body and lead configuration at vendor’s option within limits shown.
Lead spacing tolerance is non-cumulative.
Lead thickness is measured at seating plane or below.
Supplied in standard sticks/tubes of 18 devices.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5811
BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
www.allegromicro.com
5811
BiMOS II 12-BIT
SERIAL-INPUT,
LATCHED SOURCE DRIVERS
POWER
INTERFACE DRIVERS
Function
Output Ratings*
Part Number†
SERIAL-INPUT LATCHED DRIVERS
8-Bit (saturated drivers)
8-Bit
8-Bit
8-Bit
8-Bit
8-Bit (constant-current LED driver)
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)
-120 mA
350 mA
350 mA
350 mA
350 mA
75 mA
250 mA
350 mA
100 mA
50 V‡
50 V
80 V
50 V‡
80 V‡
17 V
50 V
50 V‡
50 V
5895
5821
5822
5841
5842
6275
6595
6A595
6B595
10-Bit (active pull-downs)
-25 mA
60 V
5810-F and 6809/10
12-Bit (active pull-downs)
-25 mA
60 V
5811 and 6811
75 mA
17 V
6276
20-Bit (active pull-downs)
-25 mA
60 V
5812-F and 6812
32-Bit (active pull-downs)
32-Bit
32-Bit (saturated drivers)
-25 mA
100 mA
100 mA
60 V
30 V
40 V
5818-F and 6818
5833
5832
16-Bit (constant-current LED driver)
PARALLEL-INPUT LATCHED DRIVERS
4-Bit
350 mA
50 V‡
5800
8-Bit
8-Bit
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)
-25 mA
350 mA
100 mA
250 mA
60 V
50 V‡
50 V
50 V
5815
5801
6B273
6273
SPECIAL-PURPOSE DEVICES
Unipolar Stepper Motor Translator/Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 28-Line Decoder/Driver
1.25 A
250 mA
350 mA
100 mA
450 mA
50 V‡
50 V
50 V‡
50 V
30 V
5804
6259
6A259
6B259
6817
*
Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.
Negative current is defined as coming out of (sourcing) the output.
†
Complete part number includes additional characters to indicate operating temperature range and package style.
‡
Internal transient-suppression diodes included for inductive-load protection.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000