$6/9 $XJXVW $GYDQFHG,QIRUPDWLRQ 90î0î&026)ODVK((3520 )HDWXUHV • Organization: 2M×8 / 1M×16 • Sector architecture - One 16K; two 8K; one 32K; and thirty-one 64K byte sectors - One 8K; two 4K; one 16K; and thirty-one 32K word sectors - Boot code sector architecture—T (top) or B (bottom) - Erase any combination of sectors or full chip • Single 2.7-3.6V power supply for read/write operations • Sector protection • High speed 70/80/90/120 ns address access time • Automated on-chip programming algorithm - Automatically programs/verifies data at specified address • Automated on-chip erase algorithm - Automatically preprograms/erases chip or specified sectors • Hardware RESET pin - Resets internal state machine to read mode 3LQDUUDQJHPHQW 48-pin TSOP Erase voltage generator Input/output buffers Reset VSS A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 RESET Program/erase control BYTE Command register Program voltage generator $6/9 STB Chip enable Output enable Logic CE OE STB Timer Data latch Y decoder Y gating X decoder Cell matrix 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC detector Address latch WE DQ0–DQ15 (A-1) 44-pin SO A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE RESET NC NC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 RY/BY VCC Sector protect/ erase voltage switches 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 WE A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 A0–A19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 $6/9 /RJLFEORFNGLDJUDP • Low power consumption - 200 nA typical automatic sleep mode current - 200 nA typical standby current - 10 mA typical read current • JEDEC standard software, packages and pinouts - 48-pin TSOP - 44-pin SO (availability TBD) • CFI (Common Flash Interface) compliant • Detection of program/erase cycle completion - DQ7 DATA polling - DQ6 toggle bit - RY/BY output • Erase suspend/resume - Supports reading data from or programming data to a sector not being erased • Low VCC write lock-out below 1.5V • 10 year data retention at 150C • 100,000 write/erase cycle endurance 6HOHFWLRQJXLGH 29LV160-70 29LV160-80 29LV160-90 29LV160-120 Unit Maximum access time tAA 70 80 90 120 ns Maximum chip enable access time tCE 70 80 90 120 ns Maximum output enable access time tOE 30 30 35 50 ns 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 1 of 29 &RS\ULJKW$OOLDQFH6HPLFRQGXFWRU$OOULJKWVUHVHUYHG $6/9 )XQFWLRQDOGHVFULSWLRQ The AS29LV160 is a 16 megabit, 3.0 volt Flash memory organized as 2 Megabyte of 8 bits/1 Megabyte of 16 bits each. For flexible erase and program capability, the 8 megabits of data is divided into thirty-five sectors: one 16K, two 8K, one 32K, and thirty-one 64k byte sectors; or one 8K, two 4K, one 16K, and thirty-one 32K word sectors. The ×8 data appears on DQ0–DQ7; the ×16 data appears on DQ0–DQ15. The AS29LV160 is offered in JEDEC standard 48-pin TSOP, 48-pin BGA, and 44-pin SO (availability TBD) packages. This device is designed to be programmed and erased in-system with a single 3.0V VCC supply. The device can also be reprogrammed in standard EPROM programmers. The AS29LV160 offers access times of 70/80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. Word mode (×16 output) is selected by BYTE = high. Byte mode (×8 output) is selected by BYTE = low. The AS29LV160 is fully compatible with the JEDEC single power supply Flash standard. Write commands are sent to the command register using standard microprocessor write timings. An internal state-machine uses register contents to control the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Read data from the device occurs in the same manner as other Flash or EPROM devices. Use the program command sequence to invoke the automated on-chip programming algorithm that automatically times the program pulse widths and verifies proper cell margin. Use the erase command sequence to invoke the automated on-chip erase algorithm that preprograms the sector (if it is not already programmed before executing the erase operation), times the erase pulse widths, and verifies proper cell margin. Boot sector architecture enables the system to boot from either the top (AS29LV160T) or the bottom (AS29LV160B) sector. Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both program and erase operations in all, or any combination of, the nineteen sectors. The device provides true background erase with Erase Suspend, which puts erase operations on hold to either read data from, or program data to, a sector that is not being erased. The chip erase command will automatically erase all unprotected sectors. A factory shipped AS29LV160 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other sectors. The device features single 3.0V power supply operation for Read, Write, and Erase functions. Internally generated and regulated voltages are provided for the Program and Erase operations. A low VCC detector automatically inhibits write operations during power transtitions. The RY/BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect end of program or erase operations. The device automatically resets to the read mode after program/erase operations are completed. DQ2 indicates which sectors are being erased. The AS29LV160 resists accidental erasure or spurious programming signals resulting from power transitions. Control register architecture permits alteration of memory contents only after successful completion of specific command sequences. During power up, the device is set to read mode with all program/erase commands disabled when VCC is less than VLKO (lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. To initiate write commands, CE and WE must be logical zero and OE a logical 1. When the device’s hardware RESET pin is driven low, any program/erase operation in progress is terminated and the internal state machine is reset to read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an automated on-chip program/erase algorithm, data in address locations being operated on may become corrupted and requires rewriting. Resetting the device enables the system’s microprocessor to read boot-up firmware from the Flash memory. The AS29LV160 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are programmed one at a time using EPROM programming mechanism of hot electron injection. 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 2 of 29 $6/9 2SHUDWLQJPRGHV Mode CE OE WE A0 A1 A6 A9 RESET ID read MFR code L L H L L L VID H Code ID read device code L L H H L L VID H Code Read L L H A0 A1 A6 A9 H DOUT Standby H X X X X X X H High Z Output disable L H H X X X X H High Z Write L H L A0 A1 A6 A9 H DIN Enable sector protect L VID Pulse/L L H L VID H X Sector unprotect L VID Pulse/L L H H VID H X Temporary sector unprotect X X X X X X X VID X L L H L H L VID H Code L L H L H H VID H Code X X X X X X X L High Z Verify sector protect† Verify sector unprotect † Hardware Reset DQ L = Low (<VIL) = logic 0; H = High (>VIH) = logic 1; VID = 10.0 ± 1.0V; X = don’t care. In ×16 mode, BYTE = VIH. In ×8 mode, BYTE = VIL with DQ8-DQ14 in high Z and DQ15 = A-1. †Verification of sector protect/unprotect during A9 = V ID. 0RGHGHILQLWLRQV Item Description ID MFR code, device code Selected by A9 = VID(9.5V–10.5V), CE = OE = A1 = A6 = L, enabling outputs. When A0 is low (VIL) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products. When A0 is high (VIH), DOUT represents the device code for the AS29LV160. Read mode Selected with CE = OE = L, WE = H. Data is valid in tACC time after addresses are stable, tCE after CE is low and tOE after OE is low. Standby Selected with CE = H. Part is powered down, and ICC reduced to <1.0 µA when CE = VCC ± 0.3V = RESET. If activated during an automated on-chip algorithm, the device completes the operation before entering standby. Output disable Part remains powered up; but outputs tri-stated with OE pulled high. Write Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command register. Contents of command register serve as inputs to the internal state machine. Address latching occurs on the falling edge of WE or CE, whichever occurs later. Data latching occurs on the rising edge WE or CE, whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands. Enable sector protect Hardware protection circuitry implemented with external programming equipment causes the device to disable program and erase operations for specified sectors. For in-system sector protection, refer to Sector protect algorithm on page 15. Disables sector protection for all sectors using external programming equipment. All sectors must be Sector unprotect protected prior to sector unprotection. For in-system sector unprotection, refer to Sector unprotect algorithm on page 15. 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 3 of 29 $6/9 Item Description Verify sector protect/ unprotect Verifies write protection for sector. Sectors are protected from program/erase operations on commercial programming equipment. Determine if sector protection exists in a system by writing the ID read command sequence and reading location XXX02h, where address bits A12–18 select the defined sector addresses. A logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector. Temporarily disables sector protection for in-system data changes to protected sectors. Apply +10V to RESET Temporary to activate temporary sector unprotect mode. During temporary sector unprotect mode, program protected sector unprotect sectors by selecting the appropriate sector address. All protected sectors revert to protected state on removal of +10V from RESET. RESET Resets the interal state machine to read mode. If device is programming or erasing when RESET = L, data may be corrupted. Deep power down Hold RESET low to enter deep power down mode (<1 µA). Recovery time to start of first read cycle is 50ns. Enabled automatically when addresses remain stable for 300ns. Typical current draw is 1 µA with no current Automatic sleep drawn by the external devices from teh output pin. Existing data is available to the system during this mode. mode If an address is changed, automatic sleep mode is disabled and new data is returned within standard access times. )OH[LEOH6HFWRU$UFKLWHFWXUH Bottom boot sector architecture (AS29LV160B) Top boot sector architecture (AS29LV160T) Sector ×8 ×16 Size (Kbytes) ×8 ×16 Size (Kbytes) 0 000000-003FFF 00000-01FFF 16 000000-00FFFF 00000-07FFF 64 1 004000-005FFF 02000-02FFF 8 010000-01FFFF 08000-0FFFF 64 2 006000-007FFF 03000-03FFF 8 020000-02FFFF 10000-17FFF 64 3 008000-00FFFF 04000-07FFF 32 030000-03FFFF 18000-1FFFF 64 4 010000-01FFFF 08000-0FFFF 64 040000-04FFFF 20000-27FFF 64 5 020000-02FFFF 10000-17FFF 64 050000-05FFFF 28000-2FFFF 64 6 030000-03FFFF 18000-1FFFF 64 060000-06FFFF 30000-37FFF 64 7 040000-04FFFF 20000-27FFF 64 070000-07FFFF 38000-3FFFF 64 8 050000-05FFFF 28000-2FFFF 64 080000-08FFFF 40000-47FFF 64 9 060000-06FFFF 30000-37FFF 64 090000-09FFFF 48000-4FFFF 64 10 070000-07FFFF 38000-3FFFF 64 0A0000-0AFFFF 50000-57FFF 64 11 080000-08FFFF 40000-47FFF 64 0B0000-0BFFFF 58000-5FFFF 64 12 090000-09FFFF 48000-4FFFF 64 0C0000-0CFFFF 60000-67FFF 64 13 0A0000-0AFFFF 50000-57FFF 64 0D0000-0DFFFF 68000-6FFFF 64 14 0B0000-0BFFFF 58000-5FFFF 64 0E0000-0EFFFF 70000-77FFF 64 15 0C0000-0CFFFF 60000-67FFF 64 0F0000-0FFFFF 78000-7FFFF 64 16 0D0000-0DFFFF 68000-6FFFF 64 100000-10FFFF 80000-87FFF 64 17 0E0000-0EFFFF 70000-77FFF 64 110000-11FFFF 88000-8FFFF 64 18 0F0000-0FFFFF 78000-7FFFF 64 120000-12FFFF 90000-97FFF 64 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 4 of 29 $6/9 Bottom boot sector architecture (AS29LV160B) Top boot sector architecture (AS29LV160T) Sector ×8 ×16 Size (Kbytes) ×8 ×16 Size (Kbytes) 19 100000-10FFFF 80000-87FFF 64 130000-13FFFF 98000-9FFFF 64 20 110000-11FFFF 88000-8FFFF 64 140000-14FFFF A0000-A7FFF 64 21 120000-12FFFF 90000-97FFF 64 150000-15FFFF A8000-AFFFF 64 22 130000-13FFFF 98000-9FFFF 64 160000-16FFFF B0000-B7FFF 64 23 140000-14FFFF A0000-A7FFF 64 170000-17FFFF B8000-BFFFF 64 24 150000-15FFFF A8000-AFFFF 64 180000-18FFFF C0000-C7FFF 64 25 160000-16FFFF B0000-B7FFF 64 190000-19FFFF C8000-CFFFF 64 26 170000-17FFFF B8000-BFFFF 64 1A0000-1AFFFF D0000-D7FFF 64 27 180000-18FFFF C0000-C7FFF 64 1B0000-1BFFFF D8000-DFFFF 64 28 190000-19FFFF C8000-CFFFF 64 1C0000-1CFFFF E0000-E7FFF 64 29 1A0000-1AFFFF D0000-D7FFF 64 1D0000-1DFFFF E8000-EFFFF 64 30 1B0000-1BFFFF D8000-DFFFF 64 1E0000-1EFFFF F0000-F7FFF 64 31 1C0000-1CFFFF E0000-E7FFF 64 1F0000-1F7FFF F8000-FBFFF 32 32 1D0000-1DFFFF E8000-EFFFF 64 1F8000-1F9FFF FC000-FCFFF 8 33 1E0000-1EFFFF F0000-F7FFF 64 1FA000-1FBFFF FD000-FDFFF 8 34 1F0000-1FFFFF F8000-FFFFF 64 1FC000-1FFFFF FE000-FFFFF 16 In word mode, there are one 8K word, two 4K word, one 16K word, and fifteen 32K word sectors. Address range is A19–A-1 if BYTE = VIL; address range is A19–A0 if BYTE = VIH. ,'6HFWRUDGGUHVVWDEOH Bottom boot sector architecture Top boot sector architecture (AS29LV160B) (AS29LV160T) Sector A19 A18 A17 A16 A15 A14 A13 A12 A19 A18 A17 A16 A15 A14 A13 A12 0 0 0 0 0 0 0 0 X 0 0 0 0 0 X X X 1 0 0 0 0 0 0 1 0 0 0 0 0 1 X X X 2 0 0 0 0 0 0 1 1 0 0 0 1 0 X X X 3 0 0 0 0 0 1 X X 0 0 0 1 1 X X X 4 0 0 0 0 1 X X X 0 0 1 0 0 X X X 5 0 0 0 1 0 X X X 0 0 1 0 1 X X X 6 0 0 0 1 1 X X X 0 0 1 1 0 X X X 7 0 0 1 0 0 X X X 0 0 1 1 1 X X X 8 0 0 1 0 1 X X X 0 1 0 0 0 X X X 9 0 0 1 1 0 X X X 0 1 0 0 1 X X X 10 0 0 1 1 1 X X X 0 1 0 1 0 X X X 11 0 1 0 0 0 X X X 0 1 0 1 1 X X X 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 5 of 29 $6/9 Bottom boot sector architecture Top boot sector architecture (AS29LV160B) (AS29LV160T) Sector 12 0 1 0 0 1 X X X 0 1 1 0 0 X X X 13 0 1 0 1 0 X X X 0 1 1 0 1 X X X 14 0 1 0 1 1 X X X 0 1 1 1 0 X X X 15 0 1 1 0 0 X X X 0 1 1 1 1 X X X 16 0 1 1 0 1 X X X 1 0 0 0 0 X X X 17 0 1 1 1 0 X X X 1 0 0 0 1 X X X 18 0 1 1 1 1 X X X 1 0 0 1 0 X X X 19 1 0 0 0 0 X X X 1 0 0 1 1 X X X 20 1 0 0 0 1 X X X 1 0 1 0 0 X X X 21 1 0 0 1 0 X X X 1 0 1 0 1 X X X 22 1 0 0 1 1 X X X 1 0 1 1 0 X X X 23 1 0 1 0 0 X X X 1 0 1 1 1 X X X 24 1 0 1 0 1 X X X 1 1 0 0 0 X X X 25 1 0 1 1 0 X X X 1 1 0 0 1 X X X 26 1 0 1 1 1 X X X 1 1 0 1 0 X X X 27 1 1 0 0 0 X X X 1 1 0 1 1 X X X 28 1 1 0 0 1 X X X 1 1 1 0 0 X X X 29 1 1 0 1 0 X X X 1 1 1 0 1 X X X 30 1 1 0 1 1 X X X 1 1 1 1 0 X X X 31 1 1 1 0 0 X X X 1 1 1 1 1 0 X X 32 1 1 1 0 1 X X X 1 1 1 1 1 1 0 0 33 1 1 1 1 0 X X X 1 1 1 1 1 1 0 1 34 1 1 1 1 1 X X X 1 1 1 1 1 1 1 X 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 6 of 29 $6/9 &RPPDQGIRUPDWELWPRGH Bus Write Operations1 Command Length 1st bus cycle 2nd bus cycle Address Data 1 X F0 3 555 AA 2AA Auto Select 3 555 AA Program 4 555 Unlock Bypass 3 Unlock Bypass Program 4th bus cycle 5th bus cycle 6th bus cycle Address Data 55 X FO 2AA 55 555 90 *2 *2 AA 2AA 55 555 A0 PA PD 555 AA 2AA 55 555 20 2 X A0 PA PD Unlock Bypass Reset 2 X 90 X OO Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Block Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30 CFI Query 1 X 98 Read/Reset Address Data 3rd bus cycle Address Data Address Data Address Data Key: L =Low (<VIL); H = High (>VIH); X =Don’t care )RXUWKEXVF\FOHLQWKHDXWRVHOHFWPRGHLVDUHDGF\FOHZLWKWKHIROORZLQJH[SHFWHGGDWDVHHQH[WWDEOH7KHUHFDQEHVXFFHVVLYHUHDGF\FOHVZLWKDGGUHVV; ;;LQDQ\RUGHU 5($'FRGHV Mode A19–A12 A6 A1 A0 Code 1 L L L 52h ×8 T boot X L L H CAh ×8 B boot X L L H 49h ×16 T boot X L L H 22C4h ×16 B boot X L L H 2249h Sector address L H L 01h protected 00h unprotected MFR code (Alliance Semiconductor) Device code X Sector protection Key: L =Low (<VIL); H = High (>VIH); X =Don’t care 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 7 of 29 $6/9 &RPPDQGIRUPDWELWPRGH Bus Write Operations1 Command Length 1st bus cycle 2nd bus cycle Address Data 1 X F0 3 AAA AA 555 Auto Select 3 AAA AA Program 4 AAA Unlock Bypass 3 Unlock Bypass Program 4th bus cycle 5th bus cycle 6th bus cycle Address Data 55 X FO 555 55 AAA 90 *2 * AA 555 55 AAA A0 PA PD AAA AA 555 55 AAA 20 2 X A0 PA PD Unlock Bypass Reset 2 X 90 X OO Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Block Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30 CFI query 1 X 98 Read/Reset Address Data 3rd bus cycle Address Data Address Data Address Data [ 'RQ¶WFDUH3$ 3URJUDPDGGUHVV%$ $Q\DGGUHVVLQWKHEORFN 6HHIRRWQRWH³´RQSUHFHHGLQJSDJH)RXUWKEXVF\FOHLQWKHDXWRVHOHFWPRGHLVDUHDGF\FOHZLWKWKHGDWDLQWKH³5($'FRGHVWDEOH´RQWKHSUFHHGLQJSDJH H[SHFWHG 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 8 of 29 $6/9 &RPPDQGGHILQLWLRQV Item Description Reset/Read Initiate read or reset operations by writing the Read/Reset command sequence into the command register. This allows the microprocessor to retrieve data from the memory. Device remains in read mode until command register contents are altered. Device automatically powers up in read/reset state. This feature allows only reads, therefore ensuring no spurious memory content alterations during power up. AS29LV160 provides manufacturer and device codes in two ways. External PROM programmers typically access the device codes by driving +10V on A9. AS29LV160 also contains an ID Read command to read the device code with only +3V, since multiplexing +10V on address lines is generally undesirable. ID Read Initiate device ID read by writing the ID Read command sequence into the command register. Follow with a read sequence from address XXX00h to return MFR code. Follow ID Read command sequence with a read sequence from address XXX01h to return device code. To verify write protect status on sectors, read address XXX02h. Sector addresses A19–A12 produce a 1 on DQ0 for protected sector and a 0 for unprotected sector. Exit from ID read mode with Read/Reset command sequence. Hardware Reset Holding RESET low for 500 ns resets the device, terminating any operation in progress; data handled in the operation is corrupted. The internal state machine resets 20 µs after RESET is driven low. RY/BY remains low until internal state machine resets. After RESET is set high, there is a delay of 50 ns for the device to permit read operations. Programming the AS29LV160 is a four bus cycle operation performed on a byte-by-byte or wordby-word basis. Two unlock write cycles precede the Program Setup command and program data write cycle. Upon execution of the program command, no additional CPU controls or timings are necessary. Addresses are latched on the falling edge of CE or WE, whichever is last; data is latched on the rising edge of CE or WE, whichever is first. The AS29LV160’s automated on-chip program algorithm provides adequate internally-generated programming pulses and verifies the programmed cell margin. Byte/word Programming Check programming status by sampling data on the RY/BY pin, or either the DATA polling (DQ7) or toggle bit (DQ6) at the program address location. The programming operation is complete if DQ7 returns equivalent data, if DQ6 = no toggle, or if RY/BY pin = high. The AS29LV160 ignores commands written during programming. A hardware reset occurring during programming may corrupt the data at the programmed location. AS29LV160 allows programming in any sequence, across any sector boundary. Changing data from 0 to 1 requires an erase operation. Attempting to program data 0 to 1 results in either DQ5 = 1 (exceeded programming time limits); reading this data after a read/reset operation returns a 0. When programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this state, a Reset command returns the device to read mode. 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 9 of 29 $6/9 &RPPDQGGHILQLWLRQV Item Description The unlock bypass feature increases the speed at which the system programs bytes or words to the device because it bypasses the first two unlock cycles of the standard program command sequence. To initiate the unlock bypass command sequence, two unlock cycles must be written, then followed by a third cycle which has the unlock bypass command, 20h. Unlock Bypass Command Sequence The device then begins the unlock bypass mode. In order to program in this mode, a two cycle unlock bypass program sequence is required. The first cycle has the unlock bypass program command, A0h. It is followed by a second cycle which has the program address and data. To program additional data, the same sequence must be followed. The unlock bypass mode has two valid commands, the Unlock Bypass Program command and the Unlock Bypass Reset command. The only way the system can exit the unlock bypass mode is by issuing the unlock bypass reset command sequence. This sequence involves two cycles. The first cycle contains the data, 90h. The second cycle contains the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data. Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional unlock write cycles; and finally the Chip Erase command. Chip Erase Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip erase algorithm is invoked with the Chip Erase command sequence, AS29LV160 automatically programs and verifies the entire memory array for an all-zero pattern prior to erase. The 29LV160 returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding time limit. Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles, and finally the Sector Erase command. Identify the sector to be erased by addressing any location in the sector. The address is latched on the falling edge of WE; the command, 30h is latched on the rising edge of WE. The sector erase operation begins after a sector erase time-out. Sector Erase To erase multiple sectors, write the Sector Erase command to each of the addresses of sectors to erase after following the six bus cycle operation above. Timing between writes of additional sectors must be less than the erase time-out period, or the AS29LV160 ignores the command and erasure begins. During the time-out period any falling edge of WE resets the time-out. Any command (other than Sector Erase or Erase Suspend) during time-out period resets the AS29LV160 to read mode, and the device ignores the sector erase command string. Erase such ignored sectors by restarting the Sector Erase command on the ignored sectors. The entire array need not be written with 0s prior to erasure. AS29LV160 writes 0s to the entire sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected sectors unaffected. AS29LV160 requires no CPU control or timing signals during sector erase operations. Automatic sector erase begins after sector erase time-out from the last rising edge of WE from the sector erase command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling address must be performed on addresses that fall within the sectors being erased. AS29LV160 returns to read mode after sector erase unless DQ5 is set high by exceeding the time limit. Common Flash Interface 8/30/01; V.0.9.5 In order to achieve long term system compatibility, certain information about the internal configuration of the memory is provided which can be accessed in this mode. According to this information, system software may be configured for both upward and downward compatibility with Flash in a similar family. CFI mode can be entered by issuing CFI command either from read or from autoselect mode. The system can read CFI information at the addresses given in the tables below. $OOLDQFH6HPLFRQGXFWRU P. 10 of 29 $6/9 &RPPDQGGHILQLWLRQV Item Description Erase Suspend allows interruption of sector erase operations to read data from or program data to a sector not being erased. Erase suspend applies only during sector erase operations, including the time-out period. Writing an Erase Suspend command during sector erase time-out results in immediate termination of the time-out period and suspension of erase operation. AS29LV160 ignores any commands during erase suspend other than Read/Reset, Program or Erase Resume commands. Writing the Erase Resume Command continues erase operations. Addresses are Don’t Care when writing Erase Suspend or Erase Resume commands. Erase Suspend AS29LV160 takes 0.2–15 µs to suspend erase operations after receiving Erase Suspend command. To determine completion of erase suspend, either check DQ6 after selecting an address of a sector not being erased, or poll RY/BY. Check DQ2 in conjunction with DQ6 to determine if a sector is being erased. AS29LV160 ignores redundant writes of Erase Suspend. While in erase-suspend mode, AS29LV160 allows reading data (erase-suspend-read mode) from or programming data (erase-suspend-program mode) to any sector not undergoing sector erase; these operations are treated as standard read or standard programming mode. AS29LV160 defaults to erase-suspend-read mode while an erase operation has been suspended. Write the Resume command 30h to continue operation of sector erase. AS29LV160 ignores redundant writes of the Resume command. AS29LV160 permits multiple suspend/resume operations during sector erase. Sector Protect 8/30/01; V.0.9.5 When attempting to write to a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for about <1 µs. When attempting to erase a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for about <5 µs. In both cases, the device returns to read mode without altering the specified sectors. $OOLDQFH6HPLFRQGXFWRU P. 11 of 29 $6/9 &),GHVFULSWLRQDQGWDEOHV &RPPRQ)ODVK0HPRU\,QWHUIDFH4XHU\,GHQWLILFDWLRQ6WULQJ Addresses (Word Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Addresses (Byte Mode) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query unique ASCII string (QRY) Primary OEM command set Address for primary extended table Alternate OEM command set (00h = does not exist) Address for alternate OEM extended table (00h = does not exist) 6\VWHP,QWHUIDFH6WULQJ Addresses (Word Mode) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Addresses (Byte Mode) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Data 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h Description VccMin.(write/erase), D7-D4:volt, D3-D0: 100 millivolt VccMax.(write/erase), D7-D4: volt, D3-D0: 100 millivolt VppMin. Voltage (00h = no Vpp pin present) VppMax. Voltage (00h = no Vpp in present) Typical timeout per single byte/word write 2N us Typical timeout for Min. size buffer write 2N us (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) 'HYLFH*HRPHWU\'HILQLWLRQ Addresses (Word Mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 8/30/01; V.0.9.5 Addresses (Byte Mode) 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h Data 0015h 0002h 0000h 0000h 0000h 0004h 0000h 0000h 0040h 0000h Description Device size = 2N byte Flash device interface description Max. number of byte in multi-byte write = 2N (00h = not supported) Number of erase block regions within device Erase block region 1 information $OOLDQFH6HPLFRQGXFWRU P. 12 of 29 $6/9 Addresses (Word Mode) 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Addresses (Byte Mode) 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h Data 0001h 0000h 0020h 0000h 0000h 0000h 0080h 0000h 001Eh 0000h 0000h 0001h Description Erase block region 2 information Erase block region 3 information Erase block region 4 information 3ULPDU\9HQGRU6SHFLILF([WHQGHG4XHU\ Addresses (Word Mode) 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 8/30/01; V.0.9.5 Addresses (Byte Mode) 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h 92h 94h 96h 98h Data 0050h 0052h 0049h 0031h 0030h 0000h 0002h 0001h 0001h 0004h 0000h 0000h 0000h Description Query-unique ASCII string (PRI) Major version number, ASCII Minor version number, ASCII Address sensitive unlock, 0 = required, 1 = not required Erase suspend, 0 = not supported, 1 = to read only, 2 = to read and write Sector protect, 0 = not supported, X = number of sectors in per group Sector temporary unprotect, 00 = not supported, 01 = supported Sector protect/unprotect scheme Simultaneous operation, 00 = not supported, 01 = supported Burst mode type, 00 = not supported , 01 = supported Page mode type, 00 = not supported, 01 = 4 word page, 02 = 8 word page $OOLDQFH6HPLFRQGXFWRU P. 13 of 29 $6/9 6WDWXVRSHUDWLRQV DATA polling (DQ7) Only active during automated on-chip algorithms or sector erase time outs. DQ7 reflects complement of data last written when read during the automated on-chip program algorithm (0 during erase algorithm); reflects true data when read after completion of an automated on-chip program algorithm (1 after completion of erase agorithm). Toggle bit 1 (DQ6) Active during automated on-chip algorithms or sector erase time outs. DQ6 toggles when CE or OE toggles, or an Erase Resume command is invoked. DQ6 is valid after the rising edge of the fourth pulse of WE during programming; after the rising edge of the sixth WE pulse during chip erase; after the last rising edge of the sector erase WE pulse for sector erase. For protected sectors, DQ6 toggles for <1 µs during program mode writes, and <5 µs during erase (if all selected sectors are protected). Exceeding time limit (DQ5) Indicates unsuccessful completion of program/erase operation (DQ5 = 1). DATA polling remains active. If DQ5 = 1 during chip erase, all or some sectors are defective; during byte programming or sector erase, the sector is defective (in this case, reset the device and execute a program or erase command sequence to continue working with functional sectors). Attempting to program 0 to 1 will set DQ5 = 1. Sector erase timer (DQ3) Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no commands will be accepted. If DQ3 = 0, the device will accept sector erase commands. Check DQ3 before and after each Sector Erase command to verify that the command was accepted. Toggle bit 2 (DQ2) During sector erase, DQ2 toggles with OE or CE only during an attempt to read a sector being erased. During chip erase, DQ2 toggles with OE or CE for all addresses. If DQ5 = 1, DQ2 toggles only at sector addresses where failure occurred, and will not toggle at other sector addresses. Use DQ2 in conjunction with DQ6 to determine whether device is in auto erase or erase suspend mode. Ready/Busy RY/BY indicates whether an automated on-chip algorithm is in progress (RY/BY = low) or completed (RY/BY = high). The device does not accept Program/Erase commands when RY/BY = low. RY/BY= high when device is in erase suspend mode. RY/BY = high when device exceeds time limit, indicating that a program or erase operation has failed. RY/BY is an open drain output, enabling multiple RY/BY pins to be tied in parallel with a pull up resistor to VCC. :ULWHRSHUDWLRQVWDWXV Standard mode Erase suspend mode Exceeded time limits Status DQ7 DQ6 DQ5 DQ3 DQ2 RY/BY Auto programming DQ7 Toggle 0 N/A No toggle 0 0 Program/erase in auto erase 0 Toggle 0 1 Toggle† Read erasing sector 1 No toggle 0 N/A Toggle 1 Data Data Data Data Data 1 Read non-erasing sector Program in erase suspend DQ7 Toggle 0 N/A Toggle Auto programming (byte) DQ7 Toggle 1 N/A No toggle † Program/erase in auto erase 0 Toggle 1 N/A Toggle Program in erase suspend (non-erase suspended sector) DQ7 Toggle 1 N/A No toggle DQ2 toggles when an erase-suspended sector is read repeatedly. DQ6 toggles when any address is read repeatedly. DQ2 = 1 if byte address being programmed is read during erase-suspend program mode. 8/30/01; V.0.9.5 † 0 1 1 1 †DQ2 toggles when the read address applied points to a sector which is undergoing erase, suspended erase, or a failure to erase. $OOLDQFH6HPLFRQGXFWRU P. 14 of 29 $6/9 6HFWRUSURWHFWDOJRULWKP6HFWRUXQSURWHFWDOJRULWKP Temporary sector unprotect mode No START START PLSCNT = 1 PLSCNT = 1 RESET# = VID RESET# = VID Wait 1 µs Wait 1 µs Protect all sectors: The shaded portion of the sector protct algorithm must be initiated for all unprotected sectors before calling the sector unprotect First Write Cycle=60h? Yes Set up sector address Sector protect: write 60h to sector address with A6=0, A1=1, A0=0 No All sectors protected? Yes Sector unprotect: write 60h to sector address with A6=1, A1=1, A0=0 Verify sector protect; write 40h to sector address with A6=0, A1=1, A0=0 PLSCNT=25? Wait 15 ms Set up first sector address Read from sector address with A6=0, A1=1, A0=0 No No Verify sector unprotect; write 40h to sector address with A6=1, A1=1, A0=0 Increment PLSCNT Read from sector address with A6=1, A1=1, A0=0 Data=01h? No Yes Set up next sector address Yes Device failed Protect another sector? Temporary sector unprotect mode Yes Wait 150 µs Increment PLSCNT No First Write Cycle=60h? Yes PLSCNT =1000? No Remove VID from RESET# No Data=00h? Yes Yes Device failed Write reset command Last sector verified? No Yes Remove VID from RESET# Sector protect complete Write reset command Sector unprotect complete 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 15 of 29 $6/9 $XWRPDWHGRQFKLSSURJUDPPLQJDOJRULWKP $XWRPDWHGRQFKLSHUDVHDOJRULWKP START START Write erase command sequence (see below) Write program command sequence (see below) DATA polling or toggle bit successfully completed DATA polling or toggle bit successfully completed Erase complete Increment address Last address? Individual sector/multiple sector Chip erase command sequence ×16 mode (address/data): NO YES erase command sequence ×16 mode (address/data): 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/10h Sector address/30h Programming completed Program command sequence ×16 mode (address/data): 555h/AAh 2AAh/55h 555h/A0h Sector address/30h Program address/program data Sector address/30h optional sector erase commands † The system software should check the status of DQ3 prior to and following each subsequent sector erase command to ensure command completion. The device may not have accepted the command if DQ3 is high on second status check. 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 16 of 29 $6/9 3URJUDPPLQJXVLQJXQORFNE\SDVVFRPPDQG Unlock bypass command sequence x16 mode (address/data) START 555h/AAh Write unlock bypass command (3 cycles) 2AAh/55h 555h/20h Write unlock bypass program command (2 cycles) Unlock bypass program command sequence x16 mode (address/data) DATA polling or toggle bit successfully completed xxxh/A0h Increment address Last address? program address/ program data NO Unlock bypass reset command sequence x16 mode (address/data) YES xxxh/90h Write unlock bypass reset command (2 cycles) xxxh/00h Programming completed 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 17 of 29 $6/9 '$7$SROOLQJDOJRULWKP Read byte (DQ0–DQ7) Address = VA† DQ7 = data ? YES DONE NO DQ5 = 1 ? NO YES Read byte (DQ0–DQ7) Address = VA DQ7 = data‡ ? YES† DONE NO† FAIL † VA = Byte address for programming. VA = any of the sector addresses within the sector being erased during Sector Erase. VA = valid address equals any non-protected sector group address during Chip Erase. ‡ DQ7 rechecked even if DQ5 = 1 because DQ5 and DQ7 may not change simultaneously. 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 18 of 29 $6/9 7RJJOHELWDOJRULWKP Read byte (DQ0–DQ7) Address = don’t care DQ6 = toggle ? NO DONE YES NO DQ5 = 1 ? YES Read byte (DQ0–DQ7) Address = don’t care DQ6 = toggle† ? NO DONE YES FAIL †DQ6 rechecked even if DQ5 = 1 because DQ6 may stop toggling when DQ5 changes to 1. 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 19 of 29 $6/9 '&HOHFWULFDOFKDUDFWHULVWLFV Parameter 9&& ±9 Symbol Test conditions Min Max Unit - ±1 µA 35 µA Input load current ILI VIN = VSS to VCC, VCC = VCC MAX A9 Input load current ILIT VCC = VCC MAX, A9 = 10V Output leakage current ILO VOUT = VSS to VCC, VCC = VCC MAX - ±1 µA Active current, read @ 5MHz ICC1 CE = VIL, OE = VIH - 20 mA Active current, program/erase ICC2 CE = VIL, OE = VIH - 30 mA Automatic sleep mode1 ICC3 CE = VIL, OE = VIH; VIL= 0.3V, VIH = VCC - 0.3V - 5 µA Standby current ISB CE = VCC - 0.3V, RESET = VCC - .3V - 5 µA Deep power down current3 IPD RESET = 0.3V - 5 µA Input low voltage VIL -0.5 0.8 V Input high voltage VIH 0.7×VCC VCC + 0.3 V Output low voltage VOL IOL = 4.0mA, VCC = VCC MIN - 0.45 V Output high voltage VOH IOH = -2.0 mA, VCC = VCC MIN 0.85×VCC - V Low VCC lock out voltage VLKO 1.5 - V Input HV select voltage VID 9 11 V 1 Automatic sleep mode enables the deep power down mode when addresses are stable for 150 ns. Typical sleep mode current is 200 nA. 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 20 of 29 $6/9 $&SDUDPHWHUV²UHDGF\FOH -70 -80 -90 -120 JEDEC Symbol Std Symbol Parameter Min Max Min Max Min Max Min Max Unit tAVAV tRC Read cycle time 70 - 80 - 90 - 120 - ns tAVQV tACC Address to output delay - 70 - 80 - 90 - 120 ns tELQV tCE Chip enable to output - 70 - 80 - 90 - 120 ns tGLQV tOE Output enable to output - 30 - 30 - 35 - 50 ns tOES Output enable setup time 0 - 0 - 0 - 0 - ns tEHQZ tDF Chip enable to output High Z - 25 - 25 - 30 - 30 ns tGHQZ tDF Output enable to output High Z - 25 - 25 - 30 - 30 ns tAXQX tOH Output hold time from addresses, first occurrence of CE or OE 0 - 0 - 0 - 0 - ns tPHQV Output enable hold time: Read 10 - 10 - 10 - 10 - ns tOEH Output enable hold time: Toggle and data polling 10 - 10 - 10 - 10 - ns tRH RESET high to output delay - 50 - 50 - 50 - 50 ns tREADY RESET pin low to read mode - 10 - 10 - 10 - 10 µs tRP RESET pulse 500 - 500 - 500 - 500 - ns 5HDGZDYHIRUP tRC Addresses stable Addresses tACC CE tDF tOE tOES OE tOEH WE tCE Outputs High Z tOH Output valid High Z tRH RESET 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 21 of 29 $6/9 $&SDUDPHWHUV²ZULWHF\FOH :(FRQWUROOHG -70 -80 -90 -120 JEDEC Symbol Std Symbol Parameter Min Max Min Max Min Max Min Max Unit tAVAV tWC Write cycle time 70 - 80 - 90 - 120 - ns tAVWL tAS Address setup time 0 - 0 - 0 - 0 - ns tWLAX tAH Address hold time 45 - 45 - 45 - 50 - ns tDVWH tDS Data setup time 35 - 35 - 45 - 50 - ns tWHDX tDH Data hold time 0 - 0 - 0 - 0 - ns tGHWL tGHWL Read recover time before write 0 - 0 - 0 - 0 - ns tELWL tCS CE setup time 0 - 0 - 0 - 0 - ns tWHEH tCH CE hold time 0 - 0 - 0 - 0 - ns tWLWH tWP Write pulse width 35 - 35 - 35 - 50 - ns tWHWL tWPH Write pulse width high 30 - 30 - 30 - 30 - ns :ULWHZDYHIRUP :(FRQWUROOHG 3rd bus cycle Addresses tWC tAS 555h Program address DATA polling Program address tAH tCH CE tGHWL; tOES OE tWP WE tCS tWHWH1 or 2 tWPH tDH DATA 8/30/01; V.0.9.5 A0h tDS Program data $OOLDQFH6HPLFRQGXFWRU DQ7 DOUT P. 22 of 29 $6/9 $&SDUDPHWHUV²ZULWHF\FOH &(FRQWUROOHG -70 -80 -90 -120 JEDEC Symbol Std Symbol Parameter Min Max Min Max Min Max Min Max Unit tAVAV tWC Write cycle time 70 - 80 - 90 - 120 - ns tAVEL tAS Address setup time 0 - 0 - 0 - 0 - ns tELAX tAH Address hold time 45 - 45 - 45 - 50 - ns tDVEH tDS Data setup time 35 - 35 - 45 - 50 - ns tEHDX tDH Data hold time 0 - 0 - 0 - 0 - ns tGHEL tGHEL Read recover time before write 0 - 0 - 0 - 0 - ns tWLEL tWS WE setup time 0 - 0 - 0 - 0 - ns tEHWH tWH WE hold time 0 - 0 - 0 - 0 - ns tELEH tCP CE pulse width 35 - 35 - 35 - 50 - ns tEHEL tCPH CE pulse width high 30 - 30 - 30 - 30 - ns :ULWHZDYHIRUP &(FRQWUROOHG DATA polling Addresses 555h Program address tWC tAS Program address tAH WE tGHEL, tOES OE tCP tWHWH1 or 2 CE tCPH tDH DATA A0h Program data DQ7 DOUT tDS 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 23 of 29 $6/9 $&SDUDPHWHUV²WHPSRUDU\VHFWRUXQSURWHFW -70/80/90/120 JEDEC Symbol Std Symbol Parameter Min Max Unit tVIDR VID rise and fall time 500 - ns tRSP RESET setup time for temporary sector unprotect 4 - µs 7HPSRUDU\VHFWRUXQSURWHFWZDYHIRUP 12V 0 or 3V RESET tVIDR tVIDR Program/erase command sequence CE 0 or 3V WE tRSP RY/BY $&SDUDPHWHUV²5(6(7 -70/80/90/120 JEDEC Symbol Std Symbol Parameter Min Max Unit tRP RESET pulse 500 - ns tRH RESET High time before Read 50 - ns tREADY RESET Low to Read mode - 20 µs 5(6(7ZDYHIRUP RESET tRP RY/BY tREADY tRP tRH DQ status status valid data valid data (UDVHZDYHIRUP Addresses îPRGH tWC 555h tAS 2AAh 555h 555h 2AAh Sector address tAH CE tGHWL OE tWP tWC WE tWPH tCS AAh Data tDH 55h 80h AAh 55h 10h for Chip Erase 30h tDS 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 24 of 29 $6/9 $&3DUDPHWHUV²5($'<%86< -70/80/90/120 JEDEC Symbol Std Symbol - Parameter Min Max Unit tVCS VCC setup time 50 - µs - tRB Recovery time from RY/BY 0 - ns - tBUSY Program/erase valid to RY/BY delay 90 - ns 5<%<ZDYHIRUP CE Rising edge of last WE signal WE RY/BY tri-stated open-drain tBUSY Program/erase operation tRB VCC tVCS '$7$SROOLQJZDYHIRUP tCH CE tDF tOE OE tOEH WE tCE tOH DQ7 Input DQ7 Output DQ7 Output High Z tWHWH1 or 2 7RJJOHELWZDYHIRUP CE tOEH WE OE DQ6 tOE tDH 8/30/01; V.0.9.5 toggle $OOLDQFH6HPLFRQGXFWRU toggle no toggle P. 25 of 29 $6/9 :RUGE\WHFRQILJXUDWLRQ -70/80/90/120 JEDEC Symbol Std Symbol Parameter - tELFL/tELFH - Min Max Unit CE to BYTE switching Low or High - 10 ns tFLQZ BYTE switching Low to output High-Z - 30 ns tFHQZ BYTE switching High to output Active 80 - ns %<7(UHDGZDYHIRUP CE OE BYTE Word to Byte tELFL DQ15/A-1 tELFH BYTE Byte to Word DQ0-DQ14 Data output DQ0-DQ14 DQ0-DQ7 Data output DQ15 output tFLQZ DQ0-DQ14 DQ0-DQ7 Data output DQ15/A-1 Address input Address input DQ0-DQ14 Data output DQ15 output tFHQV %<7(ZULWHZDYHIRUP CE falling edge of last WE signal WE BYTE See Erase/Program operations table for tAS and tAH specifications. tSET (tAS) tHOLD (tAH) 6HFWRUSURWHFWXQSURWHFW RESET# VID VIH SA, A6, A1, A0 Don’t care Valid* Don’t care Valid* Don’t care Valid* Don’t care Verify 40h Don’t care Status Sector protect/unprotect 60h DATA CE# 1 µs 60h Sector protect: 100 µs Sector unprotect: 10 ms WE# OE# * For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0. 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 26 of 29 $6/9 $&WHVWFRQGLWLRQV 9 1 RUHTXLYDOHQW .Ω 'HYLFHXQGHUWHVW .Ω &/ 966 1 RUHTXLYDOHQW 966 966 7HVWVSHFLILFDWLRQVIRU$&SDUDPHWHUV Test Condition -70, -80 -90, -120 Output Load Unit 1 TTL gate Output Load Capacitance CL (including jig capacitance) 30 100 pF 5 ns 0.0-3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V Input Rise and Fall Times Input Pulse Levels (UDVHDQGSURJUDPPLQJSHUIRUPDQFH Limits Parameter Min Typical Max Unit - 1.0 15 sec Byte - 10 300 µs Word - 15 360 µs - 7.2 27 sec - 100,000 - cycles Sector erase and verify-1 time (excludes 00h programming prior to erase) Programming time Chip programming time 1 Erase/program cycles 1 Erase/program cycle test is not verified on each shipped unit. /DWFKXSWROHUDQFH Parameter Min Max Unit Input voltage with respect to VSS on A9, OE, and RESET pin -1.0 +12.0 V Input voltage with respect to VSS on all DQ, address, and control pins -0.5 VCC+0.5 V Current -100 +100 mA Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU P. 27 of 29 $6/9 5HFRPPHQGHGRSHUDWLQJFRQGLWLRQV Parameter Symbol Min Max Unit Vcc +2.7 +3.6 V VSS 0 0 V VIH 1.9 VCC + 0.3 V VIL –0.5 0.8 V Supply voltage Input voltage $EVROXWHPD[LPXPUDWLQJV Parameter Symbol Min Max Unit Input voltage (Input or DQ pin) VIN –0.5 VCC+ 0.5 V Input voltage (A9 pin, OE, RESET) VIN –0.5 +12.5 V Power supply voltage VCC -0.5 +4.0 V Operating temperature TOPR –55 +125 °C Storage temperature (plastic) TSTG –65 +150 °C 150 mA Short circuit output current IOUT Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 7623SLQFDSDFLWDQFH Symbol CIN COUT CIN2 Parameter Input capacitance Output capacitance Control pin capacitance Test setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 8 Max 7.5 12 10 Unit pF pF pF Test setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 8 Max 7.5 12 10 Unit pF pF pF 62SLQFDSDFLWDQFHDYDLODELOLW\7%' Symbol CIN COUT CIN2 Parameter Input capacitance Output capacitance Control pin capacitance 'DWDUHWHQWLRQ Parameter Minimum pattern data retention time 8/30/01; V.0.9.5 $OOLDQFH6HPLFRQGXFWRU Temp.(°C) Min Unit 150° 10 years 125° 20 years P. 28 of 29 $6/9 3DFNDJHGLPHQVLRQV 7KLQVPDOORXWOLQHSDFNDJH7623, b e 48-pin 12×20 c A2 L pin 1 A A1 pin 48 pin 24 D Min Max – 1.27 0.05 0.15 0.95 1.05 0.17 0.27 0.15 nominal 18.20 18.60 0.50 nominal 11.90 12.10 19.80 20.20 0.50 0.70 0° 5° A A1 A2 b c D e E Hd L α Hd pin 25 48-pin α E 3DFNDJHGLPHQVLRQV 6PDOO2XWOLQH3ODVWLF62DYDLODELOLW\7%' c 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 JEDEC MO - 175 AA 44-pin SO e He SO 1 2 3 4 5 6 7 8 0–10° 9 10 11 12 13 14 15 16 17 18 19 20 21 22 d A2 A A1 l Min (mm) Max (mm) A – 3.1 A1 0.05 – A2 2.5 2.9 b 0.25 0.45 c 0.09 0.25 d 28.0 28.4 e 12.4 12.8 E He b 8/30/01; V.0.9.5 E l $OOLDQFH6HPLFRQGXFWRU 1.27 (typical) 16.05 (typical) 0.73 1.3 P. 29 of 29 © Copyright Alliance Semiconductor Corporation. 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