AS4C256K16E0 ® 5V 256K×16 CMOS DRAM (EDO) Features • Organization: 262,144 words × 16 bits • High speed - 30/35/50 ns RAS access time - 16/18/25 ns column address access time - 7/10/10/10 ns CAS access time • Low power consumption - Active: 500 mW max (AS4C256K16E0-25) - Standby: 3.6 mW max, CMOS I/O (AS4C256K16E0-25) • EDO page mode • Refresh - 512 refresh cycles, 8 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh - Self-refresh option is available for new generation device only. Contact Alliance for more information. • Read-modify-write • TTL-compatible, three-state I/O • JEDEC standard packages - 400 mil, 40-pin SOJ - 400 mil, 40/44-pin TSOP II • 5V power supply • Latch-up current > 200 mA Pin arrangement Pin designation 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AS4C256K16E0 Vcc I/O0 I/O1 I/O2 I/O3 Vcc I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 Vcc 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 GND VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 NC NC WE RAS NC A0 A1 A2 A3 VCC 13 14 15 16 17 18 19 20 21 22 AS4C256K16E0 TSOP II SOJ 44 43 42 41 40 39 38 37 36 35 GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 32 31 30 29 28 27 26 25 24 23 NC LCAS UCAS OE A8 A7 A6 A5 A4 GND Pin(s) Description A0 to A8 Address inputs RAS Row address strobe I/O0 to I/O15 Input/output OE Output enable UCAS Column address strobe, upper byte LCAS Column address strobe, lower byte WE Read/write control VCC Power (5V ± 0.5V) GND Ground Selection guide Symbol AS4C256K16E0-30 AS4C256K16E0-35 AS4C256K16E0-50 Unit Maximum RAS access time tRAC 30 35 50 ns Maximum column address access time tCAA 16 18 25 ns Maximum CAS access time tCAC 10 10 10 ns Maximum output enable (OE) access time tOEA 10 10 10 ns Minimum read or write cycle time tRC 65 70 85 ns Minimum EDO page mode cycle time tPC 12 14 25 ns Maximum operating current ICC1 180 160 140 mA Maximum CMOS standby current ICC2 2.0 2.0 2.0 mA Shaded areas contain advance information. 4/11/01; v.1.1 Alliance Semiconductor 1 of 24 Copyright © Alliance Semiconductor. All rights reserved. AS4C256K16E0 ® Functional description The AS4C256K16E0 is a high performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16 bits. The AS4C256K16E0 is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The AS4C256K16E0 features a high speed page mode operation in which high speed read, write and read-write are performed on any of the 512 × 16 bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Very fast CAS to output access time eases system design. Refresh on the 512 address combinations of A0 to A8 during an 8 ms period is accomplished by performing any of the following: • RAS-only refresh cycles • Hidden refresh cycles • CAS-before-RAS refresh cycles • Normal read or write cycles • Self-refresh cycles* The AS4C256K16E0 is available in standard 40-pin plastic SOJ and 40/44-pin TSOP II packages compatible with widely available automated testing and insertion equipment. System level features include single power supply of 5V ± 0.5V tolerance and direct interface with TTL logic families. REFRESH CONTROLLER Logic block diagram RAS UCAS RAS CLOCK GENERATOR CAS CLOCK GENERATOR A0 A1 A2 A3 A4 A5 A6 A7 A8 OE 512×512×16 ARRAY (4,194,304) SUBSTRATE BIAS GENERATOR LCAS WE WE CLOCK GENERATOR Recommended operating conditions Parameter Supply voltage Input voltage I/O0 to I/O15 SENSE AMP ROW DECODER GND DATA I/O BUFFER COLUMN DECODER ADDRESS BUFFERS VCC (Ta = 0°C to +70°C) Symbol Min Typ Max Unit VCC 4.5 5.0 5.5 V GND 0.0 0.0 0.0 V VIH 2.4 – VCC + 1 V VIL –1.0 – 0.8 V *Self-refresh option is available for new generation device only. Contact Alliance for more information. 4/11/01; v.1.1 Alliance Semiconductor 2 of 24 AS4C256K16E0 ® Absolute maximum ratings Parameter Symbol Min Max Unit Input voltage Vin -1.0 +7.0 V Output voltage Vout -1.0 +7.0 V Power supply voltage VCC -1.0 +7.0 V Operating temperature TOPR 0 +70 °C Storage temperature (plastic) TSTG -55 +150 °C Soldering temperature × time TSOLDER – 260 × 10 o Power dissipation PD – 1 W Short circuit output current Iout – 50 mA 200 – mA Latch-up current C × sec NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC electrical characteristics -30 -35 -50 Max Unit Note Parameter Symbol Test conditions Min Max Min Max Min Input leakage current IIL 0V ≤ Vin ≤ +5.5V pins not under test = 0V -10 10 -10 10 -10 10 µA Output leakage current IOL DOUT disabled, 0V ≤ Vout ≤ +5.5V -10 10 -10 10 -10 10 µA Operating power supply current ICC1 RAS, UCAS, LCAS, address cycling; tRC=min – 180 – 160 – 140 mA TTL standby power ICC2 supply current RAS = UCAS = LCAS = VIH – 2.0 – 2.0 – 2.0 mA Average power supply current, RAS refresh mode ICC3 RAS cycling, UCAS = LCAS = VIH, tRC = min – 200 – 190 – 140 mA 1 EDO page mode average power supply current ICC4 RAS=UCAS=LCAS=VIL, address cycling: tSC = min – 190 – 180 – 70 mA 1,2 CMOS standby power supply current ICC5 RAS=UCAS=LCAS= VCC - 0.2V – 1.0 – 1.0 – 1.0 mA CAS-before-RAS refresh power supply current ICC6 RAS, UCAS, LCAS, cycling; tRC = min – 200 – 190 – 140 mA VOH IOUT = -5.0 mA 2.4 – 2.4 – 2.4 – V VOL IOUT = 4.2 mA – 0.4 – 0.4 – 0.4 V ICC7 RAS = UCAS = LCAS=VIL, WE = OE = A0-A8 = VCC-0.2V, DQ0-DQ15 = VCC-0.2V, 0.2V are open – 2.0 – 2.0 – 2.0 mA Output Voltage Self refresh current 1,2 1 Shaded areas contain advance information. 4/11/01; v.1.1 Alliance Semiconductor 3 of 24 AS4C256K16E0 ® AC parameters common to all waveforms -30 -35 -50 Std Symbol Parameter Min Max Min Max Min Max tRC Random read or write cycle time 65 – 70 – 85 – ns tRP RAS precharge time 25 – 25 – 25 – ns tRAS RAS pulse width 30 75K 35 75K 50 75K ns tCAS CAS pulse width 5 – 6 – 10 – ns tRCD RAS to CAS delay time 15 20 16 24 15 35 ns 6 tRAD RAS to column address delay time 10 14 11 17 15 25 ns 7 tRSH(R) CAS to RAS hold time (read cycle) 10 – 10 – 10 – ns tCSH RAS to CAS hold time 30 – 35 – 50 – ns tCRP CAS to RAS precharge time 5 – 5 – 5 – ns tASR Row address setup time 0 – 0 – 0 – ns tRAH Row address hold time 5 – 6 – 9 – ns tT Transition time (rise and fall) 1.5 50 1.5 50 3 50 ns 4,5 tREF Refresh period – 8 – 8 – 8 ms 3 tCLZ CAS to output in low Z 0 – 0 – 3 – ns 8 Unit Notes Shaded areas contain advance information. Read cycle -30 Std Symbol Parameter tRAC -35 -50 Min Max Min Max Min Max Access time from RAS – 30 – 35 – 50 ns 6 tCAC Access time from CAS – 10 – 10 – 10 ns 6,13 tAA Access time from address – 16 – 18 – 25 ns 7,13 tAR(R) Column add hold from RAS 26 – 28 – 30 – ns tRCS Read command setup time 0 – 0 – 0 – ns tRCH Read command hold time to CAS 0 – 0 – 0 – ns 9 tRRH Read command hold time to RAS 0 – 0 – 0 – ns 9 tRAL Column address to RAS Lead time 16 – 18 – 25 – ns tCPN CAS precharge time 3 – 4 – 5 – ns tOFF Output buffer turn-off time 0 8 0 8 0 8 ns Unit Notes 8,10 Shaded areas contain advance information. 4/11/01; v.1.1 Alliance Semiconductor 4 of 24 AS4C256K16E0 ® Write cycle -30 Std Symbol Parameter tASC -35 -50 Unit Notes Min Max Min Max Min Max Column address setup time 0 – 0 – 0 – ns tCAH Column address hold time 5 – 5 – 9 – ns tAWR Column address hold time to RAS 26 – 28 – 30 – ns tWCS Write command setup time 0 – 0 – 0 – ns 11 tWCH Write command hold time 5 – 5 – 9 – ns 11 tWCR Write command hold time to RAS 26 – 28 – 30 – ns tWP Write command pulse width 5 – 5 – 9 – ns tRWL Write command to RAS lead time 10 – 11 – 12 – ns tCWL Write command to CAS lead time 10 – 11 – 12 – ns tDS Data-in setup time 0 – 0 – 0 – ns 12 tDH Data-in hold time 5 – 5 – 9 – ns 12 26 – 28 – 30 – ns tDHR Data-in hold time to RAS Shaded areas contain advance information. Read-modify-write cycle -30 -35 -50 Std Symbol Parameter Min Max Min Max Min Max tRWC Read-write cycle time 100 – 105 – 120 – ns tRWD RAS to WE delay time 50 – 54 – 60 – ns 11 tCWD CAS to WE delay time 26 – 28 – 30 – ns 11 tAWD Column address to WE delay time 32 – 35 – 40 – ns 11 tRSH(W) CAS to RAS hold time (write) 10 – 10 – 12 – ns 15 – 15 – 15 – ns CAS pulse width (write) tCAS(W) Shaded areas contain advance information. 4/11/01; v.1.1 Alliance Semiconductor Unit Notes 5 of 24 AS4C256K16E0 ® EDO page mode cycle -30 Std Symbol Parameter tPC -35 -50 Unit Notes – ns 14 – 23 ns 13 – 5 – ns 58 – 60 – ns – 46 – 50 – ns 75K 35 75K 50 75K ns Unit Notes Min Max Min Max Min Max Read or write cycle time 12 – 14 – 25 tCAP Access time from CAS precharge – 19 – 21 tCP CAS precharge time 3 – 4 tPCM EDO page mode RMW cycle 56 – tCRW Page mode CAS pulse width (RMW) 44 tRASP RAS pulse width 30 Shaded areas contain advance information. Refresh cycle -30 Std Symbol Parameter tCSR -35 -50 Min Max Min Max Min Max CAS setup time (CAS-before-RAS) 10 – 10 – 10 – ns 3 tCHR CAS hold time (CAS-before-RAS) 7 – 8 – 10 – ns 3 tRPC RAS precharge to CAS hold time 0 – 0 – 0 – ns tCPT CAS precharge time (CAS-before-RAS counter test) 8 – 8 – 8 – ns Shaded areas contain advance information. Output enable -30 Std Symbol Parameter tROH -35 -50 Min Max Min Max Min Max RAS hold time referenced to OE 5 – 5 – 5 – ns tOEA OE access time – 10 – 10 – 10 ns tOED OE to data delay 5 – 5 – 8 – ns tOEZ Output buffer turnoff delay from OE – 8 – 8 – 8 ns tOEH OE command hold time 8 – 8 – 8 – ns Unit Notes 8 Shaded areas contain advance information. Self refresh cycle -30 Std Symbol Parameter tRASS RAS pulse width (CBR self refresh) tRPS tCHS -35 -50 Unit Min Max Min Max Min Max 100K – 100K – 100K – ns RAS precharge time (CBR self refresh) 85 – 85 – 85 – ns CAS hold time (CBR self refresh) 30 – 30 – 30 – ns Notes Shaded areas contain advance information. 4/11/01; v.1.1 Alliance Semiconductor 6 of 24 AS4C256K16E0 ® Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ICC1, ICC3, ICC4, and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). AC Characteristics assume tT = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 60 pF, VIL (min) ≥ GND and VIH (max) ≤ VCC. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent). Either tRCH or tRRH must be satisfied for a read cycle. tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS ≥ tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles. Access time is determined by the longest of tCAA or tCAC or tCAP. tASC ≥ tCP to achieve tPC (min) and tCAP (max) values. These parameters are sampled and not 100% tested. Key to switching waveform Undefined/don’t care Rising input Falling input Read cycle waveform tRC tRAS tRCD tRSH tRP RAS tCSH tCRP tCAH tASC tRCS tCAS UCAS, tAR LCAS tRAD tASR Address tRAL tRAH Row Address Col Address tRRH tRCH WE tROH OE tOEZ tRAC tAA tOFF tOEA tCAC tCLZ I/O 4/11/01; v.1.1 Data Out Alliance Semiconductor 7 of 24 AS4C256K16E0 ® Upper byte read cycle waveform tRC tRAS tRP RAS tRCD tRSH tCSH tCRP tCRP tCAS UCAS tCRP LCAS tRAH tRAL tRAD tASC tASR Address tCAH Row Column tRCH tRRH tRCS WE tROH OE tOEA tRAC tOEZ tAA tCAC tCLZ tOFF Upper I/O Data Out Lower I/O Lower byte read cycle waveform tRC tRAS tRP RAS tRCD tRSH tCSH tCRP tCRP tCAS LCAS tCRP UCAS tASC tRAH tRAD tRAL tASR Address tCAH Row Column tRCS tRRH tRCH WE tROH OE Upper I/O tOEA tRAC tOEZ tAA tCAC tOFF tCLZ Data Out Lower I/O 4/11/01; v.1.1 Alliance Semiconductor 8 of 24 AS4C256K16E0 ® Early write cycle waveform tRC tRAS tRP RAS tCSH tRSH tCRP tRCD tCAS UCAS, tAWR LCAS tRAD tRAL tASC tASR Address tRAH tCAH Row Address Col Address tWCR tCWL tRWL tWP tWCS tWCH WE OE tDHR tDH tDS I/O Data In Upper byte early write cycle waveform tRC tRAS tRP RAS tAWR tASR tRAD tRAL tRAH Address Row Address Column Address tCAH tASC tRCD tRSH tCSH tCRP tCAS tCRP UCAS tCRP tRPC LCAS tCWL tWCH tWCS tRWL tWCR tWP WE OE tDHR tDS Upper I/O tDH Data In Lower I/O 4/11/01; v.1.1 Alliance Semiconductor 9 of 24 AS4C256K16E0 ® Lower byte early write cycle waveform tRC tRAS tRP RAS tAWR tRAD tASR Address tRAL tRAH Row Address Column Address tCRP tRPC UCAS tASC tCAH tRCD tCAS tCSH tRSH tCRP tCRP LCAS tWCR tRWL tCWL tWCH tWCS tWP WE OE Upper I/O tDHR tDS tDH Lower I/O Data In Write cycle waveform (OE controlled) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tRCD UCAS, LCAS tRAL tAWR tRAD tASR Address tASC tRAH tCAH Row Address Col Address tWCR tRWL tCWL tWP WE tOEH OE tDHR tOED I/O 4/11/01; v.1.1 tDS tDH Data In Alliance Semiconductor 10 of 24 AS4C256K16E0 ® Upper byte write cycle waveform (OE controlled) tRC tRAS tRP RAS tRAD tRAL tAWR tASR Address tRAH Row Address Column Address tCSH tRSH tRCD tCAH tCRP tASC tCAS tCRP UCAS tCRP tRPC LCAS tCWL tRWL tWP WE tOEH OE tDS tDH Upper I/O Data In tOED Lower I/O Lower byte write cycle waveform (OE controlled) tRC tRAS tRP RAS tRAD tAWR tASR tRAL tRAH Address Row Address Column Address tCAH tCAS tRCD tCSH tCRP tRSH tACS tCRP LCAS tCRP tRPC UCAS tCWL tRWL tWP WE tOEH OE Upper I/O tDH tDS Lower I/O 4/11/01; v.1.1 Data In Alliance Semiconductor 11 of 24 AS4C256K16E0 ® Read-modify-write cycle waveform tRWC tRAS tRP RAS tCAS tCRP tRCD tRSH tCSH UCAS, LCAS tAR tRAL tRAD tASR Address tASC tRAH tCAH Row Address Col Address tRWL tRWD tCWL tAWD tRCS WE tCWD tOEA tWP tOED tOEZ OE tRAC tAA tCAC tCLZ I/O 4/11/01; v.1.1 Data Out Alliance Semiconductor tDS tDH Data In 12 of 24 AS4C256K16E0 ® Upper byte read-modify-write cycle waveform tRWC tRAS tRP RAS tCSH tRCD tCAS tRSH tCRP tCRP UCAS tCRP tRPC LCAS tRAD tACS tASR tRAL tCAH tRAH Address Row Column Address tRWD tCWL tAWD tRWL tCWD tRCS WE tWP tOEA OE tDS tOED Upper Input tCLZ tCAC Data In tAA tOEZ tRAC Upper Output Data Out tOED Lower Input Lower Output Data Out 4/11/01; v.1.1 Alliance Semiconductor 13 of 24 AS4C256K16E0 ® Lower byte read-modify-write cycle waveform tRWC tRAS tRP RAS tRPC tCRP UCAS tCSH tCAS tRCD tCRP tRSH tCRP LCAS tRAD tASR tRAL tACS tCAH tRAH Address Row Column Address tCWL tRWD tRWL tAWD tRCS tCWD tWP WE tOEA OE Upper Input Upper Output Data Out tDS tOED Lower Input tRAC tAA tCAC tCLZ Data In tOEZ Lower Output Data Out 4/11/01; v.1.1 Alliance Semiconductor 14 of 24 AS4C256K16E0 ® EDO page mode read cycle waveform tRASP tRP RAS tCSH tCRP tRSH tRCD UCAS, LCAS tCAS tCP tPC tAR tCAH tRAD tRAL tRAH tASR Address tASC Col Address Row Col Address tRCS Col Address tRCS tRCH tRRH tRCH WE tOEA tOEA OE tRAC tCAP tCLZ tCAC tAA tCAC I/O Data Out Data Out EDO page mode byte read cycle waveform tRP tRASP RAS tCSH tCRP tRSH tCAS tCAS tRCD tCRP UCAS tCP tPC tPC tCAS tCRP Address tCAH tRAH tRAD tASR Row tRAL tASC tCAH tASC Column 1 tRPC tCP LCAS tCAH tASC Column 2 Column n tRCS tRCS tRCS tRCH tRCH WE tOEA tOEA tOEA OE tCAC tCLZ tAA tCAP Lower I/O tOFF tOEZ Data Out 2 tAA tRAC tCAC tCLZ tOFF tOEZ tAA tCAP tCAC tCLZ tOFF tOEZ Upper I/O Data Out 1 4/11/01; v.1.1 Alliance Semiconductor Data Out n 15 of 24 AS4C256K16E0 ® EDO page mode early write cycle waveform tRASP tRAH tRWL RAS tCRP tRCD tPC tCSH tCAS UCAS, LCAS tCAH tASC tCP tWCS tRSH tRAL tAR tASR Address tRAD Row address Col address Col Address Col Address tCWL tWP tWCH tOEH WE OE tHDR tDH tDS I/O Data In Data In Data In EDO page mode byte early write cycle waveform tRASP tRP RAS tCSH tCRP tRCD tRSH tCAS tCAS tCRP UCAS tCP tCP tPC tPC tCAS tCRP tRPC LCAS tRAD tRAH tASR Address tCAH tASC tASC tASC Row tRAL tCAH tCAH Column 1 Column 2 Column n tRWL tWCH tWCH tWCH tWCS tWCS tWCS tWP tCWL tWP tCWL tWP tCWL WE OE tDS Lower I/O tDH Data In 2 tDS tDH tDS tDH Upper I/O Data In 1 4/11/01; v.1.1 Alliance Semiconductor Data In n 16 of 24 AS4C256K16E0 ® EDO page mode read-modify-write cycle waveform tRASP tRP RAS tPCM tCSH tRCD UCAS, LCAS tCAS tCP tCRP tRAD tRAH tASR tRAL tCAH Address Row Ad tCAH Col Ad Col Ad tRWD tRCS tCAH Col Address tCWL tRWL tCWD tCWD tCWD tAWD tAWD tCWL tWP WE tOEA tOEZ tOED tOEA OE tAA tDH tRAC tDS tCLZ tCAC I/O tCAP tDS tCLZ tCLZ tCAC tCAC Data In Data Out Data In Data Out Data In Data Out CAS-before-RAS refresh cycle waveform (WE = VIH ) tRC tRP tRAS RAS tRPC tCHR tCPN tCSR UCAS, LCAS tOFF I/O RAS only refresh cycle waveform (WE = OE = VIH or VIL) tRC tRAS tRP RAS tCRP UCAS, LCAS Address 4/11/01; v.1.1 tARS tRPC tRAH Row Address Alliance Semiconductor 17 of 24 AS4C256K16E0 ® EDO page mode byte read-modify-write cycle tRASP tRP RAS tCSH tRCD tCRP tRSH tCAS tCAS tCRP UCAS tPCM tCP tCP tCAS LCAS tRAD tRAH tASR Address tAWD tASC tASC R C1 tASC Cn C2 tRWL tAWD tCWD tRCS tRAL tCAH tAWD tCAH tCAH tCWD tCWD tCWL tRWD tCWL tWP tCWL tWP tWP WE tOEA tOEA tOEA OE tDH tOED tOED tDH tDS tDS Upper Input Data In 1 tRAC tAA tCAC Data In n tCAP tAA tCAC tOEZ tOEZ tCLZ tCLZ Upper Output tOED Data Out 1 tDH Data Out n Lower Input Data In 2 tDS tAA tOEZ tCAC tCLZ Lower Output Data Out 2 4/11/01; v.1.1 Alliance Semiconductor 18 of 24 AS4C256K16E0 ® Hidden refresh cycle (read) waveform tRC tRC tRAS tPR tRAS tPR RAS tCRP tCHR tRCD tRSH tCRP CAS tAR tRAD tRAH tASC tASR Row Address Col Address tRCS tRRH WE tOEA OE tRAC tAA tCAC tOFF tCLZ tOEZ Data Out I/O Hidden refresh cycle (write) waveform tRC tRAS tRP RAS tCRP tRCD tRSH UCAS, LCAS tAR tRAD tRAH tRAL tASR Address tASC Row Address tCAH Col Address tRWL tWCR tWP tWCS tWCH WE tDS tDH tDHR I/O Data In OE 4/11/01; v.1.1 Alliance Semiconductor 19 of 24 AS4C256K16E0 ® CAS-before-RAS refresh counter test cycle waveform tRAS tRSH tRP RAS tCPT tCSR tCAS tCHR UCAS, LCAS tRAL tCAH Address Col Address tAA tCAC tCLZ Read Cycle I/O tOFF Data Out tRRH tRCH tRCS WE tOEA tROH OE tRWL tCWL tWP tWCH Write Cycle tWCS WE tDH tDS I/O Data In OE tRCS tWP tCWD tAWD tCWL Read-Write Cycle WE tOEA t AA tCLZ tDH tCAC I/O 4/11/01; v.1.1 tOED OE Data Out Alliance Semiconductor tOEZ tDS Data In 20 of 24 AS4C256K16E0 ® CAS-before-RAS self refresh cycle tRP tRASS tRPS RAS tRPC tRPC tCP tCHS tCSR UCAS, LCAS tCEZ DQ Typical DC and AC characteristics 1.2 1.1 1.0 0.9 0.8 4.0 70 4.5 5.0 5.5 Supply voltage (V) Typical supply current ICC vs. supply voltage VCC Supply current (mA) Supply current (mA) 1.2 1.1 1.0 0.9 40 30 20 10 6.0 60 50 30 50 Typical supply current ICC vs. ambient temperature Ta 100 150 200 Load capacitance (pF) 250 Typical power-on current IPO vs. cycle rate 1/tRC 35 30 50 40 30 20 0.0 –55 70 –10 35 80 125 Ambient temperature (°C) 10 4.5 5.0 5.5 Supply voltage (V) 80 40 60 50 4/11/01; v.1.1 90 1.3 70 60 0.0 4.0 1.4 0.8 –55 6.0 Typical access time tRAC vs. load capacitance CL 100 Power-on current (mA) 1.3 Ta = 25°C Normalized access time tRAC vs. ambient temperature Ta Typical access time 1.4 1.5 Normalized access time Normalized access time 1.5 Normalized access time tRAC vs. supply voltage VCC 25 20 15 10 5 0.0 –10 35 80 125 Ambient temperature (°C) Alliance Semiconductor 2 4 6 8 Cycle rate (MHz) 10 21 of 24 AS4C256K16E0 ® 35 Typical refresh current ICC3 vs. Ambient temperature Ta Refresh current (mA) 25 20 15 10 0 4.0 4.5 5.0 5.5 Supply voltage (V) 3.0 25 20 15 10 Typical TTL stand-by current ICC2 vs. ambient temperature Ta 3.5 70 3.0 60 2.5 2.0 1.5 1.0 0.5 0.0 0 EDO page mode current (mA) 25 20 15 10 5 0.0 0 20 40 60 80 Ambient temperature (°C) 4/11/01; v.1.1 2.0 1.5 1.0 0 4.0 70 50 40 30 20 10 4.5 5.0 5.5 Supply voltage (V) 6.0 Typical output source current IOH vs. output voltage VOH 60 50 40 30 20 10 0.0 0.5 1.0 1.5 Output voltage (V) 2.0 0.0 1.0 2.0 3.0 Output voltage (V) 4.0 Typical EDO page mode current ICC4 vs. supply voltage VCC 35 Typical EDO page mode current ICC4 vs. ambient temperature Ta 35 30 2.5 20 40 60 80 Ambient temperature (°C) Typical output sink current IOL vs. output voltage VOL 0.0 0.0 20 40 60 80 Ambient temperature (°C) Typical TTL stand-by current ICC2 vs. supply voltage VCC 0.5 0 0.0 6.0 Output sink current (mA) Stand-by current (mA) 30 5 5 EDO page mode current (mA) 3.5 Output source current (mA) Refresh current (mA) 30 35 Stand-by current (mA) Typical refresh current ICC3 vs. supply voltage VCC 30 25 20 15 10 5 0.0 4.0 4.5 5.0 5.5 Supply voltage (V) Alliance Semiconductor 6.0 22 of 24 AS4C256K16E0 ® Package dimensions 44-pin TSOP II 1 2 3 4 5 6 7 8 E He 13 14 15 16 17 18 19 20 21 22 9 10 d l A2 A 0–5° A1 A A1 A2 b c d E He e l 44-pin TSOP II Min Max (mm) (mm) 1.2 0.05 0.95 1.05 0.30 0.45 0.127 (typical) 18.28 18.54 10.03 10.29 11.56 11.96 0.80 (typical) 0.40 0.60 A A1 A2 B b c D E E1 E2 e 40-pin SOJ 400 mil Min Max 0.128 0.148 0.025 1.105 1.115 0.026 0.032 0.015 0.020 0.007 0.013 1.020 1.035 0.370 (typical) 0.390 0.410 0.435 0.445 0.050 (typical) c 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 e b e D 40-pin SOJ E1 E2 Pin 1 B c A A2 A1 E Seating Plane b Capacitance ƒ = 1 MHz, Ta = room temperature, VCC = 5V ± 0.5V Parameter Input capacitance I/O capacitance Symbol Signals Test conditions Max Unit CIN1 A0 to A8 Vin = 0V 5 pF CIN2 RAS, UCAS, LCAS, WE, OE Vin = 0V 7 pF CI/O I/O0 to I/O15 Vin = Vout = 0V 7 pF Ordering codes Package \ Access time 30 ns 35 ns 50 ns Plastic SOJ, 400 mil, 40-pin AS4C256K16E0-30JC AS4C256K16E0-35JC AS4C256K16E0-50JC TSOP II, 400 mil, 40/44-pin AS4C256K16E0-50TC Shaded areas contain advance information. Part numbering system AS4C 256K16E0 –XX X C DRAM prefix Device number RAS access time Package: J = SOJ T = TSOP II Commercial temperature range, 0°C to 70 °C 4/11/01; v.1.1 Alliance Semiconductor 23 of 24 AS4C256K16E0 ® 4/11/01; v.1.1 Alliance Semiconductor 24 of 24 © Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. 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