November 2003 AS80M2516A rev 1.0 Pin Configuration Features • Two on chip PLLs. • Generates an EMI optimized clocking signal at output. • Non Spread spectrum mode available • Input Frequency Range 2MHz– 200Mhz in Non Spread mode • X1IN 1 16 REF1OUT X1OUT 2 15 GND VDDA/DIGITAL 3 14 SCL VDD_FOUT2 4 13 SDA VDD_FOUT1 5 12 FOUT1_CLK2 FOUT1_CLK1 6 11 FOUT2_CLK2 FOUT2_CLK1 7 10 REF2OUT PLL1_REF_D2 8 9 Input Frequency Range 6Mhz – 80Mhz in Spread mode. • Output Frequency Range 4Mhz – 140Mhz. • Four frequency outputs; two per PLL. • Programmable spread range and type of modulation ( center or down) and type of profile. • Power down feature is incorporated. • Both the PLL have reference frequency POWER DOWN output. • Supply voltage range 3.3 V (± 0.3) • Software is available for configuring all the parameters of the Chip, through I2C . functional parameters of the AS80M2516A can be Product Description configured from external I2C master unit through The AS80M2516A is dual phase lock loop clock I2C bus. chip. The AS80M2516A is a versatile spread spectrum frequency modulator design specifically The AS80M2516A modulates the output of PLL in for a wide range of clock frequencies. order to spread the bandwidth of a The AS80M2516A reduces electromagnetic synthesized clock , there by decreasing the peak interference (EMI) at clock source. The amplitudes of its harmonics. This results in AS80M2516A allows significant system cost significantly lower system EMI compared to the savings by reducing the number of circuit board typical narrow band signal produced by oscillator layers and shielding that are required to pass EMI and most clock generators. Lowering EMI by regulations. increasing a signal's bandwidth is called spread The AS80M2516A is I2C configurable. All the spectrum clock generation. Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. November 2003 AS80M2516A rev 1.0 Block Diagram X1IN X1OUT Crystal Oscillator 1 / R PLL1 FOUT1_CLK1 PLL1 Out Div FOUT1EN CLKGENEN1 DIV MODULATION 1/N Feedback Counter I 2 C FOUT1_CLK2 Out Div FOUT2EN CLKGENEN1 SDA SCL I N T E R F A C E REF1 OUT DIV 1 2 REFOUT1EN CLKGENEN1 PLL1_REF_D2 FOUT2_CLK1 1 / R PLL2 PLL2 1/N Feedback Counter Out Div DIV FOUT1EN CLKGENEN2 FOUT2_CLK2 Out Div FOUT2EN CLKGENEN2 REFOUT2 REFOUT2EN CLKGENEN2 Low Power EMI Reduction IC Notice: The information in this document is subject to change without notice. ` 2 of 15 November 2003 AS80M2516A rev 1.0 Pin Description Pin No Pin Name Pin Type 1 X1IN IN Connection to Crystal-1 2 X1OUT OUT Connection to Crystal-1 3 VDDA/DIGITAL PWR Power supply to Analog and Digital blocks except the Output Buffers 4 VDD_FOUT2 PWR 5 VDD_FOUT1 PWR 6 FOUT1_CLK1 OUT Tristatable Clock Output-1 of Clock Generator-1 7 FOUT2_CLK1 OUT Tristatable Clock Output-2 of Clock Generator-1 8 PLL1_REF_D2 IN Set High to divide the REF_IN(X1IN) by 2 9 POWERDOWN IN Powers the entire chip down 10 REF2OUT OUT Buffered and Divide by 2 Output of X1IN 11 FOUT2_CLK2 OUT Tristatable Clock Output-2 of Clock Generator-2 12 FOUT1_CLK2 OUT Tristatable Clock Output-1 of Clock Generator-2 13 SDA IN/OUT 14 SCL IN 15 GND PWR Ground to entire chip 16 REF1OUT OUT Buffered Output of X1IN Description Variable Output Voltage Control for FOUT2 . The minimum voltage is 1.8V. Variable Output Voltage Control for FOUT1 . The minimum voltage is 1.8V. Serial Data I/O for I2C Serial Clock Input for I2C Note:- All the Pin types IN have CMOS pull-up resistors. Low Power EMI Reduction IC Notice: The information in this document is subject to change without notice. 3 of 15 November 2003 AS80M2516A rev 1.0 Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality and reliability. PARAMETER SYMBOL MIN MAX UNITS VDD VSS-0.5 7 V Input Voltage, dc VI VSS-0.5 VDD+0.5 V Output Voltage, dc VO VSS-0.5 VDD+0.5 V IIK -50 50 mA IOK -50 50 mA TS -65 150 °C TA -55 125 °C 150 °C 260 °C 2 kV Supply Voltage, dc (Vss = ground) Input Clamp Current, dc (VI < 0 or VI >VDD) Output Clamp Current, dc (VI < 0 or VI >VDD) Storage Temperature Range (non condensing) Ambient Temperature Range, Under Bias Junction Temperature TJ Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL – STD 883E, Method 3015.7) CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Low Power EMI Reduction IC Notice: The information in this document is subject to change without notice. 4 of 15 November 2003 AS80M2516A rev 1.0 Operating Conditions PARAMETER Supply Voltage Ambient Operating Temperature Range Crystal Resonator Frequency SYMBOL VDD CONDITIONS/DESCRIPTION 3.3V ± 10% MAX UNITS 3 3.3 3.6 V 0 70 °C FXIN 2 200 MHz 10 100 kb/s 15 pF Standard mode Rate Capacitance TYP TA Serial Data Transfer Output Driver Load MIN CL Low Power EMI Reduction IC Notice: The information in this document is subject to change without notice. 5 of 15 November 2003 AS80M2516A rev 1.0 DC Electrical Specifications Unless otherwise stated, VDD=3.3V ± 10%, no load on any output, and ambient temperature range TA=0°C to 70°C. Parameters with an astertsk (*) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents inclicate current flows out of the device. PARAMETER SYMBOL CONDITIONS/ DESCRIPTION MIN TYP MAX UNIT Overall Supply Current, Dynamic Supply Current, Static IDD IDDL VDD=3.3V, FCLK=50MHz, CL=15pF VDD = 3.3V, powered down via Power Down pin 43 mA 0.3 mA All input pins High-Level Input Voltage Low-Level Input Voltage High-Level Input Current VIH VDD=3.3V 2.0 VDD+0.3 V VIL VDD=3.3V VSS-0.3 0.8 V IIH -1 1 µA IIL -20 -36 -80 µA Low-Level Input Current (pull-up) High-Level Output Source Current Low-Level Output Source Current IxOH VDD=V(XIN) = 3.3V, VO=0V 10 21 30 mA IxOL VDD=3.3V, V(XIN)=VO=5.5V -10 -21 -30 mA Clock Outputs (CLK1, CLK2) High-Level Output Source Current Low-Level Output Sink Current Output Impedance IOH VO=2.4V -20 mA IOL VO=0.4V 23 mA ZOH VO=0.5VDD; output driving high 29 Ω ZOL Vo=0.5VDD; output driving low 27 Low Power EMI Reduction IC Notice: The information in this document is subject to change without notice. 6 of 15 November 2003 AS80M2516A rev 1.0 AC Timing Specifications Unless otherwise stated, VDD = 3.3.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not currently produciton tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. PARAMETER SYMBOL CONDITIONS/ DESCRIPTION CLOCK (MHz) MIN TYP MAX UNIT 140 MHz Overall Output Frequency fo VDD = 3.3V 4 Rise Time tr VO = 0.3V to 3.0V; CL = 15pF 2.1 ns Fall Time Tf VO = 3.0V to 0.3V; CL = 15pF 1.9 ns Clock Outputs (PLL A clock via FOUT1_CLK1/FOUT2_CLK1 pins) Duty Cycle Ratio of pulse width (as measured from rising edge to next falling edge 100 45 55 % at 2.5V) to one clock period On rising edges 500 µs apart at 2.5V relative to an ideal clock, CL = 15pF, fXIN=14.318MHz, FOUT = Jitter, Long Term (σy(τ))* Tj(LT) 100 45 50 165 100 110 50 390 50MHz, PLL–B inactive. On rising edges 500 µs apart at 2.5V relative to an ideal clock, CL = 15pF, fXIN=14.318MHz, FOUT = 50MHz, PLL –B active (60MHz) From rising edge to the next rising edge at 2.5V, CL = 15pF, fXIN=14.318MHz, FOUT = 50MHz Jitter, Period (peak-peak) Tj(∆P) PLL-B inactive. From rising edge to the next rising edge at 2.5V, CL = 15pF, fXIN=14.318MHz, FOUT = 50MHz PLL-B active (60MHz) Low Power EMI Reduction IC Notice: The information in this document is subject to change without notice. 7 of 15 ps November 2003 AS80M2516A rev 1.0 AC Timing Specifications (Continued) Unless otherwise stated, VDD = 3.3.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not currently produciton tested to any specific limits. MIN and MAX characterization data are ± 3 σ from typical. PARAMETER SYMBOL CONDITIONS/ CLOCK DESCRIPTION (MHz) Clock Outputs (PLL B clock via FOUT1_CLK2 / FOUT2_CLK2 pins) Duty Cycle Ratio of pulse width (as measured from rising edge to 100 next falling edge at 2.5V) to one clock period On rising edges 500 µs apart at 2.5V relative to an ideal clock, Jitter, Long CL = 15pF, fXIN=14.318MHz, Tj(LT) 100 Term (σy(τ))* FOUT = 50MHz , PLL –A inactive. On rising edges 500 µs apart at 2.5V relative to an ideal clock, CL = 15pF, fXIN=14.318MHz, 60 FOUT = 50MHz, PLL –A active (60MHz) From rising edge to the next Jitter, Period rising edge at 2.5V, CL = 15pF, Tj(∆P) 100 (peak-peak) fXIN=14.318MHz, FOUT = 50MHz PLL-B inactive. From rising edge to the next rising edge at 2.5V, CL = 15pF, 60 fXIN=14.318MHz, FOUT = 50MHz PLL-A active (50MHz) Clock Otput active from power up, Stabilization tSTB RUN Mode via Power Down Time pin MIN TYP MAX UNIT 55 % 45 Low Power EMI Reduction IC Notice: The information in this document is subject to change without notice. 45 ps 75 120 ps 400 100 8 of 15 ns November 2003 AS80M2516A rev 1.0 Modulation Domain Analyser Snapshot of 75MHz 0.75% Deviation Clock Spectrum Analyser Snapshot of 75MHz 0.75% Deviation Clock Low Power EMI Reduction IC Notice: The information in this document is subject to change without notice. 9 of 15 November 2003 AS80M2516A rev 1.0 General I2C Serial Interface Information The information in this section assumes familiarity with I2C programming. How to Write through I2C : How to Read through I2C: • Master (host) sends a start bit. • Master (host) will send start bit. • Master (host) sends the write address XX (H) • Master (host) sends the read address XX (H) • AS80M2516A device will acknowledge • AS80M2516A device will acknowledge • Master (host) sends a dummy command code • AS80M2516A device will send the byte count • AS80M2516A device will acknowledge • Master (host) acknowledges • Master (host) sends a dummy byte count • AS80M2516A device sends first byte (Byte 0) • AS80M2516A device will acknowledge • Master (host) starts sending first byte (Byte 0) through byte N - 1 • • AS80M2516A device will acknowledge each • Master (host) will send a stop bit (* N is the number of bytes) byte one at a time. • Master (host) will need to acknowledge each byte through byte N - 1 Master (host) sends a Stop bit Controller (Host) AS80M2516A (slave/receiver) Start Bit Controller (Host) Slave Address XX(H) ACK Start Bit Slave Address XX(H) Dummy Command ACK Code Date Byte Count ACK ACK Dummy byte count First byte (Byte 0) ACK ACK First byte (Byte 0) Second Byte (Byte ACK 1) Second Byte (Byte 1) ACK ACK ---- ------------- ---- Last Byte (Bye N-1) Last Byte (Bye N-1) ACK Stop Bit AS80M2516A (slave/receiver) Not Acknowledge Stop Bit Low Power EMI Reduction IC Notice: The information in this document is subject to change without notice. 10 of 15 November 2003 AS80M2516A rev 1.0 Software A demonstration board and software is available By pressing the drop down arrow of Port ID for the AS80M2516A. toolbar button ,any of the three parallel ports ( The software can operate under LPT1 LPT2 or LPT3 ) can be selected. The Windows 95 and Windows NT. selected parallel port is used for the I2C data The opening screen of the software is transfer. shown in figure 2. Opening screen Low Power EMI Reduction IC Notice: The information in this document is subject to change without notice. 11 of 15 November 2003 AS80M2516A rev 1.0 Programming the PLLs:- 1. Enter the input freq say 15 Mhz, in the Select the CGEN check box to enable the PLL 2. Enter the required output frequency say 3. Enter the percentage error say 0.01 in 4. Enter the modulation rate say 30 khz in 5. Select the second output frequency by input frequency box. 65 Mhz, in the out1 frequency box. and the EMI reduction check box to enable the spread spectrum on. Enter the input frequency (in the error box. Mhz) , output frequency (Mhz) , percentage error and modulation rate (Khz) in the respective input the modulation rate box. boxes. To enable the OUT1 OUT2 and REFOUT click the respective check box. To tristate all the outputs pressing the pull down menu of the out2 click the tristate check box. Select the type of the frequency. modulation between the center or down and enter The value of OUT2 frequency can the deviation (percentage ) in the respective input be selected as vco/2 , vco/3 , box. Profile type can be selected between the sine vco/4 , vco/5 , vco/6 , vco/8 , triangular or lexmark. vco/9 , vco/10 , vco/12 , vco/15 , vco/18 , vco/24 or vco/30. EMI reduction enable/disable option is only 6. available for the PLL1. Select the type of the deviation , percentage deviation and type of the profile. 7. Enter the data for PLL2 in a similar manner. Writing the data to the chip :There are two different ways of writing data to the chip. 1. Writing through the file. 2. Enter the required data in the respective forms and calculate and then write. For Example: 8. Press the CalcResult button to load the data in the ROM data panel. 9. To write this data to the chip press the I2CWrite button. Low Power EMI Reduction IC Notice: The information in this document is subject to change without notice. 12 of 15 November 2003 AS80M2516A rev 1.0 Results Window Reading the data from the Chip 1. To read the data from the chip through 2. The data can be seen in the rom data 3. This data which is read from the chip can I2C , press the I2CRead button. field. be saved in the file by clicking the Save button . Low Power EMI Reduction IC Notice: The information in this document is subject to change without notice. 13 of 15 November 2003 AS80M2516A rev 1.0 Package Information Low Power EMI Reduction IC Notice: The information in this document is subject to change without notice. 14 of 15 November 2003 AS80M2516A rev 1.0 Alliance Semiconductor Corporation 2595, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Preliminary Information Part Number: AS80M2516A Document Version: v1.0 © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in lifesupporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. Low Power EMI Reduction IC Notice: The information in this document is subject to change without notice. 15 of 15