ASM1232LP/LPS January 2005 rev 1.5 5V µP Power Supply Monitor and Reset Circuit General Description • Low-cost surface mount packages: 8-pin/16-pin SO, 8-pin DIP and 8-pin Micro SO packages The ASM1232LP/LPS is a fully integrated microprocessor • supervisor. It can halt and restart a “hung-up” microprocessor, Wide operating temperature -40°C to +85°C (N suffixed devices) restart a microprocessor after a power failure. It has a watchdog timer and external reset override. Applications and • Microprocessor Systems comparator circuits monitor the 5V, VCC input voltage status. • Computers During power-up or when the VCC power supply falls outside selectable tolerance limits, both RESET and RESET become • Controllers • Portable Equipment • Intelligent Instuments • Automotive Systems A precision temperature-compensated reference active. When VCC rises above the threshold voltage, the reset signals remain active for an additional 250ms minimum, allowing the power supply and system microprocessor to Typical Operating Circuit stabilize. The trip point tolerance signal, TOL, selects the trip level tolerance to be either 5% or 10%. +5V Each device has both a push-pull, active HIGH reset output and an open drain active LOW reset output. A debounced manual reset input, PBRST, activates the reset outputs for a 10kΩ ASM1232LP/LPS minimum period of 250ms. I/O ST There is a watchdog timer to stop and restart a microprocessor RESET that is “hung-up”. The watchdog timeouts periods are selectable: 150ms, 610ms and 1200ms. If the ST input is not GND TD µP RESET TOL strobed LOW before the time-out period expires, a reset is generated. Devices are available in 8-pin DIP, 16-pin SO and compact 8- Block Diagram pin MicroSO packages. ASM1232LP/LPS Key Features VCC 5V supply monitor • Selectable watchdog period • Debounce manual push-button reset input • + Reference 40kΩ • Power-up, power-down and brown out detection • 250ms minimum reset time • Active LOW open drain reset output and active HIGH push-pull output Selectable trip point tolerance: 5% or 10% RESET - VCC Precision temperature-compensated voltage reference and comparator. • Tolerance Selection TOL • RESET PBRST Push Button Debounce TD Voltage Sense Comparators ST Watchdog Transition Detector Reset & Watchdog Timer GND Alliance Semiconductor 2575 Augustine Drive . Santa Clara, CA 95054 . Tel: 408.855.4900 . Fax: 408.855.4999 . www.alsc.com Notice: The information in this document is subject to change without notice ASM1232LP/LPS January 2005 rev 1.5 Pin Configuration DIP/SO/MicroSO PBRST 1 TD 2 TOL 3 GND 4 ASM1232LP ASM1232LPS-2 ASM1232LPU SO 8 VCC NC 7 ST PBRST 2 16 NC 1 6 RESET NC 3 5 RESET TD 4 NC 15 VCC 14 NC 13 ST 5 12 NC TOL 6 11 RESET NC 7 10 NC GND 8 9 ASM1232LPS RESET Pin Description Pin # 8-Pin Package Pin # 16-Pin Package Pin Name 1 2 PBRST 2 4 TD 3 6 TOL 4 8 GND Function Debounced manual pushbutton RESET input. Watchdog time delay selection. (tTD = 150ms for TD = GND, tTD = 610ms for TD=Open, and tTD = 1200ms for TD = VCC). Selects 5% (TOL connected to GND) or 10% (TOL connected to VCC) trip point tolerance. Ground. Active HIGH reset output. RESET is active: 1. If VCC falls below the reset voltage trip point. 5 9 RESET 2. If PBRST is LOW. 3. If ST is not strobed LOW before the timeout period set by TD expires. 4. During power-up. 6 11 RESET Active LOW reset output. (See RESET). 7 13 ST Strobe input. 8 15 VCC 5V power. - 1,3,5,7, 10,12,14,16 NC No internal connection. 5V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 2 of 10 ASM1232LP/LPS January 2005 rev 1.5 Detailed Description tR The ASM1232LP/LPS monitors the microprocessor or VCCTP(MAX) VCCTP microcontroller power supply and generates reset signal, both active HIGH and Active LOW, that halt processor VCCTP(MIN) ~~ operation whenever the power supply voltage levels are outside a predetermined tolerance. tRPU VCC RESET RESET and RESET outputs VOH RESET is an active HIGH signal developed by a CMOS push-pull output stage and is the logical opposite to RESET. ~ ~~~ RESET is an active LOW signal. It is developed with an open drain driver. A pull up resistor of typical value 10kΩ to 50kΩ is required to connect with the output. VOL RESET Figure 1: Timing Diagram : Power Up Trip Point Tolerance Selection The TOL input is used to determine the level VCC can vary below 5V without asserting a reset. With TOL conected to VCC, RESET and RESET become active whenever VCC falls tF VCC VCCTP (MAX) VCCTP below 4.5V. RESET and RESET become active when the VCCTP (MIN) After VCC has risen above the trip point set by TOL, RESET ~~ VCC falls below 4.75V if TOL is connected to ground. RESET tRPD and RESET remain active for a minimum time period of 250ms. On power-down, once VCC falls below the reset less until VCC drops below 1.2V. The active HIGH reset signal Tolerance RESET Figure 2: Timing Diagram : Power Down is valid down to a VCC level of 1.2V also. Tolerance Select VOL ~ ~~ VOH threshold RESET stays LOW and is guaranteed to be 0.4V or TRIP Point Voltage (V) Min Nom Max TOL = VCC 10% 4.25 4.37 4.49 TOL = GND 5% 4.5 4.62 4.74 Application Information Manual Reset Operation Push-button switch input, PBRST, allows the user to override the internal trip point detection circuits and issue reset signals. The pushbutton input is debounced and is pulled HIGH through an internal 40kΩ resistor. 5V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 3 of 10 ASM1232LP/LPS January 2005 rev 1.5 When PBRST is held LOW for the minimum time tPB, both power-up after the supply voltage returns to an in-tolerance resets become active and remain active for a minimum time condition, the reset signal remains active for 250ms period of 250ms after PBRST returns HIGH. minimum, allowing the power supply and system microprocessor to stabilize. ST pulses as short as 20ns can The debounced input is guaranteed to recognize pulses be detected. greater than 20ms. No external pull-up resistor is required, Valid Strobe since PBRST is pulled HIGH by an internal 40kΩ resistor. Valid Strobe Invalid Strobe ST tST The PBRST can be driven from a TTL or CMOS logic line or tRST shorted to ground with a mechanical switch. tTD (min) ~ tTD (max) tPB PBRST RESET Note: ST is ignored whenever a reset is active VIH tPDLY Figure 5: Timing Diagram: Strobe Input VIL ~ ~~ RESET RESET Timeouts periods of approximately 150ms, 610ms or tRST 1,200ms are selected through the TD pin. VOH VOL Watchdog Time-out Period (ms) TD Voltage level Min Nom Max GND 62.5 150 250 Floating 250 610 1000 VCC 500 1200 2000 Figure 3: Timing Diagram: Pushbutton Reset 5V ASM1232LP/LPS 1 2 3 4 PBRST TD VCC 8 ST TOL RESET GND RESET 7 6 5 The watchdog timer can not be disabled. It must be strobed I/O µP with a high-to-low transition to avoid watchdog timeout and reset. RESET 5V Figure 4: Application Circuit: Pushbutton Reset ASM1232 LP/LPS 1 2 Watchdog Timer and ST Input A watchdog timer stops and restarts a microprocessor that is “hung-up”. The µP must toggle the ST input within a set period (as selectable through TD input) to verify proper software execution. If the ST is not toggled low within the minimum timeout period, reset signals become active. In 3 4 PBRST TD TOL GND MREQ VCC 8 ST RESET 7 6 10kΩ µP Decoder RESET Address 5 Bus Figure 6: Application Circuit: Watchdog Timer 5V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 4 of 10 ASM1232LP/LPS January 2005 rev 1.5 Absolute Maximum Ratings Parameter Min Max Unit Voltage on VCC -0.5 7 V Voltage on ST, TD -0.5 VCC + 0.5 V Voltage on PBRST, RESET, RESET -0.5 VCC + 0.5 V Operating Temperature Range (N suffixed devices) -40 +85 °C 0 70 °C +260 °C +125 °C 2 200 KV V Operating Temperature Range (others) Soldering Temperature (for 10 sec) Storage Temperature -55 ESD rating HBM MM Note: 1. Voltages are measured with respect to ground 2. These are stress ratings only and functional implication is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. DC Electrical Characteristics Unless otherwise stated, 4.5V <= VCC<= 5.5V and over the operating temperature range of 0°C to 70°C (-40°C to +85°C. for N devices). All voltages are referenced to ground. Parameter Symbol Conditions Min Typ Max Unit Supply Voltage VCC 4.5 5.5 V ST and PBRST Input High Level VIH 2 VCC + 0.3 V ST and PBRST Input Low Level VIL -0.3 0.8 V VCC Trip Point (TOL = GND) VCCTP 4.50 4.62 4.74 V VCC Trip Point (TOL = VCC) VCCTP 4.25 4.37 4.49 V Watchdog Timeout Period tTD TD = GND 62.5 150 250 ms Watchdog Timeout Period tTD TD = VCC 500 1200 2000 ms Watchdog Timeout Period tTD TD Floating 250 610 1000 ms Output Voltage VOH I=-500µA, Note 3 VCC - 0.5 VCC - 0.1 V Output Current IOH Output = 2.4V, Note 2 -8 -10 mA Output Current IOL Output = 0.4V 10 5V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice mA 5 of 10 ASM1232LP/LPS January 2005 rev 1.5 Parameter Symbol Input Leakage RESET Low Level Conditions IIL Note 1 VOL Note 3 Internal Pull-up Resistor Min Typ -1.0 Note 1 Max Unit 1.0 µA 0.4 V 40 kΩ Operating Current (CMOS) ICC1 30 µA Input Capacitance CIN 5 pF COUT 10 pF Output Capacitance PBRST Manual Reset Minimum Low Time tPB Reset Active Time tRST ST Pulse Width tST VCC Fail Detect to RESET or VCC Slew Rate tF PBRST Stable LOW to RESET and RESET Active VCC Detect to RESET or RESET VCC Slew Rate 20 250 Note 4 ms 610 tR tRISE = 5µs 4.25V to 4.75V 8 300 250 0 µs µs tPDLY tRPU ms ns 5 4.75V to 4.25V 1000 20 tRPD RESET inactive PBRST = VIL 610 20 ms 1000 ms ns Notes 1. PBRST is internally pulled HIGH to VCC through a nominal 40kΩ resistor. 2. RESET is an open drain output. 3. RESET remains within 0.5V of VCC on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down until VCC falls below 2.0V. 4. Must not exceed the minimum watchdog time-out period (tTD). The watchdogcircuit cannot be disabled. To avoid a reset, ST must be strobed. 5V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 6 of 10 ASM1232LP/LPS January 2005 rev 1.5 Package Information MicroSO (8-Pin) Inches Millimeteres Min Max Min Max MicroSO (8-Pin) A 0.032 0.044 0.81 1.10 A1 0.002 0.006 0.05 0.15 A2 0.030 0.038 0.76 0.97 b 0.012 BSC 0.004 0.008 0.10 D 0.114 0.122 2.90 e 0.0256 BSC 0.20 3.10 0.65 BSC E 0.184 0.200 4.67 5.08 E1 0.114 0.122 2.90 3.10 L 0.016 0.026 0.41 S a 0.0206 BSC 0° 0.66 0.52 BSC 6° 0° 6° SO (8-Pin) SO (8-Pin) H E A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 A2 0.049 0.059 1.25 1.50 B 0.012 0.020 0.31 0.51 C 0.007 0.010 0.18 D D 0.193 BSC A C A1 B Plastic DIP (8-Pin) D θ L 0.25 4.90 BSC E 0.154 BSC 3.91 BSC e 0.050 BSC 1.27 BSC H A2 e 0.30 BSC C 0.236 BSC L 0.016 θ 0° 6.00 BSC 0.050 0.41 1.27 8° 0° 8° Plastic DIP (8-Pin) A - 0.210 - 5.33 A1 0.015 - 0.38 - A2 0.115 0.195 2.92 4.95 b 0.014 0.022 0.36 0.56 b2 0.045 0.070 1.14 1.78 C 0.008 0.014 0.20 0.36 D 0.355 0.400 9.02 10.16 E 0.300 0.325 7.62 8.26 E1 0.240 0.280 6.10 e 0.100 BSC 7.11 2.54 BSC eB - 0.430 - 10.92 L 0.115 0.150 2.92 3.81 5V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 7 of 10 ASM1232LP/LPS January 2005 rev 1.5 SO (16-Pin) PIN 1 ID 1 8 E 9 H 16 D A2 D A e h Seating Plane C θ 0.004 L A1 B SO (16-Pin)* Inches Millimeter Min Max Min Max A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 A2 0.049 0.059 1.25 1.50 B 0.013 0.022 0.33 0.53 C 0.008 0.012 0.19 0.27 D 0.386 0.394 9.80 10.01 E 0.150 0.157 3.80 4.00 e 0.050 BSC 1.27 BSC H 0.228 0.244 5.80 6.20 h 0.010 0.016 0.25 0.41 L 0.016 0.035 0.40 0.89 θ 0° 8° 0° 8° * JEDEC Drawing MS-013AA 5V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 8 of 10 ASM1232LP/LPS January 2005 rev 1.5 Ordering Information Package Operating Temperature Range Maximum Supply Current (µA) Voltage Monitoring Application Package Marking ASM1232LP 8L PDIP 0°C to +70°C 30 5V ASM1232LP ASM1232LPN 8L PDIP -40° C to +85°C 30 5V ASM1232LPN ASM1232LPS 16L SOIC 0°C to +70°C 30 5V ASM1232LPS ASM1232LPS-2 8L SOIC 0°C to +70° C 30 5V ASM1232LPS-2 ASM1232LPSN 16L SOIC -40°C to +85°C 30 5V ASM1232LPSN ASM1232LPSN-2 8L SOIC -40°C to +85°C 30 5V ASM1232LPSN-2 ASM1232LPU 8L MSOP 0°C to +70°C 30 5V ASM1232LP ASM1232LPUN 8L MSOP -40°C to +85°C 30 5V ASM1232LPN ASM1232LPF 8L PDIP 0°C to +70°C 30 5V ASM1232LPF ASM1232LPNF 8L PDIP -40°C to +85°C 30 5V ASM1232LPNF ASM1232LPS-2F 8L SOIC 0°C to +70°C 30 5V ASM1232LPS-2F ASM1232LPSF 16L SOIC 0°C to +70°C 30 5V ASM1232LPSF ASM1232LPSN-2F 8L SOIC -40°C to +85°C 30 5V ASM1232LPSN-2F ASM1232LPSNF 16L SOIC -40°C to +85°C 30 5V ASM1232LPSNF ASM1232LPUF 8L MSOP 0°C to +70°C 30 5V ASM1232LPF ASM1232LPUNF 8L MSOP -40°C to +85°C 30 5V ASM1232LPNF Part Number TIN-LEAD DEVICES LEAD FREE DEVICES 5V µP Power Supply Monitor and Reset Circuit Notice: The information in this document is subject to change without notice 9 of 10 ASM1232LP/LPS Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM1232LP/LPS Document Version: 1.5 © Copyright 2003 Alliance Semiconductor Corporation. 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