ALTERA FLEX10KE

FLEX 10KE
®
Embedded Programmable
Logic Device
January 2003, ver. 2.5
Features...
Data Sheet
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Embedded programmable logic devices (PLDs), providing
system-on-a-programmable-chip (SOPC) integration in a single
device
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Enhanced embedded array for implementing megafunctions
such as efficient memory and specialized logic functions
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Dual-port capability with up to 16-bit width per embedded array
block (EAB)
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Logic array for general logic functions
High density
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30,000 to 200,000 typical gates (see Tables 1 and 2)
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Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be
used without reducing logic capacity
System-level features
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MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or
5.0-V devices
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Low power consumption
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Bidirectional I/O performance (tSU and tCO) up to 212 MHz
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Fully compliant with the PCI Special Interest Group (PCI SIG)
PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at
33 MHz or 66 MHz
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-1 speed grade devices are compliant with PCI Local Bus
Specification, Revision 2.2, for 5.0-V operation
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Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic
For information on 5.0-V FLEX® 10K or 3.3-V FLEX 10KA devices, see the
FLEX 10K Embedded Programmable Logic Family Data Sheet.
Table 1. FLEX 10KE Device Features
Feature
EPF10K30E
EPF10K50E
EPF10K50S
Typical gates (1)
30,000
50,000
Maximum system gates
119,000
199,000
1,728
2,880
Logic elements (LEs)
EABs
Total RAM bits
Maximum user I/O pins
Altera Corporation
DS-F10KE-2.5
6
10
24,576
40,960
220
254
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FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 2. FLEX 10KE Device Features
Feature
EPF10K100E (2)
EPF10K130E
EPF10K200E
EPF10K200S
Typical gates (1)
100,000
130,000
200,000
Maximum system gates
257,000
342,000
513,000
4,992
6,656
9,984
12
16
24
49,152
65,536
98,304
338
413
470
Logic elements (LEs)
EABs
Total RAM bits
Maximum user I/O pins
Note to tables:
(1)
(2)
The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum
system gates.
New EPF10K100B designs should use EPF10K100E devices.
...and More
Features
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Fabricated on an advanced process and operate with a 2.5-V
internal supply voltage
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In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
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ClockLockTM and ClockBoostTM options for reduced clock
delay/skew and clock multiplication
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Built-in low-skew clock distribution trees
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100% functional testing of all devices; test vectors or scan chains
are not required
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Pull-up on I/O pins before and during configuration
Flexible interconnect
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FastTrack® Interconnect continuous routing structure for fast,
predictable interconnect delays
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Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
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Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
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Tri-state emulation that implements internal tri-state buses
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Up to six global clock signals and four global clear signals
Powerful I/O pins
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Individual tri-state output enable control for each pin
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Open-drain option on each I/O pin
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Programmable output slew-rate control to reduce switching
noise
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Clamp to VCCIO user-selectable on a pin-by-pin basis
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Supports hot-socketing
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
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Software design support and automatic place-and-route provided by
Altera’s development systems for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800
Flexible package options
–
Available in a variety of packages with 144 to 672 pins, including
the innovative FineLine BGATM packages (see Tables 3 and 4)
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SameFrameTM pin-out compatibility between FLEX 10KA and
FLEX 10KE devices across a range of device densities and pin
counts
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
DesignWare components, Verilog HDL, VHDL, and other interfaces
to popular EDA tools from manufacturers such as Cadence,
Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity,
VeriBest, and Viewlogic
Table 3. FLEX 10KE Package Options & I/O Pin Count
Device
144-Pin
TQFP
208-Pin
PQFP
EPF10K30E
102
147
176
220
220 (3)
EPF10K50E
102
147
189
191
254
254 (3)
EPF10K50S
102
147
189
191
220
254
254 (3)
147
189
191
274
338
338 (3)
274
369
EPF10K100E
EPF10K130E
240-Pin
PQFP
RQFP
Notes (1), (2)
186
256-Pin 356-Pin 484-Pin 599-Pin
FineLine
BGA
FineLine
PGA
BGA
BGA
EPF10K200E
EPF10K200S
182
274
369
600-Pin 672-Pin
BGA
FineLine
BGA
424
413
470
470
470
470
470
470
Notes:
(1)
(2)
(3)
FLEX 10KE device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), pin-grid array (PGA), and ball-grid array (BGA) packages.
Devices in the same package are pin-compatible, although some devices have more I/O pins than others. When
planning device migration, use the I/O pins that are common to all devices.
This option is supported with a 484-pin FineLine BGA package. By using SameFrame pin migration, all
FineLine BGA packages are pin-compatible. For example, a board can be designed to support 256-pin, 484-pin, and
672-pin FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration
is set.
Altera Corporation
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FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 4. FLEX 10KE Package Sizes
Device
144Pin
TQFP
208-Pin
PQFP
240-Pin
PQFP
RQFP
256-Pin
FineLine
BGA
Pitch (mm)
0.50
0.50
0.50
1.0
1.27
1.0
–
1.27
1.0
Area (mm 2)
484
936
1,197
289
1,225
529
3,904
2,025
729
Length × width 22 × 22 30.6 × 30.6 34.6 × 34.6 17 × 17
(mm × mm)
General
Description
356Pin
BGA
484-Pin
FineLine
BGA
599-Pin
PGA
600Pin
BGA
672-Pin
FineLine
BGA
35 × 35 23 × 23 62.5 × 62.5 45 × 45 27 × 27
Altera FLEX 10KE devices are enhanced versions of FLEX 10K devices.
Based on reconfigurable CMOS SRAM elements, the FLEX architecture
incorporates all features necessary to implement common gate array
megafunctions. With up to 200,000 typical gates, FLEX 10KE devices
provide the density, speed, and features to integrate entire systems,
including multiple 32-bit buses, into a single device.
The ability to reconfigure FLEX 10KE devices enables 100% testing prior
to shipment and allows the designer to focus on simulation and design
verification. FLEX 10KE reconfigurability eliminates inventory
management for gate array designs and generation of test vectors for fault
coverage.
Table 5 shows FLEX 10KE performance for some common designs. All
performance values were obtained with Synopsys DesignWare or LPM
functions. Special design techniques are not required to implement the
applications; the designer simply infers or instantiates a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
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Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 5. FLEX 10KE Performance
Application
Resources Used
Performance
Units
LEs
EABs
16-bit loadable counter
16
0
-1 Speed Grade -2 Speed Grade -3 Speed Grade
285
250
200
MHz
16-bit accumulator
16
0
285
250
200
MHz
16-to-1 multiplexer (1)
10
0
3.5
4.9
7.0
ns
16-bit multiplier with 3-stage
pipeline (2)
592
0
156
131
93
MHz
256 × 16 RAM read cycle
speed (2)
0
1
196
154
118
MHz
256 × 16 RAM write cycle
speed (2)
0
1
185
143
106
MHz
Notes:
(1)
(2)
This application uses combinatorial inputs and outputs.
This application uses registered inputs and outputs.
Table 6 shows FLEX 10KE performance for more complex designs. These
designs are available as Altera MegaCore® functions.
Table 6. FLEX 10KE Performance for Complex Designs
Application
LEs Used
Performance
Units
-1 Speed Grade -2 Speed Grade -3 Speed Grade
8-bit, 16-tap parallel finite impulse
response (FIR) filter
8-bit, 512-point fast Fourier
transform (FFT) function
a16450 universal asynchronous
receiver/transmitter (UART)
597
192
156
116
MSPS
1,854
23.4
28.7
38.9
µs (1)
113
92
68
MHz
36
28
20.5
MHz
342
Note:
(1)
These values are for calculation time. Calculation time = number of clocks required/fmax. Number of clocks
required = ceiling [log 2 (points)/2] × [points +14 + ceiling]
Altera Corporation
5
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Similar to the FLEX 10KE architecture, embedded gate arrays are the
fastest-growing segment of the gate array market. As with standard gate
arrays, embedded gate arrays implement general logic in a conventional
“sea-of-gates” architecture. Additionally, embedded gate arrays have
dedicated die areas for implementing large, specialized functions. By
embedding functions in silicon, embedded gate arrays reduce die area
and increase speed when compared to standard gate arrays. While
embedded megafunctions typically cannot be customized, FLEX 10KE
devices are programmable, providing the designer with full control over
embedded megafunctions and general logic, while facilitating iterative
design changes during debugging.
Each FLEX 10KE device contains an embedded array and a logic array.
The embedded array is used to implement a variety of memory functions
or complex logic functions, such as digital signal processing (DSP), wide
data-path manipulation, microcontroller applications, and datatransformation functions. The logic array performs the same function as
the sea-of-gates in the gate array and is used to implement general logic
such as counters, adders, state machines, and multiplexers. The
combination of embedded and logic arrays provides the high
performance and high density of embedded gate arrays, enabling
designers to implement an entire system on a single device.
FLEX 10KE devices are configured at system power-up with data stored
in an Altera serial configuration device or provided by a system
controller. Altera offers the EPC1, EPC2, and EPC16 configuration
devices, which configure FLEX 10KE devices via a serial data stream.
Configuration data can also be downloaded from system RAM or via the
Altera BitBlasterTM, ByteBlasterMVTM, or MasterBlaster download cables.
After a FLEX 10KE device has been configured, it can be reconfigured
in-circuit by resetting the device and loading new data. Because
reconfiguration requires less than 85 ms, real-time changes can be made
during system operation.
FLEX 10KE devices contain an interface that permits microprocessors to
configure FLEX 10KE devices serially or in-parallel, and synchronously or
asynchronously. The interface also enables microprocessors to treat a
FLEX 10KE device as memory and configure it by writing to a virtual
memory location, making it easy to reconfigure the device.
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Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
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For more information on FLEX device configuration, see the following
documents:
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Configuration Devices for APEX & FLEX Devices Data Sheet
BitBlaster Serial Download Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
MasterBlaster Download Cable Data Sheet
Application Note 116 (Configuring APEX 20K, FLEX 10K, & FLEX 6000
Devices)
FLEX 10KE devices are supported by the Altera development systems,
which are integrated packages that offer schematic, text (including
AHDL), and waveform design entry, compilation and logic synthesis, full
simulation and worst-case timing analysis, and device configuration. The
Altera software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL,
and other interfaces for additional design entry and simulation support
from other industry-standard PC- and UNIX workstation-based EDA
tools.
The Altera software works easily with common gate array EDA tools for
synthesis and simulation. For example, the Altera software can generate
Verilog HDL files for simulation with tools such as Cadence Verilog-XL.
Additionally, the Altera software contains EDA libraries that use devicespecific features such as carry chains, which are used for fast counter and
arithmetic functions. For instance, the Synopsys Design Compiler library
supplied with the Altera development system includes DesignWare
functions that are optimized for the FLEX 10KE architecture.
The Altera development system runs on Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800.
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Altera Corporation
See the MAX+PLUS II Programmable Logic Development System & Software
Data Sheet and the Quartus Programmable Logic Development System &
Software Data Sheet for more information.
7
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Functional
Description
Each FLEX 10KE device contains an enhanced embedded array to
implement memory and specialized logic functions, and a logic array to
implement general logic.
The embedded array consists of a series of EABs. When implementing
memory functions, each EAB provides 4,096 bits, which can be used to
create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.
When implementing logic, each EAB can contribute 100 to 600 gates
towards complex logic functions, such as multipliers, microcontrollers,
state machines, and DSP functions. EABs can be used independently, or
multiple EABs can be combined to implement larger functions.
The logic array consists of logic array blocks (LABs). Each LAB contains
eight LEs and a local interconnect. An LE consists of a four-input look-up
table (LUT), a programmable flipflop, and dedicated signal paths for carry
and cascade functions. The eight LEs can be used to create medium-sized
blocks of logic—such as 8-bit counters, address decoders, or state
machines—or combined across LABs to create larger logic blocks. Each
LAB represents about 96 usable gates of logic.
Signal interconnections within FLEX 10KE devices (as well as to and from
device pins) are provided by the FastTrack Interconnect routing structure,
which is a series of fast, continuous row and column channels that run the
entire length and width of the device.
Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect routing structure. Each IOE
contains a bidirectional I/O buffer and a flipflop that can be used as either
an output or input register to feed input, output, or bidirectional signals.
When used with a dedicated clock pin, these registers provide exceptional
performance. As inputs, they provide setup times as low as 0.9 ns and
hold times of 0 ns. As outputs, these registers provide clock-to-output
times as low as 3.0 ns. IOEs provide a variety of features, such as JTAG
BST support, slew-rate control, tri-state buffers, and open-drain outputs.
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Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 1 shows a block diagram of the FLEX 10KE architecture. Each
group of LEs is combined into an LAB; groups of LABs are arranged into
rows and columns. Each row also contains a single EAB. The LABs and
EABs are interconnected by the FastTrack Interconnect routing structure.
IOEs are located at the end of each row and column of the FastTrack
Interconnect routing structure.
Figure 1. FLEX 10KE Device Block Diagram
Embedded Array Block (EAB)
I/O Element
(IOE)
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
Column
Interconnect
Logic Array
EAB
Logic Array
Block (LAB)
IOE
IOE
IOE
IOE
Logic Element (LE)
Row
Interconnect
EAB
Local Interconnect
Logic
Array
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
Embedded Array
FLEX 10KE devices provide six dedicated inputs that drive the flipflops’
control inputs and ensure the efficient distribution of high-speed, lowskew (less than 1.5 ns) control signals. These signals use dedicated routing
channels that provide shorter delays and lower skews than the FastTrack
Interconnect routing structure. Four of the dedicated inputs drive four
global signals. These four global signals can also be driven by internal
logic, providing an ideal solution for a clock divider or an internally
generated asynchronous clear signal that clears many registers in the
device.
Altera Corporation
9
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Embedded Array Block
The EAB is a flexible block of RAM, with registers on the input and output
ports, that is used to implement common gate array megafunctions.
Because it is large and flexible, the EAB is suitable for functions such as
multipliers, vector scalars, and error correction circuits. These functions
can be combined in applications such as digital filters and
microcontrollers.
Logic functions are implemented by programming the EAB with a readonly pattern during configuration, thereby creating a large LUT. With
LUTs, combinatorial functions are implemented by looking up the results,
rather than by computing them. This implementation of combinatorial
functions can be faster than using algorithms implemented in general
logic, a performance advantage that is further enhanced by the fast access
times of EABs. The large capacity of EABs enables designers to implement
complex functions in one logic level without the routing delays associated
with linked LEs or field-programmable gate array (FPGA) RAM blocks.
For example, a single EAB can implement any function with 8 inputs and
16 outputs. Parameterized functions such as LPM functions can take
advantage of the EAB automatically.
The FLEX 10KE EAB provides advantages over FPGAs, which implement
on-board RAM as arrays of small, distributed RAM blocks. These small
FPGA RAM blocks must be connected together to make RAM blocks of
manageable size. The RAM blocks are connected together using
multiplexers implemented with more logic blocks. These extra
multiplexers cause extra delay, which slows down the RAM block. FPGA
RAM blocks are also prone to routing problems because small blocks of
RAM must be connected together to make larger blocks. In contrast, EABs
can be used to implement large, dedicated blocks of RAM that eliminate
these timing and routing concerns.
The FLEX 10KE enhanced EAB adds dual-port capability to the existing
EAB structure. The dual-port structure is ideal for FIFO buffers with one
or two clocks. The FLEX 10KE EAB can also support up to 16-bit-wide
RAM blocks and is backward-compatible with any design containing
FLEX 10K EABs. The FLEX 10KE EAB can act in dual-port or single-port
mode. When in dual-port mode, separate clocks may be used for EAB read
and write sections, which allows the EAB to be written and read at
different rates. It also has separate synchronous clock enable signals for
the EAB read and write sections, which allow independent control of
these sections.
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Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
The EAB can also be used for bidirectional, dual-port memory
applications where two ports read or write simultaneously. To implement
this type of dual-port memory, two EABs are used to support two
simultaneous read or writes.
Alternatively, one clock and clock enable can be used to control the input
registers of the EAB, while a different clock and clock enable control the
output registers (see Figure 2).
Figure 2. FLEX 10KE Device in Dual-Port RAM Mode
Notes (1)
Dedicated Inputs &
Global Signals
Dedicated Clocks
Row Interconnect
2
RAM/ROM
256 × 16
512 × 8
Data In
1,024 × 4
2,048 × 2
4
data[ ]
D
Q
ENA
Data Out
4, 8, 16, 32
D
ENA
rdaddress[ ]
EAB Local
Interconnect (2)
4, 8
Read Address
D
Q
ENA
wraddress[ ]
Write Address
D
rden
Q
Q
4, 8, 16, 32
ENA
Read Enable
wren
D
Q
ENA
outclocken
Write Enable
inclocken
D
ENA
inclock
outclock
Q
Write
Pulse
Generator
Multiplexers allow read
address and read
enable registers to be
clocked by inclock or
outclock signals.
Column Interconnect
Notes:
(1)
(2)
All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset.
EPF10K30E and EPF10K50E devices have 88 EAB local interconnect channels; EPF10K100E, EPF10K130E, and
EPF10K200E devices have 104 EAB local interconnect channels.
Altera Corporation
11
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
The EAB can also use Altera megafunctions to implement dual-port RAM
applications where both ports can read or write, as shown in Figure 3.
Figure 3. FLEX 10KE EAB in Dual-Port RAM Mode
Port A
Port B
address_a[]
address_b[]
data_a[]
we_a
clkena_a
Clock A
data_b[]
we_b
clkena_b
Clock B
The FLEX 10KE EAB can be used in a single-port mode, which is useful for
backward-compatibility with FLEX 10K designs (see Figure 4).
12
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 4. FLEX 10KE Device in Single-Port RAM Mode
Dedicated Inputs
& Global Signals
Dedicated
Clocks
2
Chip-Wide
Reset
Row Interconnect
4
D
Q
8, 4, 2, 1
Data Out
EAB Local
Interconnect (1)
4, 8, 16, 32
RAM/ROM
256 × 16
512 × 8
Data In
1,024 × 4
2,048 × 2
D
Q
4, 8
Address
D
Q
8, 9, 10, 11
4, 8, 16, 32
Write Enable
D
Q
Column Interconnect
Note:
(1)
EPF10K30E, EPF10K50E, and EPF10K50S devices have 88 EAB local interconnect channels; EPF10K100E,
EPF10K130E, EPF10K200E, and EPF10K200S devices have 104 EAB local interconnect channels.
EABs can be used to implement synchronous RAM, which is easier to use
than asynchronous RAM. A circuit using asynchronous RAM must
generate the RAM write enable signal, while ensuring that its data and
address signals meet setup and hold time specifications relative to the
write enable signal. In contrast, the EAB’s synchronous RAM generates its
own write enable signal and is self-timed with respect to the input or write
clock. A circuit using the EAB’s self-timed RAM must only meet the setup
and hold time specifications of the global clock.
Altera Corporation
13
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
When used as RAM, each EAB can be configured in any of the following
sizes: 256 × 16, 512 × 8, 1,024 × 4, or 2,048 × 2 (see Figure 5).
Figure 5. FLEX 10KE EAB Memory Configurations
256 × 16
512 × 8
2,048 × 2
1,024 × 4
Larger blocks of RAM are created by combining multiple EABs. For
example, two 256 × 16 RAM blocks can be combined to form a 256 × 32
block; two 512 × 8 RAM blocks can be combined to form a 512 × 16 block
(see Figure 6).
Figure 6. Examples of Combining FLEX 10KE EABs
256 × 32
512 × 16
256 × 16
512 × 8
256 × 16
512 × 8
If necessary, all EABs in a device can be cascaded to form a single RAM
block. EABs can be cascaded to form RAM blocks of up to 2,048 words
without impacting timing. The Altera software automatically combines
EABs to meet a designer’s RAM specifications.
14
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
EABs provide flexible options for driving and controlling clock signals.
Different clocks and clock enables can be used for reading and writing to
the EAB. Registers can be independently inserted on the data input, EAB
output, write address, write enable signals, read address, and read enable
signals. The global signals and the EAB local interconnect can drive write
enable, read enable, and clock enable signals. The global signals,
dedicated clock pins, and EAB local interconnect can drive the EAB clock
signals. Because the LEs drive the EAB local interconnect, the LEs can
control write enable, read enable, clear, clock, and clock enable signals.
An EAB is fed by a row interconnect and can drive out to row and column
interconnects. Each EAB output can drive up to two row channels and up
to two column channels; the unused row channel can be driven by other
LEs. This feature increases the routing resources available for EAB
outputs (see Figures 2 and 4). The column interconnect, which is adjacent
to the EAB, has twice as many channels as other columns in the device.
Logic Array Block
An LAB consists of eight LEs, their associated carry and cascade chains,
LAB control signals, and the LAB local interconnect. The LAB provides
the coarse-grained structure to the FLEX 10KE architecture, facilitating
efficient routing with optimum device utilization and high performance
(see Figure 7).
Altera Corporation
15
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 7. FLEX 10KE LAB
Dedicated Inputs &
Global Signals
(1)
Row Interconnect
ter
terconnect
6
LAB Local
Interconnect
terconnect (2)
ter
(2)
16
6
See Figure 12
for details.
4
LAB Control
Signals
nal
nals
4
Carry-In &
Cascade-In
2
4
LE1
4
LE2
4
LE3
4
LE4
4
LE5
4
LE6
4
LE7
4
LE8
8
2
8
24 to 48
Column-to-Row
Interconnect
ter
terconnect
Column
Interconnect
ter
terconnect
8
16
Carry-Out &
Cascade-Out
Notes:
(1)
(2)
16
EPF10K30E, EPF10K50E, and EPF10K50S devices have 22 inputs to the LAB local interconnect channel from the
row; EPF10K100E, EPF10K130E, EPF10K200E, and EPF10K200S devices have 26.
EPF10K30E, EPF10K50E, and EPF10K50S devices have 30 LAB local interconnect channels; EPF10K100E,
EPF10K130E, EPF10K200E, and EPF10K200S devices have 34.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Each LAB provides four control signals with programmable inversion
that can be used in all eight LEs. Two of these signals can be used as clocks,
the other two can be used for clear/preset control. The LAB clocks can be
driven by the dedicated clock input pins, global signals, I/O signals, or
internal signals via the LAB local interconnect. The LAB preset and clear
control signals can be driven by the global signals, I/O signals, or internal
signals via the LAB local interconnect. The global control signals are
typically used for global clock, clear, or preset signals because they
provide asynchronous control with very low skew across the device. If
logic is required on a control signal, it can be generated in one or more LE
in any LAB and driven into the local interconnect of the target LAB. In
addition, the global control signals can be generated from LE outputs.
Logic Element
The LE, the smallest unit of logic in the FLEX 10KE architecture, has a
compact size that provides efficient logic utilization. Each LE contains a
four-input LUT, which is a function generator that can quickly compute
any function of four variables. In addition, each LE contains a
programmable flipflop with a synchronous clock enable, a carry chain,
and a cascade chain. Each LE drives both the local and the FastTrack
Interconnect routing structure (see Figure 8).
Figure 8. FLEX 10KE Logic Element
data1
data2
data3
data4
Look-Up
Table
(LUT)
Carry-In
Cascade-In
Carry
Chain
Cascade
Chain
Register Bypass
D
PRN
Q
Programmable
Register
FastTrack
Interconnect
ENA
CLRN
LAB Local
Interconnect
labctrl1
labctrl2
Clear/
Preset
Logic
Chip-Wide
Reset
Clock
Select
labctrl3
labctrl4
Carry-Out
Altera Corporation
Cascade-Out
17
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
The programmable flipflop in the LE can be configured for D, T, JK, or SR
operation. The clock, clear, and preset control signals on the flipflop can
be driven by global signals, general-purpose I/O pins, or any internal
logic. For combinatorial functions, the flipflop is bypassed and the output
of the LUT drives the output of the LE.
The LE has two outputs that drive the interconnect: one drives the local
interconnect and the other drives either the row or column FastTrack
Interconnect routing structure. The two outputs can be controlled
independently. For example, the LUT can drive one output while the
register drives the other output. This feature, called register packing, can
improve LE utilization because the register and the LUT can be used for
unrelated functions.
The FLEX 10KE architecture provides two types of dedicated high-speed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and cascade chains. The carry chain supports
high-speed counters and adders and the cascade chain implements
wide-input functions with minimum delay. Carry and cascade chains
connect all LEs in a LAB as well as all LABs in the same row. Intensive use
of carry and cascade chains can reduce routing flexibility. Therefore, the
use of these chains should be limited to speed-critical portions of a design.
Carry Chain
The carry chain provides a very fast (as low as 0.2 ns) carry-forward
function between LEs. The carry-in signal from a lower-order bit drives
forward into the higher-order bit via the carry chain, and feeds into both
the LUT and the next portion of the carry chain. This feature allows the
FLEX 10KE architecture to implement high-speed counters, adders, and
comparators of arbitrary width efficiently. Carry chain logic can be
created automatically by the Altera Compiler during design processing,
or manually by the designer during design entry. Parameterized functions
such as LPM and DesignWare functions automatically take advantage of
carry chains.
Carry chains longer than eight LEs are automatically implemented by
linking LABs together. For enhanced fitting, a long carry chain skips
alternate LABs in a row. A carry chain longer than one LAB skips either
from even-numbered LAB to even-numbered LAB, or from oddnumbered LAB to odd-numbered LAB. For example, the last LE of the
first LAB in a row carries to the first LE of the third LAB in the row. The
carry chain does not cross the EAB at the middle of the row. For instance,
in the EPF10K50E device, the carry chain stops at the eighteenth LAB and
a new one begins at the nineteenth LAB.
18
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 9 shows how an n-bit full adder can be implemented in n + 1 LEs
with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register can be bypassed for simple adders or used
for an accumulator function. Another portion of the LUT and the carry
chain logic generates the carry-out signal, which is routed directly to the
carry-in signal of the next-higher-order bit. The final carry-out signal is
routed to an LE, where it can be used as a general-purpose signal.
Figure 9. FLEX 10KE Carry Chain Operation (n-Bit Full Adder)
Carry-In
a1
b1
LUT
s1
Register
Carry Chain
LE1
a2
b2
LUT
s2
Register
Carry Chain
LE2
an
bn
LUT
sn
Register
Carry Chain
LEn
LUT
Register
Carry-Out
Carry Chain
LEn + 1
Altera Corporation
19
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Cascade Chain
With the cascade chain, the FLEX 10KE architecture can implement
functions that have a very wide fan-in. Adjacent LUTs can be used to
compute portions of the function in parallel; the cascade chain serially
connects the intermediate values. The cascade chain can use a logical AND
or logical OR (via De Morgan’s inversion) to connect the outputs of
adjacent LEs. An a delay as low as 0.6 ns per LE, each additional LE
provides four more inputs to the effective width of a function. Cascade
chain logic can be created automatically by the Altera Compiler during
design processing, or manually by the designer during design entry.
Cascade chains longer than eight bits are implemented automatically by
linking several LABs together. For easier routing, a long cascade chain
skips every other LAB in a row. A cascade chain longer than one LAB
skips either from even-numbered LAB to even-numbered LAB, or from
odd-numbered LAB to odd-numbered LAB (e.g., the last LE of the first
LAB in a row cascades to the first LE of the third LAB). The cascade chain
does not cross the center of the row (e.g., in the EPF10K50E device, the
cascade chain stops at the eighteenth LAB and a new one begins at the
nineteenth LAB). This break is due to the EAB’s placement in the middle
of the row.
Figure 10 shows how the cascade function can connect adjacent LEs to
form functions with a wide fan-in. These examples show functions of
4n variables implemented with n LEs. The LE delay is 0.9 ns; the cascade
chain delay is 0.6 ns. With the cascade chain, 2.7 ns are needed to decode
a 16-bit address.
Figure 10. FLEX 10KE Cascade Chain Operation
AND Cascade Chain
d[3..0]
OR Cascade Chain
d[3..0]
LUT
LUT
LE1
d[7..4]
LE1
d[7..4]
LUT
LUT
LE2
d[(4n – 1)..(4n – 4)]
d[(4n – 1)..(4n – 4)]
LUT
LEn
20
LE2
LUT
LEn
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
LE Operating Modes
The FLEX 10KE LE can operate in the following four modes:
■
■
■
■
Normal mode
Arithmetic mode
Up/down counter mode
Clearable counter mode
Each of these modes uses LE resources differently. In each mode, seven
available inputs to the LE—the four data inputs from the LAB local
interconnect, the feedback from the programmable register, and the
carry-in and cascade-in from the previous LE—are directed to different
destinations to implement the desired logic function. Three inputs to the
LE provide clock, clear, and preset control for the register. The Altera
software, in conjunction with parameterized functions such as LPM and
DesignWare functions, automatically chooses the appropriate mode for
common functions such as counters, adders, and multipliers. If required,
the designer can also create special-purpose functions that use a specific
LE operating mode for optimal performance.
The architecture provides a synchronous clock enable to the register in all
four modes. The Altera software can set DATA1 to enable the register
synchronously, providing easy implementation of fully synchronous
designs.
Altera Corporation
21
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 11 shows the LE operating modes.
Figure 11. FLEX 10KE LE Operating Modes
Normal Mode
Cascade-In
Carry-In
LE-Out to FastTrack
Interconnect
data1
data2
4-Input
LUT
data3
D
PRN
Q
LE-Out to Local
Interconnect
ENA
CLRN
data4
Cascade-Out
Arithmetic Mode
Carry-In
Cascade-In
LE-Out
data1
data2
PRN
D
Q
3-Input
LUT
ENA
CLRN
3-Input
LUT
Cascade-Out
Carry-Out
Up/Down Counter Mode
Cascade-In
Carry-In
data1 (ena)
data2 (u/d)
3-Input
LUT
1
D
PRN
Q
LE-Out
0
data3 (data)
ENA
CLRN
3-Input
LUT
data4 (nload)
Carry-Out
Cascade-Out
Clearable Counter Mode
Carry-In
data1 (ena)
data2 (nclr)
3-Input
LUT
D
1
PRN
Q
LE-Out
0
data3 (data)
ENA
CLRN
3-Input
LUT
data4 (nload)
22
Carry-Out
Cascade-Out
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Normal Mode
The normal mode is suitable for general logic applications and wide
decoding functions that can take advantage of a cascade chain. In normal
mode, four data inputs from the LAB local interconnect and the carry-in
are inputs to a four-input LUT. The Altera Compiler automatically selects
the carry-in or the DATA3 signal as one of the inputs to the LUT. The LUT
output can be combined with the cascade-in signal to form a cascade chain
through the cascade-out signal. Either the register or the LUT can be used
to drive both the local interconnect and the FastTrack Interconnect routing
structure at the same time.
The LUT and the register in the LE can be used independently (register
packing). To support register packing, the LE has two outputs; one drives
the local interconnect, and the other drives the FastTrack Interconnect
routing structure. The DATA4 signal can drive the register directly,
allowing the LUT to compute a function that is independent of the
registered signal; a three-input function can be computed in the LUT, and
a fourth independent signal can be registered. Alternatively, a four-input
function can be generated, and one of the inputs to this function can be
used to drive the register. The register in a packed LE can still use the clock
enable, clear, and preset signals in the LE. In a packed LE, the register can
drive the FastTrack Interconnect routing structure while the LUT drives
the local interconnect, or vice versa.
Arithmetic Mode
The arithmetic mode offers 2 three-input LUTs that are ideal for
implementing adders, accumulators, and comparators. One LUT
computes a three-input function; the other generates a carry output. As
shown in Figure 11 on page 22, the first LUT uses the carry-in signal and
two data inputs from the LAB local interconnect to generate a
combinatorial or registered output. For example, in an adder, this output
is the sum of three signals: a, b, and carry-in. The second LUT uses the
same three signals to generate a carry-out signal, thereby creating a carry
chain. The arithmetic mode also supports simultaneous use of the cascade
chain.
Up/Down Counter Mode
The up/down counter mode offers counter enable, clock enable,
synchronous up/down control, and data loading options. These control
signals are generated by the data inputs from the LAB local interconnect,
the carry-in signal, and output feedback from the programmable register.
Use 2 three-input LUTs: one generates the counter data, and the other
generates the fast carry bit. A 2-to-1 multiplexer provides synchronous
loading. Data can also be loaded asynchronously with the clear and preset
register control signals without using the LUT resources.
Altera Corporation
23
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Clearable Counter Mode
The clearable counter mode is similar to the up/down counter mode, but
supports a synchronous clear instead of the up/down control. The clear
function is substituted for the cascade-in signal in the up/down counter
mode. Use 2 three-input LUTs: one generates the counter data, and the
other generates the fast carry bit. Synchronous loading is provided by a
2-to-1 multiplexer. The output of this multiplexer is AND ed with a
synchronous clear signal.
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-states without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers’ output enable (OE) signals select which signal drives the
bus. However, if multiple OE signals are active, contending signals can be
driven onto the bus. Conversely, if no OE signals are active, the bus will
float. Internal tri-state emulation resolves contending tri-state buffers to a
low value and floating buses to a high value, thereby eliminating these
problems. The Altera software automatically implements tri-state bus
functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable register’s clear and preset functions is
controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The
clear and preset control structure of the LE asynchronously loads signals
into a register. Either LABCTRL1 or LABCTRL2 can control the
asynchronous clear. Alternatively, the register can be set up so that
LABCTRL1 implements an asynchronous load. The data to be loaded is
driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the
register.
During compilation, the Altera Compiler automatically selects the best
control signal implementation. Because the clear and preset functions are
active-low, the Compiler automatically assigns a logic high to an unused
clear or preset.
The clear and preset logic is implemented in one of the following six
modes chosen during design entry:
■
■
■
■
■
■
24
Asynchronous clear
Asynchronous preset
Asynchronous clear and preset
Asynchronous load with clear
Asynchronous load with preset
Asynchronous load without clear or preset
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
In addition to the six clear and preset modes, FLEX 10KE devices provide
a chip-wide reset pin that can reset all registers in the device. Use of this
feature is set during design entry. In any of the clear and preset modes, the
chip-wide reset overrides all other signals. Registers with asynchronous
presets may be preset when the chip-wide reset is asserted. Inversion can
be used to implement the asynchronous preset. Figure 12 shows examples
of how to setup the preset and clear inputs for the desired functionality.
Figure 12. FLEX 10KE LE Clear & Preset Modes
Asynchronous Clear
Asynchronous Preset
Asynchronous Preset & Clear
labctrl1
VCC
PRN
D
Q
Chip-Wide Reset
labctrl1 or
labctrl2
D
D
labctrl1 or
labctrl2
Chip-Wide Reset
PRN
Q
PRN
Q
CLRN
CLRN
labctrl2
Chip-Wide Reset
CLRN
VCC
Asynchronous Load without Clear or Preset
Asynchronous Load with Clear
NOT
NOT
labctrl1
(Asynchronous
Load)
labctrl1
(Asynchronous
Load)
data3
(Data)
D
NOT
PRN
Q
data3
(Data)
D
CLRN
CLRN
labctrl2
(Clear)
Chip-Wide Reset
PRN
Q
NOT
Chip-Wide Reset
Asynchronous Load with Preset
NOT
labctrl1
(Asynchronous
Load)
labctrl2
(Preset)
D
PRN
Q
data3
(Data)
CLRN
NOT
Chip-Wide Reset
Altera Corporation
25
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Asynchronous Clear
The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this
mode, the preset signal is tied to VCC to deactivate it.
Asynchronous Preset
An asynchronous preset is implemented as an asynchronous load, or with
an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRL1
asynchronously loads a one into the register. Alternatively, the Altera
software can provide preset control by using the clear and inverting the
input and output of the register. Inversion control is available for the
inputs to both LEs and IOEs. Therefore, if a register is preset by only one
of the two LABCTRL signals, the DATA3 input is not needed and can be
used for one of the LE operating modes.
Asynchronous Preset & Clear
When implementing asynchronous clear and preset, LABCTRL1 controls
the preset and LABCTRL2 controls the clear. DATA3 is tied to VCC, so that
asserting LABCTRL1 asynchronously loads a one into the register,
effectively presetting the register. Asserting LABCTRL2 clears the register.
Asynchronous Load with Clear
When implementing an asynchronous load in conjunction with the clear,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
the register preset and clear. LABCTRL2 implements the clear by
controlling the register clear; LABCTRL2 does not have to feed the preset
circuits.
Asynchronous Load with Preset
When implementing an asynchronous load in conjunction with preset, the
Altera software provides preset control by using the clear and inverting
the input and output of the register. Asserting LABCTRL2 presets the
register, while asserting LABCTRL1 loads the register. The Altera software
inverts the signal that drives DATA3 to account for the inversion of the
register’s output.
Asynchronous Load without Preset or Clear
When implementing an asynchronous load without preset or clear,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
the register preset and clear.
26
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
FastTrack Interconnect Routing Structure
In the FLEX 10KE architecture, connections between LEs, EABs, and
device I/O pins are provided by the FastTrack Interconnect routing
structure, which is a series of continuous horizontal and vertical routing
channels that traverses the device. This global routing structure provides
predictable performance, even in complex designs. In contrast, the
segmented routing in FPGAs requires switch matrices to connect a
variable number of routing paths, increasing the delays between logic
resources and reducing performance.
The FastTrack Interconnect routing structure consists of row and column
interconnect channels that span the entire device. Each row of LABs is
served by a dedicated row interconnect. The row interconnect can drive
I/O pins and feed other LABs in the row. The column interconnect routes
signals between rows and can drive I/O pins.
Row channels drive into the LAB or EAB local interconnect. The row
signal is buffered at every LAB or EAB to reduce the effect of fan-out on
delay. A row channel can be driven by an LE or by one of three column
channels. These four signals feed dual 4-to-1 multiplexers that connect to
two specific row channels. These multiplexers, which are connected to
each LE, allow column channels to drive row channels even when all eight
LEs in a LAB drive the row interconnect.
Each column of LABs or EABs is served by a dedicated column
interconnect. The column interconnect that serves the EABs has twice as
many channels as other column interconnects. The column interconnect
can then drive I/O pins or another row’s interconnect to route the signals
to other LABs or EABs in the device. A signal from the column
interconnect, which can be either the output of a LE or an input from an
I/O pin, must be routed to the row interconnect before it can enter a LAB
or EAB. Each row channel that is driven by an IOE or EAB can drive one
specific column channel.
Access to row and column channels can be switched between LEs in
adjacent pairs of LABs. For example, a LE in one LAB can drive the row
and column channels normally driven by a particular LE in the adjacent
LAB in the same row, and vice versa. This flexibility enables routing
resources to be used more efficiently (see Figure 13).
Altera Corporation
27
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 13. FLEX 10KE LAB Connections to Row & Column Interconnect
Column
Channels
To Other
Columns
Row Channels
At each intersection,
six row channels can
drive column channels.
Each LE can drive two
row channels.
From Adjacent LAB
To Adjacent LAB
LE 1
Each LE can switch
interconnect access
with an LE in the
adjacent LAB.
LE 2
LE 8
To LAB Local
Interconnect
28
To Other Rows
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
For improved routing, the row interconnect consists of a combination of
full-length and half-length channels. The full-length channels connect to
all LABs in a row; the half-length channels connect to the LABs in half of
the row. The EAB can be driven by the half-length channels in the left half
of the row and by the full-length channels. The EAB drives out to the fulllength channels. In addition to providing a predictable, row-wide
interconnect, this architecture provides increased routing resources. Two
neighboring LABs can be connected using a half-row channel, thereby
saving the other half of the channel for the other half of the row.
Table 7 summarizes the FastTrack Interconnect routing structure
resources available in each FLEX 10KE device.
Table 7. FLEX 10KE FastTrack Interconnect Resources
Device
Rows
Channels per
Row
Columns
Channels per
Column
EPF10K30E
6
216
36
24
EPF10K50E
EPF10K50S
10
216
36
24
EPF10K100E
12
312
52
24
EPF10K130E
16
312
52
32
EPF10K200E
EPF10K200S
24
312
52
48
In addition to general-purpose I/O pins, FLEX 10KE devices have six
dedicated input pins that provide low-skew signal distribution across the
device. These six inputs can be used for global clock, clear, preset, and
peripheral output enable and clock enable control signals. These signals
are available as control signals for all LABs and IOEs in the device. The
dedicated inputs can also be used as general-purpose data inputs because
they can feed the local interconnect of each LAB in the device.
Figure 14 shows the interconnection of adjacent LABs and EABs, with
row, column, and local interconnects, as well as the associated cascade
and carry chains. Each LAB is labeled according to its location: a letter
represents the row and a number represents the column. For example,
LAB B3 is in row B, column 3.
Altera Corporation
29
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 14. FLEX 10KE Interconnect Resources
See Figure 17
for details.
I/O Element (IOE)
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
Row
Interconnect
LAB
A1
LAB
A2
See Figure 16
for details.
LAB
A3
Column
Interconnect
LAB A5
LAB A4
IOE
IOE
IOE
IOE
LAB
B1
LAB
B2
Cascade &
Carry Chains
LAB
B3
LAB B5
LAB B4
IOE
IOE
IOE
IOE
IOE
IOE
I/O Element
An IOE contains a bidirectional I/O buffer and a register that can be used
either as an input register for external data that requires a fast setup time,
or as an output register for data that requires fast clock-to-output
performance. In some cases, using an LE register for an input register will
result in a faster setup time than using an IOE register. IOEs can be used
as input, output, or bidirectional pins. For bidirectional registered I/O
implementation, the output register should be in the IOE, and the data
input and output enable registers should be LE registers placed adjacent
to the bidirectional pin. The Altera Compiler uses the programmable
inversion option to invert signals from the row and column interconnect
automatically where appropriate. Figure 15 shows the bidirectional I/O
registers.
30
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 15. FLEX 10KE Bidirectional I/O Registers
Row and Column
Interconnect
2 Dedicated
Clock Inputs
4 Dedicated
Inputs
Peripheral
Control Bus
2
4
OE Register
12
D
Q
ENA
CLRN
VCC
Chip-Wide
Reset
VCC
Chip-Wide
Output Enable
OE[7..0]
(1)
Programmable Delay
VCC
Output Register (2)
D
Q
CLK[1..0]
ENA
CLRN
CLK[3..2]
VCC
Open-Drain
Output
Slew-Rate
Control
ENA[5..0]
VCC
CLRN[1..0]
Chip-Wide
Reset Input Register (2)
D
Q
VCC
ENA
CLRN
Chip-Wide
Reset
Note:
(1)
All FLEX 10KE devices (except the EPF10K50E and EPF10K200E devices) have a programmable input delay buffer
on the input path.
Altera Corporation
31
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
On all FLEX 10KE devices (except EPF10K50E and EPF10K200E devices),
the input path from the I/O pad to the FastTrack Interconnect has a
programmable delay element that can be used to guarantee a zero hold
time. EPF10K50S and EPF10K200S devices also support this feature.
Depending on the placement of the IOE relative to what it is driving, the
designer may choose to turn on the programmable delay to ensure a zero
hold time or turn it off to minimize setup time. This feature is used to
reduce setup time for complex pin-to-register paths (e.g., PCI designs).
Each IOE selects the clock, clear, clock enable, and output enable controls
from a network of I/O control signals called the peripheral control bus.
The peripheral control bus uses high-speed drivers to minimize signal
skew across the device and provides up to 12 peripheral control signals
that can be allocated as follows:
■
■
■
■
Up to eight output enable signals
Up to six clock enable signals
Up to two clock signals
Up to two clear signals
If more than six clock enable or eight output enable signals are required,
each IOE on the device can be controlled by clock enable and output
enable signals driven by specific LEs. In addition to the two clock signals
available on the peripheral control bus, each IOE can use one of two
dedicated clock pins. Each peripheral control signal can be driven by any
of the dedicated input pins or the first LE of each LAB in a particular row.
In addition, a LE in a different row can drive a column interconnect, which
causes a row interconnect to drive the peripheral control signal. The chipwide reset signal resets all IOE registers, overriding any other control
signals.
When a dedicated clock pin drives IOE registers, it can be inverted for all
IOEs in the device. All IOEs must use the same sense of the clock. For
example, if any IOE uses the inverted clock, all IOEs must use the inverted
clock and no IOE can use the non-inverted clock. However, LEs can still
use the true or complement of the clock on a LAB-by-LAB basis.
The incoming signal may be inverted at the dedicated clock pin and will
drive all IOEs. For the true and complement of a clock to be used to drive
IOEs, drive it into both global clock pins. One global clock pin will supply
the true, and the other will supply the complement.
When the true and complement of a dedicated input drives IOE clocks,
two signals on the peripheral control bus are consumed, one for each
sense of the clock.
32
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
When dedicated inputs drive non-inverted and inverted peripheral clears,
clock enables, and output enables, two signals on the peripheral control
bus will be used.
Tables 8 and 9 list the sources for each peripheral control signal, and show
how the output enable, clock enable, clock, and clear signals share
12 peripheral control signals. The tables also show the rows that can drive
global signals.
Table 8. Peripheral Bus Sources for EPF10K30E, EPF10K50E & EPF10K50S Devices
Peripheral
Control Signal
EPF10K30E
EPF10K50E
EPF10K50S
OE0
Row A
Row A
OE1
Row B
Row B
OE2
Row C
Row D
OE3
Row D
Row F
OE4
Row E
Row H
OE5
Row F
Row J
CLKENA0/CLK0/GLOBAL0
Row A
Row A
CLKENA1/OE6/GLOBAL1
Row B
Row C
CLKENA2/CLR0
Row C
Row E
CLKENA3/OE7/GLOBAL2
Row D
Row G
CLKENA4/CLR1
Row E
Row I
CLKENA5/CLK1/GLOBAL3
Row F
Row J
Altera Corporation
33
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 9. Peripheral Bus Sources for EPF10K100E, EPF10K130E, EPF10K200E & EPF10K200S Devices
Peripheral
Control Signal
EPF10K100E
EPF10K130E
EPF10K200E
EPF10K200S
OE0
Row A
Row C
Row G
OE1
Row C
Row E
Row I
OE2
Row E
Row G
Row K
OE3
Row L
Row N
Row R
OE4
Row I
Row K
Row O
OE5
Row K
Row M
Row Q
CLKENA0/CLK0/GLOBAL0
Row F
Row H
Row L
CLKENA1/OE6/GLOBAL1
Row D
Row F
Row J
CLKENA2/CLR0
Row B
Row D
Row H
CLKENA3/OE7/GLOBAL2
Row H
Row J
Row N
CLKENA4/CLR1
Row J
Row L
Row P
CLKENA5/CLK1/GLOBAL3
Row G
Row I
Row M
Signals on the peripheral control bus can also drive the four global signals,
referred to as GLOBAL0 through GLOBAL3 in Tables 8 and 9. An internally
generated signal can drive a global signal, providing the same low-skew,
low-delay characteristics as a signal driven by an input pin. An LE drives
the global signal by driving a row line that drives the peripheral bus,
which then drives the global signal. This feature is ideal for internally
generated clear or clock signals with high fan-out. However, internally
driven global signals offer no advantage over the general-purpose
interconnect for routing data signals. The dedicated input pin should be
driven to a known logic state (such as ground) and not be allowed to float.
The chip-wide output enable pin is an active-high pin (DEV_OE) that can
be used to tri-state all pins on the device. This option can be set in the
Altera software. On EPF10K50E and EPF10K200E devices, the built-in I/O
pin pull-up resistors (which are active during configuration) are active
when the chip-wide output enable pin is asserted. The registers in the IOE
can also be reset by the chip-wide reset pin.
34
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Row-to-IOE Connections
When an IOE is used as an input signal, it can drive two separate row
channels. The signal is accessible by all LEs within that row. When an IOE
is used as an output, the signal is driven by a multiplexer that selects a
signal from the row channels. Up to eight IOEs connect to each side of
each row channel (see Figure 16).
Figure 16. FLEX 10KE Row-to-IOE Connections
The values for m and n are provided in Table 10.
IOE1
m
Row FastTrack
Interconnect
n
n
n
IOE8
m
Each IOE is driven by an
m-to-1 multiplexer.
Each IOE can drive two
row channels.
Table 10 lists the FLEX 10KE row-to-IOE interconnect resources.
Table 10. FLEX 10KE Row-to-IOE Interconnect Resources
Device
Altera Corporation
Channels per Row (n)
Row Channels per Pin (m)
EPF10K30E
216
27
EPF10K50E
EPF10K50S
216
27
EPF10K100E
312
39
EPF10K130E
312
39
EPF10K200E
EPF10K200S
312
39
35
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Column-to-IOE Connections
When an IOE is used as an input, it can drive up to two separate column
channels. When an IOE is used as an output, the signal is driven by a
multiplexer that selects a signal from the column channels. Two IOEs
connect to each side of the column channels. Each IOE can be driven by
column channels via a multiplexer. The set of column channels is different
for each IOE (see Figure 17).
Figure 17. FLEX 10KE Column-to-IOE Connections
The values for m and n are provided in Table 11.
Each IOE is driven by
a m-to-1 multiplexer
Column
Interconnect
m
IOE1
m
IOE1
n
n
n
Each IOE can drive two
column channels.
Table 11 lists the FLEX 10KE column-to-IOE interconnect resources.
Table 11. FLEX 10KE Column-to-IOE Interconnect Resources
Device
36
Channels per Column (n)
Column Channels per Pin (m)
EPF10K30E
24
16
EPF10K50E
EPF10K50S
24
16
EPF10K100E
24
16
EPF10K130E
32
24
EPF10K200E
EPF10K200S
48
40
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
SameFrame
Pin-Outs
FLEX 10KE devices support the SameFrame pin-out feature for
FineLine BGA packages. The SameFrame pin-out feature is the
arrangement of balls on FineLine BGA packages such that the lower-ballcount packages form a subset of the higher-ball-count packages.
SameFrame pin-outs provide the flexibility to migrate not only from
device to device within the same package, but also from one package to
another. A given printed circuit board (PCB) layout can support multiple
device density/package combinations. For example, a single board layout
can support a range of devices from an EPF10K30E device in a 256-pin
FineLine BGA package to an EPF10K200S device in a 672-pin
FineLine BGA package.
The Altera software provides support to design PCBs with SameFrame
pin-out devices. Devices can be defined for present and future use. The
Altera software generates pin-outs describing how to lay out a board to
take advantage of this migration (see Figure 18).
Figure 18. SameFrame Pin-Out Example
Printed Circuit Board
Designed for 672-Pin FineLine BGA Package
100-Pin
FineLine
BGA
256-Pin FineLine BGA Package
(Reduced I/O Count or
Logic Requirements)
Altera Corporation
256-Pin
FineLine
BGA
672-Pin FineLine BGA Package
(Increased I/O Count or
Logic Requirements)
37
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
ClockLock &
ClockBoost
Features
To support high-speed designs, FLEX 10KE devices offer optional
ClockLock and ClockBoost circuitry containing a phase-locked loop (PLL)
used to increase design speed and reduce resource usage. The ClockLock
circuitry uses a synchronizing PLL that reduces the clock delay and skew
within a device. This reduction minimizes clock-to-output and setup
times while maintaining zero hold times. The ClockBoost circuitry, which
provides a clock multiplier, allows the designer to enhance device area
efficiency by resource sharing within the device. The ClockBoost feature
allows the designer to distribute a low-speed clock and multiply that clock
on-device. Combined, the ClockLock and ClockBoost features provide
significant improvements in system performance and bandwidth.
All FLEX 10KE devices, except EPF10K50E and EPF10K200E devices,
support ClockLock and ClockBoost circuitry. EPF10K50S and
EPF10K200S devices support this circuitry. Devices that support ClockLock and ClockBoost circuitry are distinguished with an “X” suffix in the
ordering code; for instance, the EPF10K200SFC672-1X device supports
this circuit.
The ClockLock and ClockBoost features in FLEX 10KE devices are
enabled through the Altera software. External devices are not required to
use these features. The output of the ClockLock and ClockBoost circuits is
not available at any of the device pins.
The ClockLock and ClockBoost circuitry locks onto the rising edge of the
incoming clock. The circuit output can drive the clock inputs of registers
only; the generated clock cannot be gated or inverted.
The dedicated clock pin (GCLK1) supplies the clock to the ClockLock and
ClockBoost circuitry. When the dedicated clock pin is driving the
ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the device.
For designs that require both a multiplied and non-multiplied clock, the
clock trace on the board can be connected to the GCLK1 pin. In the
Altera software, the GCLK1 pin can feed both the ClockLock and
ClockBoost circuitry in the FLEX 10KE device. However, when both
circuits are used, the other clock pin cannot be used.
38
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
ClockLock & ClockBoost Timing Parameters
For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the ClockLock and ClockBoost circuitry will lock onto the
clock during configuration. The circuit will be ready for use immediately
after configuration. Figure 19 shows the incoming and generated clock
specifications.
Figure 19. Specifications for Incoming & Generated Clocks
The tI parameter refers to the nominal input clock period; the tO parameter refers to the
nominal output clock period.
tCLK1
tINDUTY
tI ± fCLKDEV
Input
Clock
tR
tF
tI
tI ± tINCLKSTB
tO
tO + tJITTER
tOUTDUTY
ClockLockGenerated
Clock
Altera Corporation
tO – tJITTER
39
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Tables 12 and 13 summarize the ClockLock and ClockBoost parameters
for -1 and -2 speed-grade devices, respectively.
Table 12. ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices
Max
Unit
tR
Symbol
Input rise time
5
ns
tF
Input fall time
5
ns
t INDUTY
Input duty cycle
40
60
%
f CLK1
Input clock frequency (ClockBoost
clock multiplication factor equals 1)
25
180
MHz
fCLK2
Input clock frequency (ClockBoost
clock multiplication factor equals 2)
16
90
MHz
f CLKDEV
Input deviation from user
specification in the MAX+PLUS II
software (1)
25,000 (2)
PPM
t INCLKSTB
Input clock stability (measured
between adjacent clocks)
100
ps
t LOCK
Time required for ClockLock or
ClockBoost to acquire lock (3)
10
µs
t JITTER
Jitter on ClockLock or ClockBoostgenerated clock (4)
t INCLKSTB < 100
250
ps
t INCLKSTB < 50
200 (4)
ps
60
%
tOUTDUTY
40
Parameter
Duty cycle for ClockLock or
ClockBoost-generated clock
Condition
Min
40
Typ
50
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 13. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tR
Input rise time
5
ns
tF
Input fall time
5
ns
t INDUTY
Input duty cycle
40
60
%
f CLK1
Input clock frequency (ClockBoost
clock multiplication factor equals 1)
25
75
MHz
fCLK2
Input clock frequency (ClockBoost
clock multiplication factor equals 2)
16
37.5
MHz
f CLKDEV
Input deviation from user
specification in the MAX+PLUS II
software (1)
25,000 (2)
PPM
t INCLKSTB
Input clock stability (measured
between adjacent clocks)
100
ps
t LOCK
Time required for ClockLock or
ClockBoost to acquire lock (3)
10
µs
t JITTER
Jitter on ClockLock or ClockBoostgenerated clock (4)
t INCLKSTB < 100
250
ps
t INCLKSTB < 50
200 (4)
ps
60
%
tOUTDUTY
Duty cycle for ClockLock or
ClockBoost-generated clock
40
50
Notes to tables:
(1)
(2)
(3)
(4)
To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the
input frequency. The Altera software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency.
The fCLKDEV parameter specifies how much the incoming clock can differ from the specified frequency during
device operation. Simulation does not reflect this parameter.
Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.
During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration because the tLOCK value is less than the time required for configuration.
The tJITTER specification is measured under long-term observation. The maximum value for tJITTER is 200 ps if
tINCLKSTB is lower than 50 ps.
I/O
Configuration
Altera Corporation
This section discusses the peripheral component interconnect (PCI)
pull-up clamping diode option, slew-rate control, open-drain output
option, and MultiVolt I/O interface for FLEX 10KE devices. The PCI
pull-up clamping diode, slew-rate control, and open-drain output options
are controlled pin-by-pin via Altera software logic options. The MultiVolt
I/O interface is controlled by connecting VCCIO to a different voltage than
VCCINT. Its effect can be simulated in the Altera software via the Global
Project Device Options dialog box (Assign menu).
41
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
PCI Pull-Up Clamping Diode Option
FLEX 10KE devices have a pull-up clamping diode on every I/O,
dedicated input, and dedicated clock pin. PCI clamping diodes clamp the
signal to the VCCIO value and are required for 3.3-V PCI compliance.
Clamping diodes can also be used to limit overshoot in other systems.
Clamping diodes are controlled on a pin-by-pin basis. When VCCIO is
3.3 V, a pin that has the clamping diode option turned on can be driven by
a 2.5-V or 3.3-V signal, but not a 5.0-V signal. When VCCIO is 2.5 V, a pin
that has the clamping diode option turned on can be driven by a 2.5-V
signal, but not a 3.3-V or 5.0-V signal. Additionally, a clamping diode can
be activated for a subset of pins, which would allow a device to bridge
between a 3.3-V PCI bus and a 5.0-V device.
Slew-Rate Control
The output buffer in each IOE has an adjustable output slew rate that can
be configured for low-noise or high-speed performance. A slower slew
rate reduces system noise and adds a maximum delay of 4.3 ns. The fast
slew rate should be used for speed-critical outputs in systems that are
adequately protected against noise. Designers can specify the slew rate
pin-by-pin or assign a default slew rate to all pins on a device-wide basis.
The slow slew rate setting affects the falling edge of the output.
Open-Drain Output Option
FLEX 10KE devices provide an optional open-drain output (electrically
equivalent to open-collector output) for each I/O pin. This open-drain
output enables the device to provide system-level control signals (e.g.,
interrupt and write enable signals) that can be asserted by any of several
devices. It can also provide an additional wired-OR plane.
MultiVolt I/O Interface
The FLEX 10KE device architecture supports the MultiVolt I/O interface
feature, which allows FLEX 10KE devices in all packages to interface with
systems of differing supply voltages. These devices have one set of VCC
pins for internal operation and input buffers (VCCINT), and another set for
I/O output drivers (VCCIO).
42
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
The VCCINT pins must always be connected to a 2.5-V power supply.
With a 2.5-V VCCINT level, input voltages are compatible with 2.5-V, 3.3V, and 5.0-V inputs. The VCCIO pins can be connected to either a 2.5-V or
3.3-V power supply, depending on the output requirements. When the
VCCIO pins are connected to a 2.5-V power supply, the output levels are
compatible with 2.5-V systems. When the VCCIO pins are connected to a
3.3-V power supply, the output high is at 3.3 V and is therefore compatible
with 3.3-V or 5.0-V systems. Devices operating with VCCIO levels higher
than 3.0 V achieve a faster timing delay of tOD2 instead of tOD1.
Table 14 summarizes FLEX 10KE MultiVolt I/O support.
Table 14. FLEX 10KE MultiVolt I/O Support
VCCIO (V)
Input Signal (V)
2.5
3.3
Output Signal (V)
5.0
2.5
2.5
v
v(1)
v(1)
v
3.3
v
v
v(1)
v(2)
3.3
5.0
v
v
Notes:
(1)
(2)
The PCI clamping diode must be disabled to drive an input with voltages higher
than VCCIO.
When VCCIO = 3.3 V, a FLEX 10KE device can drive a 2.5-V device that has 3.3-V
tolerant inputs.
Open-drain output pins on FLEX 10KE devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a VIH of
3.5 V. When the open-drain pin is active, it will drive low. When the pin is
inactive, the trace will be pulled up to 5.0 V by the resistor. The open-drain
pin will only drive low or tri-state; it will never drive high. The rise time
is dependent on the value of the pull-up resistor and load impedance. The
IOL current specification should be considered when selecting a pull-up
resistor.
Power Sequencing & Hot-Socketing
Because FLEX 10KE devices can be used in a mixed-voltage environment,
they have been designed specifically to tolerate any possible power-up
sequence. The VCCIO and VCCINT power planes can be powered in any
order.
Signals can be driven into FLEX 10KE devices before and during power
up without damaging the device. Additionally, FLEX 10KE devices do not
drive out during power up. Once operating conditions are reached,
FLEX 10KE devices operate as specified by the user.
Altera Corporation
43
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
All FLEX 10KE devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-1990 specification. FLEX 10KE devices can also be
configured using the JTAG pins through the BitBlaster or ByteBlasterMV
download cable, or via hardware that uses the JamTM STAPL
programming and test language. JTAG boundary-scan testing can be
performed before or after configuration, but not during configuration.
FLEX 10KE devices support the JTAG instructions shown in Table 15.
Table 15. FLEX 10KE JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern to be output at the device
pins.
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.
BYPASS
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during normal
device operation.
USERCODE
Selects the user electronic signature (USERCODE) register and places it between the
TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO.
IDCODE
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE
to be serially shifted out of TDO.
ICR Instructions
These instructions are used when configuring a FLEX 10KE device via JTAG ports with
a BitBlaster or ByteBlasterMV download cable, or using a Jam File (.jam) or
Jam Byte-Code File (.jbc) via an embedded processor.
The instruction register length of FLEX 10KE devices is 10 bits. The
USERCODE register length in FLEX 10KE devices is 32 bits; 7 bits are
determined by the user, and 25 bits are pre-determined. Tables 16 and 17
show the boundary-scan register length and device IDCODE information
for FLEX 10KE devices.
Table 16. FLEX 10KE Boundary-Scan Register Length
Device
EPF10K30E
690
EPF10K50E
EPF10K50S
798
EPF10K100E
44
Boundary-Scan Register Length
1,050
EPF10K130E
1,308
EPF10K200E
EPF10K200S
1,446
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 17. 32-Bit IDCODE for FLEX 10KE Devices
Device
Note (1)
IDCODE (32 Bits)
Version
(4 Bits)
Part Number (16 Bits)
Manufacturer’s 1 (1 Bit)
Identity (11 Bits)
(2)
EPF10K30E
0001
0001 0000 0011 0000
00001101110
1
EPF10K50E
EPF10K50S
0001
0001 0000 0101 0000
00001101110
1
EPF10K100E
0010
0000 0001 0000 0000
00001101110
1
EPF10K130E
0001
0000 0001 0011 0000
00001101110
1
EPF10K200E
EPF10K200S
0001
0000 0010 0000 0000
00001101110
1
Notes:
(1)
(2)
The most significant bit (MSB) is on the left.
The least significant bit (LSB) for all JTAG IDCODEs is 1.
FLEX 10KE devices include weak pull-up resistors on the JTAG pins.
f
For more information, see the following documents:
■
■
■
■
Altera Corporation
Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in
Altera Devices)
BitBlaster Serial Download Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
Jam Programming & Test Language Specification
45
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 20 shows the timing requirements for the JTAG signals.
Figure 20. FLEX 10KE JTAG Waveforms
TMS
TDI
t JCP
t JCH
t JCL
t JPSU
t JPH
TCK
tJPZX
t JPXZ
t JPCO
TDO
tJSH
tJSSU
Signal
to Be
Captured
Signal
to Be
Driven
tJSCO
tJSZX
tJSXZ
Table 18 shows the timing parameters and values for FLEX 10KE devices.
Table 18. FLEX 10KE JTAG Timing Parameters & Values
Symbol
46
Parameter
Min
Max
Unit
tJCP
TCK clock period
100
ns
tJCH
TCK clock high time
50
ns
tJCL
TCK clock low time
50
ns
tJPSU
JTAG port setup time
20
ns
tJPH
JTAG port hold time
45
ns
tJPCO
JTAG port clock to output
25
ns
tJPZX
JTAG port high impedance to valid output
25
ns
tJPXZ
JTAG port valid output to high impedance
25
tJSSU
Capture register setup time
20
tJSH
Capture register hold time
45
tJSCO
Update register clock to output
35
ns
tJSZX
Update register high impedance to valid output
35
ns
tJSXZ
Update register valid output to high impedance
35
ns
ns
ns
ns
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Generic Testing
Each FLEX 10KE device is functionally tested. Complete testing of each
configurable static random access memory (SRAM) bit and all logic
functionality ensures 100% yield. AC test measurements for FLEX 10KE
devices are made under conditions equivalent to those shown in
Figure 21. Multiple test patterns can be used to configure devices during
all stages of the production flow.
Figure 21. FLEX 10KE AC Test Conditions
Power supply transients can affect AC
measurements. Simultaneous transitions of
multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast-groundcurrent transients normally occur as the
device outputs discharge the load
capacitances. When these transients flow
through the parasitic inductance between
the device ground pin and the test system
ground, significant reductions in
observable noise immunity can result.
Numbers in brackets are for 2.5-V devices
or outputs. Numbers without brackets are
for 3.3-V. devices or outputs.
Operating
Conditions
Symbol
703 Ω
[481 Ω ]
Test
System
Device
Output
8.06 kΩ
[481 Ω ]
C1 (includes
JIG capacitance)
Device input
rise and fall
times < 3 ns
Tables 19 through 23 provide information on absolute maximum ratings,
recommended operating conditions, DC operating conditions, and
capacitance for 2.5-V FLEX 10KE devices.
Table 19. FLEX 10KE 2.5-V Device Absolute Maximum Ratings
V CCINT
VCCIO
Parameter
Supply voltage
Note (1)
Conditions
With respect to ground (2)
V CCIO
Max
Unit
3.6
V
–0.5
4.6
V
–2.0
5.75
V
–25
25
mA
–65
150
°C
–65
135
°C
PQFP, TQFP, BGA, and FineLine BGA
packages, under bias
135
°C
Ceramic PGA packages, under bias
150
°C
VI
DC input voltage
I OUT
DC output current, per pin
T STG
Storage temperature
No bias
T AMB
Ambient temperature
Under bias
TJ
Junction temperature
Altera Corporation
Min
–0.5
47
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 20. 2.5-V EPF10K50E & EPF10K200E Device Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Unit
V CCINT
Supply voltage for internal logic
and input buffers
(3), (4)
2.30 (2.30)
2.70 (2.70)
V
V CCIO
Supply voltage for output buffers, (3), (4)
3.3-V operation
3.00 (3.00)
3.60 (3.60)
V
Supply voltage for output buffers, (3), (4)
2.5-V operation
2.30 (2.30)
2.70 (2.70)
V
VI
Input voltage
VO
Output voltage
TA
Ambient temperature
(5)
For commercial use
For industrial use
–0.5
5.75
V
0
V CCIO
V
°C
0
70
–40
85
°C
0
85
°C
–40
TJ
Operating temperature
100
°C
tR
Input rise time
40
ns
tF
Input fall time
40
ns
For commercial use
For industrial use
Table 21. 2.5-V EPF10K30E, EPF10K50S, EPF10K100E, EPF10K130E & EPF10K200S Device
Recommended Operating Conditions
Symbol
Parameter
Min
Max
Unit
2.375
(2.375)
2.625
(2.625)
V
Supply voltage for output buffers, (3), (4)
3.3-V operation
3.00 (3.00)
3.60 (3.60)
V
Supply voltage for output buffers, (3), (4)
2.5-V operation
2.375
(2.375)
2.625
(2.625)
V
V CCINT
Supply voltage for internal logic
and input buffers
V CCIO
Conditions
(3), (4)
VI
Input voltage
VO
Output voltage
(5)
TA
Ambient temperature
For commercial use
TJ
Operating temperature
For commercial use
tR
Input rise time
tF
Input fall time
For industrial use
For industrial use
48
–0.5
5.75
V
0
V CCIO
V
0
70
°C
–40
85
°C
0
85
°C
–40
100
°C
40
ns
40
ns
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 22. FLEX 10KE 2.5-V Device DC Operating Conditions
Symbol
Parameter
Conditions
Notes (6), (7)
Min
Typ
Max
Unit
V IH
High-level input
voltage
1.7, 0.5 × VCCIO (8)
5.75
V
V IL
Low-level input
voltage
–0.5
0.8,
0.3 × VCCIO (8)
V
V OH
3.3-V high-level TTL
output voltage
2.4
V
V CCIO – 0.2
V
0.9 × VCCIO
V
2.5-V high-level output I OH = –0.1 mA DC,
V CCIO = 2.30 V (9)
voltage
2.1
V
I OH = –1 mA DC,
V CCIO = 2.30 V (9)
2.0
V
I OH = –2 mA DC,
V CCIO = 2.30 V (9)
1.7
V
I OH = –8 mA DC,
V CCIO = 3.00 V (9)
3.3-V high-level
I OH = –0.1 mA DC,
CMOS output voltage V CCIO = 3.00 V (9)
3.3-V high-level PCI
output voltage
V OL
I OH = –0.5 mA DC,
V CCIO = 3.00 to 3.60 V (9)
I OL = 12 mA DC,
V CCIO = 3.00 V (10)
0.45
V
3.3-V low-level CMOS I OL = 0.1 mA DC,
V CCIO = 3.00 V (10)
output voltage
0.2
V
0.1 × VCCIO
V
2.5-V low-level output I OL = 0.1 mA DC,
V CCIO = 2.30 V (10)
voltage
0.2
V
I OL = 1 mA DC,
V CCIO = 2.30 V (10)
0.4
V
I OL = 2 mA DC,
V CCIO = 2.30 V (10)
0.7
V
3.3-V low-level TTL
output voltage
3.3-V low-level PCI
output voltage
I OL = 1.5 mA DC,
V CCIO = 3.00 to 3.60 V
(10)
II
Input pin leakage
current
V I = V CCIOmax to 0 V (11)
–10
10
µA
I OZ
Tri-stated I/O pin
leakage current
VO = VCCIOmax to 0 V (11)
–10
10
µA
I CC0
V CC supply current
(standby)
V I = ground, no load, no
toggling inputs
5
mA
V I = ground, no load, no
toggling inputs (12)
10
mA
R CONF
Value of I/O pin pull- V CCIO = 3.0 V (13)
up resistor before and V CCIO = 2.3 V (13)
during configuration
Altera Corporation
20
50
k¾
30
80
k¾
49
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 23. FLEX 10KE Device Capacitance
Symbol
Parameter
Note (14)
Conditions
Min
Max
Unit
CIN
Input capacitance
VIN = 0 V, f = 1.0 MHz
10
pF
CINCLK
Input capacitance on
dedicated clock pin
VIN = 0 V, f = 1.0 MHz
12
pF
COUT
Output capacitance
VOUT = 0 V, f = 1.0 MHz
10
pF
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
50
See the Operating Requirements for Altera Devices Data Sheet.
Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents
less than 100 mA and periods shorter than 20 ns.
Numbers in parentheses are for industrial-temperature-range devices.
Maximum V CC rise time is 100 ms, and VCC must rise monotonically.
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
Typical values are for T A = 25° C, V CCINT = 2.5 V, and V CCIO = 2.5 V or 3.3 V.
These values are specified under the FLEX 10KE Recommended Operating Conditions shown in Tables 20 and 21.
The FLEX 10KE input buffers are compatible with 2.5-V, 3.3-V (LVTTL and LVCMOS), and 5.0-V TTL and CMOS
signals. Additionally, the input buffers are 3.3-V PCI compliant when VCCIO and VCCINT meet the relationship shown
in Figure 22.
The IOH parameter refers to high-level TTL, PCI, or CMOS output current.
The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
as well as output pins.
This value is specified for normal device operation. The value may vary during power-up.
This parameter applies to -1 speed-grade commercial-temperature devices and -2 speed-grade-industrial
temperature devices.
Pin pull-up resistance values will be lower if the pin is driven higher than V CCIO by an external source.
Capacitance is sample-tested only.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 22 shows the required relationship between VCCIO and VCCINT for
3.3-V PCI compliance.
Figure 22. Relationship between VCCIO & VCCINT for 3.3-V PCI Compliance
2.7
V CCINT
(V)
II
PCI-Compliant Region
2.5
2.3
3.0
3.1
3.3
3.6
VCCIO
IO (V)
Figure 23 shows the typical output drive characteristics of FLEX 10KE
devices with 3.3-V and 2.5-V VCCIO. The output driver is compliant to the
3.3-V PCI Local Bus Specification, Revision 2.2 (when VCCIO pins are
connected to 3.3 V). FLEX 10KE devices with a -1 speed grade also comply
with the drive strength requirements of the PCI Local Bus Specification,
Revision 2.2 (when VCCINT pins are powered with a minimum supply of
2.375 V, and VCCIO pins are connected to 3.3 V). Therefore, these devices
can be used in open 5.0-V PCI systems.
Altera Corporation
51
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 23. Output Drive Characteristics of FLEX 10KE Devices
90
90
IOL
80
80
70
70
60
Typical IO
Output
Current (mA)
Note (1)
VCCINT = 2.5 V
VCCIO = 2.5 V
Room Temperature
50
40
30
IOL
60
Typical IO
Output
Current (mA)
VCCINT = 2.5 V
VCCIO = 3.3 V
Room Temperature
50
40
30
IOH
IOH
20
20
10
10
1
2
VO Output Voltage (V)
3
1
2
3
VO Output Voltage (V)
Note:
(1)
These are transient (AC) currents.
Timing Model
The continuous, high-performance FastTrack Interconnect routing
resources ensure predictable performance and accurate simulation and
timing analysis. This predictable performance contrasts with that of
FPGAs, which use a segmented connection scheme and therefore have
unpredictable performance.
Device performance can be estimated by following the signal path from a
source, through the interconnect, to the destination. For example, the
registered performance between two LEs on the same row can be
calculated by adding the following parameters:
■
■
■
■
LE register clock-to-output delay (tCO)
Interconnect delay (tSAMEROW)
LE look-up table delay (tLUT )
LE register setup time (tSU)
The routing delay depends on the placement of the source and destination
LEs. A more complex registered path may involve multiple combinatorial
LEs between the source and destination LEs.
52
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Timing simulation and delay prediction are available with the Altera
Simulator and Timing Analyzer, or with industry-standard EDA tools.
The Simulator offers both pre-synthesis functional simulation to evaluate
logic design accuracy and post-synthesis timing simulation with 0.1-ns
resolution. The Timing Analyzer provides point-to-point timing delay
information, setup and hold time analysis, and device-wide performance
analysis.
Figure 24 shows the overall timing model, which maps the possible paths
to and from the various elements of the FLEX 10KE device.
Figure 24. FLEX 10KE Device Timing Model
Dedicated
Clock/Input
Interconnect
Logic
Element
I/O Element
Embedded Array
Block
Figures 25 through 28 show the delays that correspond to various paths
and functions within the LE, IOE, EAB, and bidirectional timing models.
Altera Corporation
53
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 25. FLEX 10KE Device LE Timing Model
Cascade-In
Carry-In
Register
Delays
LUT Delay
Data-In
tLUT
tRLUT
t CO
tCOMB
t SU
tH
tPRE
tCLR
tCLUT
Packed Register
Delay
tPACKED
Data-Out
Register Control
Delay
Control-In
tC
tEN
Carry Chain
Delay
tCGENR
tCASC
tCGEN
tCICO
tLABCARRY
Carry-Out
54
tLABCASC
Cascade-Out
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 26. FLEX 10KE Device IOE Timing Model
Output Data
Delay
I/O Register
Delays
tIOD
tIOCO
tIOCOMB
tIOSU
tIOH
tIOCLR
Data-In
I/O Element
Contol Delay
Clock Enable
Clear
Clock
Output Enable
Output
Delays
tOD1
tOD2
tOD3
tXZ
tZX1
tZX2
tZX3
tIOC
tINREG
Input Register Delay
I/O Register
Feedback Delay
Data Feedback
into FastTrack
Interconnect
tIOFD
Input Delay
tINCOMB
Figure 27. FLEX 10KE Device EAB Timing Model
EAB Data Input
Delays
Input Register
Delays
RAM/ROM
Block Delays
Output Register
Delays
tEABDATA1
tEABDATA2
tEABCO
tEABBYPASS
tEABSU
tEABH
tEABCH
tEABCL
tAA
tDD
tWP
tWDSU
tWDH
tWASU
tWAH
tWO
tRP
tRASU
tRAH
tEABCO
tEABBYPASS
tEABSU
tEABH
tEABCH
tEABCL
Data-In
Address
Write Enable
Input Delays
WE
Input Register
Clock
Output Register
Clock
tEABWE1
tEABWE2
EAB Clock
Delay
EAB Output
Delay
tEABOUT
Data-Out
tEABCLK
Read Enable
Input Delays
RE
Altera Corporation
tEABRE1
tEABRE2
55
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 28. Synchronous Bidirectional Pin External Timing Model
OE Register
D
Dedicated
Clock
PRN
Q
tXZBIDIR
tZXBIDIR
CLRN
tOUTCOBIDIR
Output Register
D
PRN
Q
CLRN
Bidirectional
Pin
tINSUBIDIR
tINHBIDIR
Input Register
PRN
D
Q
CLRN
Tables 24 through 28 describe the FLEX 10KE device internal timing
parameters. Tables 29 through 30 describe the FLEX 10KE external timing
parameters and their symbols.
Table 24. LE Timing Microparameters (Part 1 of 2)
Symbol
Note (1)
Parameter
tLUT
LUT delay for data-in
tCLUT
LUT delay for carry-in
tRLUT
LUT delay for LE register feedback
tPACKED
Data-in to packed register delay
tEN
LE register enable delay
tCICO
Carry-in to carry-out delay
tCGEN
Data-in to carry-out delay
tCGENR
LE register feedback to carry-out delay
tCASC
Cascade-in to cascade-out delay
tC
LE register control signal delay
tCO
LE register clock-to-output delay
tCOMB
Combinatorial delay
tSU
LE register setup time for data and enable signals before clock; LE register
recovery time after asynchronous clear, preset, or load
tH
LE register hold time for data and enable signals after clock
tPRE
LE register preset delay
56
Condition
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 24. LE Timing Microparameters (Part 2 of 2)
Symbol
Note (1)
Parameter
tCLR
LE register clear delay
tCH
Minimum clock high time from clock pin
tCL
Minimum clock low time from clock pin
Table 25. IOE Timing Microparameters
Condition
Note (1)
Symbol
Parameter
Conditions
tIOD
IOE data delay
tIOC
IOE register control signal delay
tIOCO
IOE register clock-to-output delay
tIOCOMB
IOE combinatorial delay
tIOSU
IOE register setup time for data and enable signals before clock; IOE register
recovery time after asynchronous clear
tIOH
IOE register hold time for data and enable signals after clock
tIOCLR
IOE register clear time
tOD1
Output buffer and pad delay, slow slew rate = off, VCCIO = 3.3 V
C1 = 35 pF (2)
tOD2
Output buffer and pad delay, slow slew rate = off, VCCIO = 2.5 V
C1 = 35 pF (3)
tOD3
Output buffer and pad delay, slow slew rate = on
C1 = 35 pF (4)
tXZ
IOE output buffer disable delay
tZX1
IOE output buffer enable delay, slow slew rate = off, VCCIO = 3.3 V
tZX2
IOE output buffer enable delay, slow slew rate = off, VCCIO = 2.5 V
C1 = 35 pF (3)
tZX3
IOE output buffer enable delay, slow slew rate = on
C1 = 35 pF (4)
tINREG
IOE input pad and buffer to IOE register delay
tIOFD
IOE register feedback delay
tINCOMB
IOE input pad and buffer to FastTrack Interconnect delay
Altera Corporation
C1 = 35 pF (2)
57
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 26. EAB Timing Microparameters
Note (1)
Symbol
Parameter
Conditions
tEABDATA1
Data or address delay to EAB for combinatorial input
tEABDATA2
Data or address delay to EAB for registered input
tEABWE1
Write enable delay to EAB for combinatorial input
tEABWE2
Write enable delay to EAB for registered input
tEABRE1
Read enable delay to EAB for combinatorial input
tEABRE2
Read enable delay to EAB for registered input
tEABCLK
EAB register clock delay
tEABCO
EAB register clock-to-output delay
tEABBYPASS
Bypass register delay
tEABSU
EAB register setup time before clock
tEABH
EAB register hold time after clock
tEABCLR
EAB register asynchronous clear time to output delay
tAA
Address access delay (including the read enable to output delay)
tWP
Write pulse width
tRP
Read pulse width
tWDSU
Data setup time before falling edge of write pulse
(5)
tWDH
Data hold time after falling edge of write pulse
(5)
tWASU
Address setup time before rising edge of write pulse
(5)
tWAH
Address hold time after falling edge of write pulse
(5)
tRASU
Address setup time with respect to the falling edge of the read enable
tRAH
Address hold time with respect to the falling edge of the read enable
tWO
Write enable to data output valid delay
tDD
Data-in to data-out valid delay
tEABOUT
Data-out delay
tEABCH
Clock high time
tEABCL
Clock low time
58
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 27. EAB Timing Macroparameters
Symbol
Note (1), (6)
Parameter
tEABAA
EAB address access delay
tEABRCCOMB
EAB asynchronous read cycle time
tEABRCREG
EAB synchronous read cycle time
tEABWP
EAB write pulse width
tEABWCCOMB
EAB asynchronous write cycle time
tEABWCREG
EAB synchronous write cycle time
tEABDD
EAB data-in to data-out valid delay
tEABDATACO
EAB clock-to-output delay when using output registers
tEABDATASU
EAB data/address setup time before clock when using input register
tEABDATAH
EAB data/address hold time after clock when using input register
tEABWESU
EAB WE setup time before clock when using input register
tEABWEH
EAB WE hold time after clock when using input register
tEABWDSU
EAB data setup time before falling edge of write pulse when not using input
registers
tEABWDH
EAB data hold time after falling edge of write pulse when not using input
registers
tEABWASU
EAB address setup time before rising edge of write pulse when not using
input registers
tEABWAH
EAB address hold time after falling edge of write pulse when not using input
registers
tEABWO
EAB write enable to data output valid delay
Altera Corporation
Conditions
59
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 28. Interconnect Timing Microparameters
Symbol
Note (1)
Parameter
Conditions
tDIN2IOE
Delay from dedicated input pin to IOE control input
(7)
tDIN2LE
Delay from dedicated input pin to LE or EAB control input
(7)
tDCLK2IOE
Delay from dedicated clock pin to IOE clock
(7)
tDCLK2LE
Delay from dedicated clock pin to LE or EAB clock
(7)
tDIN2DATA
Delay from dedicated input or clock to LE or EAB data
(7)
tSAMELAB
Routing delay for an LE driving another LE in the same LAB
tSAMEROW
Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the (7)
same row
tSAMECOLUMN
Routing delay for an LE driving an IOE in the same column
tDIFFROW
Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different (7)
row
tTWOROWS
Routing delay for a row IOE or EAB driving an LE or EAB in a different row
(7)
tLEPERIPH
Routing delay for an LE driving a control signal of an IOE via the peripheral
control bus
(7)
tLABCARRY
Routing delay for the carry-out signal of an LE driving the carry-in signal of a
different LE in a different LAB
tLABCASC
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
(7)
Table 29. External Timing Parameters
Symbol
Parameter
Conditions
tDRR
Register-to-register delay via four LEs, three row interconnects, and four local (8)
interconnects
tINSU
Setup time with global clock at IOE register
(9)
tINH
Hold time with global clock at IOE register
(9)
tOUTCO
Clock-to-output delay with global clock at IOE register
(9)
tPCISU
Setup time with global clock for registers used in PCI designs
(9),(10)
tPCIH
Hold time with global clock for registers used in PCI designs
(9),(10)
tPCICO
Clock-to-output delay with global clock for registers used in PCI designs
(9),(10)
60
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 30. External Bidirectional Timing Parameters
Symbol
Note (9)
Parameter
Conditions
tINSUBIDIR
Setup time for bi-directional pins with global clock at same-row or samecolumn LE register
tINHBIDIR
Hold time for bidirectional pins with global clock at same-row or same-column
LE register
tINH
Hold time with global clock at IOE register
tOUTCOBIDIR
Clock-to-output delay for bidirectional pins with global clock at IOE register
C1 = 35 pF
tXZBIDIR
Synchronous IOE output buffer disable delay
C1 = 35 pF
tZXBIDIR
Synchronous IOE output buffer enable delay, slow slew rate= off
C1 = 35 pF
Notes to tables:
(1)
Microparameters are timing delays contributed by individual architectural elements. These parameters cannot be
measured explicitly.
(2) Operating conditions: VCCIO = 3.3 V ±10% for commercial or industrial use.
(3) Operating conditions: VCCIO = 2.5 V ±5% for commercial or industrial use in EPF10K30E, EPF10K50S,
EPF10K100E, EPF10K130E, and EPF10K200S devices.
(4) Operating conditions: VCCIO = 3.3 V.
(5) Because the RAM in the EAB is self-timed, this parameter can be ignored when the WE signal is registered.
(6) EAB macroparameters are internal parameters that can simplify predicting the behavior of an EAB at its boundary;
these parameters are calculated by summing selected microparameters.
(7) These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing
analysis are required to determine actual worst-case performance.
(8) Contact Altera Applications for test circuit specifications and test conditions.
(9) This timing parameter is sample-tested only.
(10) This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local
Bus Specification, revision 2.2.
Altera Corporation
61
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figures 29 and 30 show the asynchronous and synchronous timing
waveforms, respectively, or the EAB macroparameters in Tables 26
and 27.
Figure 29. EAB Asynchronous Timing Waveforms
EAB Asynchronous Read
WE
a0
Address
a1
a2
tEABAA
Data-Out
a3
tEABRCCOMB
d0
d1
d3
d2
EAB Asynchronous Write
WE
tEABWP
tEABWDSU
din0
Data-In
tEABWDH
din1
tEABWASU
tEABWAH
tEABWCCOMB
Address
a0
a1
a2
tEABDD
Data-Out
62
din0
din1
dout2
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 30. EAB Synchronous Timing Waveforms
EAB Synchronous Read
WE
Address
a0
a1
tEABDATASU
a2
a3
tEABRCREG
tEABDATAH
CLK
tEABDATACO
Data-Out
d2
d1
EAB Synchronous Write (EAB Output Registers Used)
WE
Data-In
Address
a0
din1
din2
din3
a1
a2
a3
tEABWESU
tEABDATASU
tEABDATAH
a2
tEABWEH
CLK
tEABDATACO
tEABWCREG
dout0
Data-Out
dout1
din1
din2
din3
din2
Tables 31 through 37 show EPF10K30E device internal and external
timing parameters.
Table 31. EPF10K30E Device LE Timing Microparameters (Part 1 of 2)
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tLUT
0.7
0.8
1.1
ns
tCLUT
0.5
0.6
0.8
ns
tRLUT
0.6
0.7
1.0
ns
tPACKED
0.3
0.4
0.5
ns
tEN
0.6
0.8
1.0
ns
tCICO
0.1
0.1
0.2
ns
tCGEN
0.4
0.5
0.7
ns
Altera Corporation
63
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 31. EPF10K30E Device LE Timing Microparameters (Part 2 of 2)
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tCGENR
0.1
0.1
0.2
ns
tCASC
0.6
0.8
1.0
ns
tC
0.0
0.0
0.0
ns
tCO
0.3
0.4
0.5
ns
tCOMB
0.4
0.4
0.6
ns
tSU
0.4
0.6
0.6
tH
0.7
1.0
1.3
0.8
tPRE
tCLR
0.9
0.8
0.9
ns
ns
1.2
ns
1.2
ns
tCH
2.0
2.5
2.5
ns
tCL
2.0
2.5
2.5
ns
Table 32. EPF10K30E Device IOE Timing Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tIOD
2.4
2.8
3.8
ns
tIOC
0.3
0.4
0.5
ns
tIOCO
1.0
1.1
1.6
ns
tIOCOMB
0.0
0.0
0.0
ns
tIOSU
1.2
1.4
1.9
ns
tIOH
0.3
0.4
0.5
ns
tIOCLR
1.0
1.1
1.6
ns
tOD1
1.9
2.3
3.0
ns
tOD2
1.4
1.8
2.5
ns
tOD3
4.4
5.2
7.0
ns
tXZ
2.7
3.1
4.3
ns
tZX1
2.7
3.1
4.3
ns
tZX2
2.2
2.6
3.8
ns
tZX3
5.2
6.0
8.3
ns
tINREG
3.4
4.1
5.5
ns
tIOFD
0.8
1.3
2.4
ns
tINCOMB
0.8
1.3
2.4
ns
64
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 33. EPF10K30E Device EAB Internal Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tEABDATA1
1.7
2.0
2.3
ns
tEABDATA1
0.6
0.7
0.8
ns
tEABWE1
1.1
1.3
1.4
ns
tEABWE2
0.4
0.4
0.5
ns
tEABRE1
0.8
0.9
1.0
ns
tEABRE2
0.4
0.4
0.5
ns
tEABCLK
0.0
0.0
0.0
ns
tEABCO
0.3
0.3
0.4
ns
0.7
ns
tEABBYPASS
0.5
0.6
tEABSU
0.9
1.0
1.2
ns
tEABH
0.4
0.4
0.5
ns
tEABCLR
0.3
0.3
0.3
tAA
3.2
3.8
ns
4.4
ns
tWP
2.5
2.9
3.3
ns
tRP
0.9
1.1
1.2
ns
tWDSU
0.9
1.0
1.1
ns
tWDH
0.1
0.1
0.1
ns
tWASU
1.7
2.0
2.3
ns
tWAH
1.8
2.1
2.4
ns
tRASU
3.1
3.7
4.2
ns
tRAH
0.2
0.2
0.2
ns
tWO
2.5
2.9
3.3
ns
tDD
2.5
2.9
3.3
ns
tEABOUT
0.5
0.6
0.7
ns
tEABCH
1.5
2.0
2.3
ns
tEABCL
2.5
2.9
3.3
ns
Altera Corporation
65
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 34. EPF10K30E Device EAB Internal Timing Macroparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
tEABAA
Max
6.4
Max
7.6
Unit
Max
8.8
ns
tEABRCOMB
6.4
7.6
8.8
ns
tEABRCREG
4.4
5.1
6.0
ns
tEABWP
2.5
2.9
3.3
ns
tEABWCOMB
6.0
7.0
8.0
ns
tEABWCREG
6.8
7.8
9.0
ns
tEABDD
5.7
6.7
7.7
ns
tEABDATACO
0.8
0.9
1.1
ns
tEABDATASU
1.5
1.7
2.0
ns
tEABDATAH
0.0
0.0
0.0
ns
tEABWESU
1.3
1.4
1.7
ns
tEABWEH
0.0
0.0
0.0
ns
tEABWDSU
1.5
1.7
2.0
ns
tEABWDH
0.0
0.0
0.0
ns
tEABWASU
3.0
3.6
4.3
ns
tEABWAH
0.5
0.5
0.4
tEABWO
66
5.1
6.0
ns
6.8
ns
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 35. EPF10K30E Device Interconnect Timing Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tDIN2IOE
1.8
2.4
2.9
ns
tDIN2LE
1.5
1.8
2.4
ns
tDIN2DATA
1.5
1.8
2.2
ns
tDCLK2IOE
2.2
2.6
3.0
ns
tDCLK2LE
1.5
1.8
2.4
ns
tSAMELAB
0.1
0.2
0.3
ns
tSAMEROW
2.0
2.4
2.7
ns
tSAMECOLUMN
0.7
1.0
0.8
ns
tDIFFROW
2.7
3.4
3.5
ns
tTWOROWS
4.7
5.8
6.2
ns
tLEPERIPH
2.7
3.4
3.8
ns
tLABCARRY
0.3
0.4
0.5
ns
tLABCASC
0.8
0.8
1.1
ns
Table 36. EPF10K30E External Timing Parameters
Symbol
Notes (1), (2)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
tDRR
Max
8.0
Max
9.5
Unit
Max
12.5
ns
tINSU (3)
2.1
2.5
3.9
ns
tINH (3)
0.0
0.0
0.0
ns
tOUTCO (3)
2.0
tINSU (4)
1.1
tINH (4)
0.0
tOUTCO (4)
0.5
tPCISU
3.0
tPCIH
0.0
tPCICO
2.0
Altera Corporation
4.9
2.0
5.9
1.5
0.5
ns
–
–
0.0
2.0
–
–
ns
ns
–
7.5
ns
ns
–
4.9
4.2
6.0
7.6
–
0.0
3.9
2.0
ns
–
ns
67
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 37. EPF10K30E External Bidirectional Timing Parameters
Symbol
Notes (1), (2)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tINSUBIDIR (3)
2.8
3.9
5.2
ns
tINHBIDIR (3)
0.0
0.0
0.0
ns
tINSUBIDIR (4)
3.8
4.9
–
ns
tINHBIDIR (4)
0.0
0.0
–
ns
tOUTCOBIDIR (3)
2.0
tXZBIDIR (3)
2.0
6.1
tZXBIDIR (3)
tOUTCOBIDIR (4)
4.9
3.9
2.0
7.5
6.1
0.5
5.9
7.5
0.5
4.9
7.6
ns
9.7
ns
9.7
ns
–
ns
–
tXZBIDIR (4)
5.1
6.5
–
ns
tZXBIDIR (4)
5.1
6.5
–
ns
Notes to tables:
(1)
(2)
(3)
(4)
All timing parameters are described in Tables 24 through 30 in this data sheet.
These parameters are specified by characterization.
This parameter is measured without the use of the ClockLock or ClockBoost circuits.
This parameter is measured with the use of the ClockLock or ClockBoost circuits.
Tables 38 through 44 show EPF10K50E device internal and external
timing parameters.
Table 38. EPF10K50E Device LE Timing Microparameters (Part 1 of 2)
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tLUT
0.6
0.9
1.3
ns
tCLUT
0.5
0.6
0.8
ns
tRLUT
0.7
0.8
1.1
ns
tPACKED
0.4
0.5
0.6
ns
tEN
0.6
0.7
0.9
ns
tCICO
0.2
0.2
0.3
ns
tCGEN
0.5
0.5
0.8
ns
tCGENR
0.2
0.2
0.3
ns
tCASC
0.8
1.0
1.4
ns
tC
0.5
0.6
0.8
ns
tCO
0.7
0.7
0.9
ns
tCOMB
0.5
0.6
0.8
ns
tSU
68
0.7
0.7
0.8
ns
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 38. EPF10K50E Device LE Timing Microparameters (Part 2 of 2)
Symbol
tH
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
0.9
Max
1.0
Unit
Max
1.4
ns
tPRE
0.5
0.6
0.8
ns
tCLR
0.5
0.6
0.8
ns
tCH
2.0
2.5
3.0
ns
tCL
2.0
2.5
3.0
ns
Table 39. EPF10K50E Device IOE Timing Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tIOD
2.2
2.4
3.3
ns
tIOC
0.3
0.3
0.5
ns
tIOCO
1.0
1.0
1.4
ns
tIOCOMB
0.0
0.0
0.2
tIOSU
1.0
tIOH
0.3
1.2
1.7
0.3
ns
ns
0.5
ns
tIOCLR
0.9
1.0
1.4
ns
tOD1
0.8
0.9
1.2
ns
tOD2
0.3
0.4
0.7
ns
tOD3
3.0
3.5
3.5
ns
tXZ
1.4
1.7
2.3
ns
tZX1
1.4
1.7
2.3
ns
tZX2
0.9
1.2
1.8
ns
tZX3
3.6
4.3
4.6
ns
tINREG
4.9
5.8
7.8
ns
tIOFD
2.8
3.3
4.5
ns
tINCOMB
2.8
3.3
4.5
ns
Altera Corporation
69
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 40. EPF10K50E Device EAB Internal Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tEABDATA1
1.7
2.0
2.7
ns
tEABDATA1
0.6
0.7
0.9
ns
tEABWE1
1.1
1.3
1.8
ns
tEABWE2
0.4
0.4
0.6
ns
tEABRE1
0.8
0.9
1.2
ns
tEABRE2
0.4
0.4
0.6
ns
tEABCLK
0.0
0.0
0.0
ns
tEABCO
0.3
0.3
0.5
ns
0.8
ns
tEABBYPASS
0.5
0.6
tEABSU
0.9
1.0
1.4
tEABH
0.4
0.4
0.6
ns
tEABCLR
0.3
0.3
0.5
ns
tAA
3.2
3.8
ns
5.1
ns
tWP
2.5
2.9
3.9
ns
tRP
0.9
1.1
1.5
ns
tWDSU
0.9
1.0
1.4
ns
tWDH
0.1
0.1
0.2
ns
tWASU
1.7
2.0
2.7
ns
tWAH
1.8
2.1
2.9
ns
tRASU
3.1
3.7
5.0
ns
tRAH
0.2
0.2
0.3
ns
tWO
2.5
2.9
3.9
ns
tDD
2.5
2.9
3.9
ns
tEABOUT
0.5
0.6
0.8
ns
tEABCH
1.5
2.0
2.5
ns
tEABCL
2.5
2.9
3.9
ns
70
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 41. EPF10K50E Device EAB Internal Timing Macroparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
tEABAA
Max
6.4
Max
7.6
Unit
Max
10.2
ns
tEABRCOMB
6.4
7.6
10.2
ns
tEABRCREG
4.4
5.1
7.0
ns
tEABWP
2.5
2.9
3.9
ns
tEABWCOMB
6.0
7.0
9.5
ns
tEABWCREG
6.8
7.8
10.6
ns
tEABDD
5.7
6.7
9.0
ns
tEABDATACO
0.8
0.9
1.3
ns
tEABDATASU
1.5
1.7
2.3
ns
tEABDATAH
0.0
0.0
0.0
ns
tEABWESU
1.3
1.4
2.0
ns
tEABWEH
0.0
0.0
0.0
ns
tEABWDSU
1.5
1.7
2.3
ns
tEABWDH
0.0
0.0
0.0
ns
tEABWASU
3.0
3.6
4.8
ns
tEABWAH
0.5
0.5
0.8
tEABWO
5.1
6.0
Table 42. EPF10K50E Device Interconnect Timing Microparameters
Symbol
ns
8.1
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
ns
Unit
Max
tDIN2IOE
3.5
4.3
5.6
ns
tDIN2LE
2.1
2.5
3.4
ns
tDIN2DATA
2.2
2.4
3.1
ns
tDCLK2IOE
2.9
3.5
4.7
ns
tDCLK2LE
2.1
2.5
3.4
ns
tSAMELAB
0.1
0.1
0.2
ns
tSAMEROW
1.1
1.1
1.5
ns
tSAMECOLUMN
0.8
1.0
1.3
ns
tDIFFROW
1.9
2.1
2.8
ns
tTWOROWS
3.0
3.2
4.3
ns
tLEPERIPH
3.1
3.3
3.7
ns
tLABCARRY
0.1
0.1
0.2
ns
tLABCASC
0.3
0.3
0.5
ns
Altera Corporation
71
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 43. EPF10K50E External Timing Parameters
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
tDRR
Max
8.5
tINSU
Notes (1), (2)
2.7
tINH
0.0
tOUTCO
2.0
tPCISU
3.0
tPCIH
0.0
tPCICO
2.0
Max
10.0
4.3
0.0
4.5
2.0
2.0
2.0
-
ns
-
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
tINSUBIDIR
2.7
3.2
4.3
tINHBIDIR
0.0
0.0
0.0
tOUTCOBIDIR
2.0
4.5
2.0
5.2
ns
Notes (1), (2)
-1 Speed Grade
Max
ns
ns
7.7
Table 44. EPF10K50E External Bidirectional Timing Parameters
Symbol
ns
7.3
-
0.0
ns
ns
0.0
5.2
4.2
6.0
Max
13.5
3.2
Unit
2.0
Unit
Max
ns
ns
7.3
ns
tXZBIDIR
6.8
7.8
10.1
ns
tZXBIDIR
6.8
7.8
10.1
ns
Notes to tables:
(1)
(2)
All timing parameters are described in Tables 24 through 30 in this data sheet.
These parameters are specified by characterization.
Tables 45 through 51 show EPF10K100E device internal and external
timing parameters.
Table 45. EPF10K100E Device LE Timing Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tLUT
0.7
1.0
1.5
ns
tCLUT
0.5
0.7
0.9
ns
tRLUT
0.6
0.8
1.1
ns
tPACKED
0.3
0.4
0.5
ns
tEN
0.2
0.3
0.3
ns
tCICO
0.1
0.1
0.2
ns
tCGEN
0.4
0.5
0.7
ns
72
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 45. EPF10K100E Device LE Timing Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tCGENR
0.1
0.1
0.2
ns
tCASC
0.6
0.9
1.2
ns
tC
0.8
1.0
1.4
ns
tCO
0.6
0.8
1.1
ns
tCOMB
0.4
0.5
0.7
ns
tSU
0.4
0.6
0.7
ns
tH
0.5
0.7
0.9
ns
0.8
tPRE
tCLR
1.0
0.8
1.4
1.0
1.4
ns
ns
tCH
1.5
2.0
2.5
ns
tCL
1.5
2.0
2.5
ns
Table 46. EPF10K100E Device IOE Timing Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tIOD
1.7
2.0
2.6
ns
tIOC
0.0
0.0
0.0
ns
tIOCO
1.4
1.6
2.1
ns
tIOCOMB
0.5
0.7
0.9
ns
tIOSU
0.8
1.0
1.3
tIOH
0.7
0.9
1.2
ns
ns
tIOCLR
0.5
0.7
0.9
ns
tOD1
3.0
4.2
5.6
ns
tOD2
3.0
4.2
5.6
ns
tOD3
4.0
5.5
7.3
ns
tXZ
3.5
4.6
6.1
ns
tZX1
3.5
4.6
6.1
ns
tZX2
3.5
4.6
6.1
ns
tZX3
4.5
5.9
7.8
ns
tINREG
2.0
2.6
3.5
ns
tIOFD
0.5
0.8
1.2
ns
tINCOMB
0.5
0.8
1.2
ns
Altera Corporation
73
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 47. EPF10K100E Device EAB Internal Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tEABDATA1
1.5
2.0
2.6
ns
tEABDATA1
0.0
0.0
0.0
ns
tEABWE1
1.5
2.0
2.6
ns
tEABWE2
0.3
0.4
0.5
ns
tEABRE1
0.3
0.4
0.5
ns
tEABRE2
0.0
0.0
0.0
ns
tEABCLK
0.0
0.0
0.0
ns
tEABCO
0.3
0.4
0.5
ns
0.2
ns
tEABBYPASS
0.1
0.1
tEABSU
0.8
1.0
1.4
tEABH
0.1
0.1
0.2
ns
tEABCLR
0.3
0.4
0.5
ns
tAA
4.0
5.1
ns
6.6
ns
tWP
2.7
3.5
4.7
ns
tRP
1.0
1.3
1.7
ns
tWDSU
1.0
1.3
1.7
ns
tWDH
0.2
0.2
0.3
ns
tWASU
1.6
2.1
2.8
ns
tWAH
1.6
2.1
2.8
ns
tRASU
3.0
3.9
5.2
ns
tRAH
0.1
0.1
0.2
ns
tWO
1.5
2.0
2.6
ns
tDD
1.5
2.0
2.6
ns
tEABOUT
0.2
0.3
0.3
ns
tEABCH
1.5
2.0
2.5
ns
tEABCL
2.7
3.5
4.7
ns
Table 48. EPF10K100E Device EAB Internal Timing Macroparameters (Part 1 of 2)
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
tEABAA
Max
5.9
Max
7.6
Note (1)
Unit
Max
9.9
ns
tEABRCOMB
5.9
7.6
9.9
ns
tEABRCREG
5.1
6.5
8.5
ns
tEABWP
2.7
3.5
4.7
ns
74
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 48. EPF10K100E Device EAB Internal Timing Macroparameters (Part 2 of 2)
Symbol
-1 Speed Grade
-2 Speed Grade
Min
Min
Max
Max
-3 Speed Grade
Min
Note (1)
Unit
Max
tEABWCOMB
5.9
7.7
10.3
ns
tEABWCREG
5.4
7.0
9.4
ns
3.4
tEABDD
tEABDATACO
4.5
0.5
5.9
0.7
0.8
ns
ns
tEABDATASU
0.8
1.0
1.4
ns
tEABDATAH
0.1
0.1
0.2
ns
tEABWESU
1.1
1.4
1.9
ns
tEABWEH
0.0
0.0
0.0
ns
tEABWDSU
1.0
1.3
1.7
ns
tEABWDH
0.2
0.2
0.3
ns
tEABWASU
4.1
5.2
6.8
ns
tEABWAH
0.0
0.0
0.0
tEABWO
3.4
4.5
Table 49. EPF10K100E Device Interconnect Timing Microparameters
Symbol
ns
5.9
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
ns
Unit
Max
tDIN2IOE
3.1
3.6
4.4
ns
tDIN2LE
0.3
0.4
0.5
ns
tDIN2DATA
1.6
1.8
2.0
ns
tDCLK2IOE
0.8
1.1
1.4
ns
tDCLK2LE
0.3
0.4
0.5
ns
tSAMELAB
0.1
0.1
0.2
ns
tSAMEROW
1.5
2.5
3.4
ns
tSAMECOLUMN
0.4
1.0
1.6
ns
tDIFFROW
1.9
3.5
5.0
ns
tTWOROWS
3.4
6.0
8.4
ns
tLEPERIPH
4.3
5.4
6.5
ns
tLABCARRY
0.5
0.7
0.9
ns
tLABCASC
0.8
1.0
1.4
ns
Altera Corporation
75
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 50. EPF10K100E External Timing Parameters
Symbol
Notes (1), (2)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
tDRR
Max
9.0
tINSU (3)
2.0
tINH (3)
0.0
tOUTCO (3)
2.0
tINSU (4)
2.0
tINH (4)
0.0
tOUTCO (4)
0.5
tPCISU
3.0
tPCIH
0.0
tPCICO
2.0
Max
12.0
2.5
2.0
6.2
2.0
ns
–
–
ns
–
–
ns
Notes (1), (2)
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
ns
ns
-1 Speed Grade
Max
ns
ns
–
6.9
Table 51. EPF10K100E External Bidirectional Timing Parameters
Symbol
9.1
–
0.0
6.0
ns
2.0
–
4.6
ns
ns
–
0.0
0.5
16.0
0.0
6.9
2.2
3.0
Max
3.3
0.0
5.2
Unit
Unit
Max
tINSUBIDIR (3)
1.7
2.5
3.3
ns
tINHBIDIR (3)
0.0
0.0
0.0
ns
tINSUBIDIR (4)
2.0
2.8
–
ns
tINHBIDIR (4)
0.0
0.0
–
ns
tOUTCOBIDIR (3)
2.0
5.2
2.0
6.9
2.0
9.1
ns
ns
tXZBIDIR (3)
5.6
7.5
10.1
tZXBIDIR (3)
5.6
7.5
10.1
ns
–
ns
tOUTCOBIDIR (4)
0.5
3.0
0.5
4.6
–
tXZBIDIR (4)
4.6
6.5
–
ns
tZXBIDIR (4)
4.6
6.5
–
ns
Notes to tables:
(1)
(2)
(3)
(4)
76
All timing parameters are described in Tables 24 through 30 in this data sheet.
These parameters are specified by characterization.
This parameter is measured without the use of the ClockLock or ClockBoost circuits.
This parameter is measured with the use of the ClockLock or ClockBoost circuits.
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Tables 52 through 58 show EPF10K130E device internal and external
timing parameters.
Table 52. EPF10K130E Device LE Timing Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tLUT
0.6
0.9
1.3
ns
tCLUT
0.6
0.8
1.0
ns
tRLUT
0.7
0.9
0.2
ns
tPACKED
0.3
0.5
0.6
ns
tEN
0.2
0.3
0.4
ns
tCICO
0.1
0.1
0.2
ns
tCGEN
0.4
0.6
0.8
ns
tCGENR
0.1
0.1
0.2
ns
tCASC
0.6
0.9
1.2
ns
tC
0.3
0.5
0.6
ns
tCO
0.5
0.7
0.8
ns
0.6
ns
0.3
tCOMB
0.5
tSU
0.5
0.7
0.8
ns
tH
0.6
0.7
1.0
ns
tPRE
0.9
1.2
1.6
tCLR
0.9
1.2
1.6
ns
ns
tCH
1.5
1.5
2.5
ns
tCL
1.5
1.5
2.5
ns
Table 53. EPF10K130E Device IOE Timing Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tIOD
1.3
1.5
2.0
ns
tIOC
0.0
0.0
0.0
ns
tIOCO
0.6
0.8
1.0
ns
tIOCOMB
0.6
0.8
1.0
ns
tIOSU
1.0
1.2
1.6
ns
tIOH
0.9
0.9
1.4
ns
tIOCLR
0.6
0.8
1.0
ns
tOD1
2.8
4.1
5.5
ns
tOD2
2.8
4.1
5.5
ns
Altera Corporation
77
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 53. EPF10K130E Device IOE Timing Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tOD3
4.0
5.6
7.5
ns
tXZ
2.8
4.1
5.5
ns
tZX1
2.8
4.1
5.5
ns
tZX2
2.8
4.1
5.5
ns
tZX3
4.0
5.6
7.5
ns
tINREG
2.5
3.0
4.1
ns
tIOFD
0.4
0.5
0.6
ns
tINCOMB
0.4
0.5
0.6
ns
Table 54. EPF10K130E Device EAB Internal Microparameters (Part 1 of 2)
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tEABDATA1
1.5
2.0
2.6
ns
tEABDATA2
0.0
0.0
0.0
ns
tEABWE1
1.5
2.0
2.6
ns
tEABWE2
0.3
0.4
0.5
ns
tEABRE1
0.3
0.4
0.5
ns
tEABRE2
0.0
0.0
0.0
ns
tEABCLK
0.0
0.0
0.0
ns
tEABCO
0.3
0.4
0.5
ns
tEABBYPASS
0.1
0.1
0.2
ns
tEABSU
0.8
1.0
1.4
tEABH
0.1
0.2
0.2
ns
tEABCLR
0.3
0.4
0.5
ns
tAA
4.0
5.0
ns
6.6
ns
tWP
2.7
3.5
4.7
ns
tRP
1.0
1.3
1.7
ns
tWDSU
1.0
1.3
1.7
ns
tWDH
0.2
0.2
0.3
ns
tWASU
1.6
2.1
2.8
ns
tWAH
1.6
2.1
2.8
ns
tRASU
3.0
3.9
5.2
ns
tRAH
0.1
0.1
0.2
tWO
78
1.5
2.0
ns
2.6
ns
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 54. EPF10K130E Device EAB Internal Microparameters (Part 2 of 2)
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tDD
1.5
2.0
2.6
ns
tEABOUT
0.2
0.3
0.3
ns
tEABCH
1.5
2.0
2.5
ns
tEABCL
2.7
3.5
4.7
ns
Table 55. EPF10K130E Device EAB Internal Timing Macroparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
tEABAA
Max
5.9
Max
7.5
Unit
Max
9.9
ns
tEABRCOMB
5.9
7.5
9.9
ns
tEABRCREG
5.1
6.4
8.5
ns
tEABWP
2.7
3.5
4.7
ns
tEABWCOMB
5.9
7.7
10.3
ns
tEABWCREG
5.4
7.0
9.4
ns
tEABDD
3.4
4.5
5.9
ns
tEABDATACO
0.5
0.7
0.8
ns
tEABDATASU
0.8
1.0
1.4
ns
tEABDATAH
0.1
0.1
0.2
ns
tEABWESU
1.1
1.4
1.9
ns
tEABWEH
0.0
0.0
0.0
ns
tEABWDSU
1.0
1.3
1.7
ns
tEABWDH
0.2
0.2
0.3
ns
tEABWASU
4.1
5.1
6.8
ns
tEABWAH
0.0
0.0
0.0
tEABWO
Altera Corporation
3.4
4.5
ns
5.9
ns
79
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 56. EPF10K130E Device Interconnect Timing Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tDIN2IOE
2.8
3.5
4.4
ns
tDIN2LE
0.7
1.2
1.6
ns
tDIN2DATA
1.6
1.9
2.2
ns
tDCLK2IOE
1.6
2.1
2.7
ns
tDCLK2LE
0.7
1.2
1.6
ns
tSAMELAB
0.1
0.2
0.2
ns
tSAMEROW
1.9
3.4
5.1
ns
tSAMECOLUMN
0.9
2.6
4.4
ns
tDIFFROW
2.8
6.0
9.5
ns
tTWOROWS
4.7
9.4
14.6
ns
tLEPERIPH
3.1
4.7
6.9
ns
tLABCARRY
0.6
0.8
1.0
ns
tLABCASC
0.9
1.2
1.6
ns
Table 57. EPF10K130E External Timing Parameters
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
tDRR
Max
9.0
tINSU (3)
1.9
tINH (3)
0.0
tOUTCO (3)
2.0
tINSU (4)
0.9
tINH (4)
0.0
tOUTCO (4)
0.5
tPCISU
3.0
tPCIH
0.0
tPCICO
2.0
80
Notes (1), (2)
Max
12.0
2.1
2.0
–
ns
–
–
ns
ns
–
6.9
ns
ns
–
0.0
2.0
ns
9.2
–
6.0
6.2
6.0
2.0
ns
ns
–
0.0
0.5
16.0
0.0
7.0
1.1
4.0
Max
3.0
0.0
5.0
Unit
ns
–
ns
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 58. EPF10K130E External Bidirectional Timing Parameters
Symbol
Notes (1), (2)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tINSUBIDIR (3)
2.2
2.4
3.2
tINHBIDIR (3)
0.0
0.0
0.0
ns
tINSUBIDIR (4)
2.8
3.0
–
ns
tINHBIDIR (4)
0.0
tOUTCOBIDIR (3)
2.0
tXZBIDIR (3)
2.0
5.6
tZXBIDIR (3)
tOUTCOBIDIR (4)
0.0
5.0
4.0
–
7.0
ns
2.0
8.1
5.6
0.5
ns
8.1
0.5
6.0
–
9.2
ns
10.8
ns
10.8
ns
–
ns
tXZBIDIR (4)
4.6
7.1
–
ns
tZXBIDIR (4)
4.6
7.1
–
ns
Notes to tables:
(1)
(2)
(3)
(4)
All timing parameters are described in Tables 24 through 30 in this data sheet.
These parameters are specified by characterization.
This parameter is measured without the use of the ClockLock or ClockBoost circuits.
This parameter is measured with the use of the ClockLock or ClockBoost circuits.
Tables 59 through 65 show EPF10K200E device internal and external
timing parameters.
Table 59. EPF10K200E Device LE Timing Microparameters (Part 1 of 2)
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tLUT
0.7
0.8
1.2
ns
tCLUT
0.4
0.5
0.6
ns
tRLUT
0.6
0.7
0.9
ns
tPACKED
0.3
0.5
0.7
ns
tEN
0.4
0.5
0.6
ns
tCICO
0.2
0.2
0.3
ns
tCGEN
0.4
0.4
0.6
ns
tCGENR
0.2
0.2
0.3
ns
tCASC
0.7
0.8
1.2
ns
tC
0.5
0.6
0.8
ns
tCO
0.5
0.6
0.8
ns
tCOMB
0.4
0.6
0.8
ns
tSU
Altera Corporation
0.4
0.6
0.7
ns
81
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 59. EPF10K200E Device LE Timing Microparameters (Part 2 of 2)
Symbol
tH
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
0.9
tPRE
0.5
tCLR
Max
1.1
0.5
Max
1.5
0.6
0.6
Unit
ns
0.8
ns
0.8
ns
tCH
2.0
2.5
3.0
ns
tCL
2.0
2.5
3.0
ns
Table 60. EPF10K200E Device IOE Timing Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tIOD
1.6
1.9
2.6
ns
tIOC
0.3
0.3
0.5
ns
tIOCO
1.6
1.9
2.6
ns
tIOCOMB
0.5
0.6
0.8
ns
tIOSU
0.8
tIOH
0.7
0.9
1.2
0.8
ns
1.1
ns
tIOCLR
0.2
0.2
0.3
ns
tOD1
0.6
0.7
0.9
ns
tOD2
0.1
0.2
0.7
ns
tOD3
2.5
3.0
3.9
ns
tXZ
4.4
5.3
7.1
ns
tZX1
4.4
5.3
7.1
ns
tZX2
3.9
4.8
6.9
ns
tZX3
6.3
7.6
10.1
ns
tINREG
4.8
5.7
7.7
ns
tIOFD
1.5
1.8
2.4
ns
tINCOMB
1.5
1.8
2.4
ns
82
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 61. EPF10K200E Device EAB Internal Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tEABDATA1
2.0
2.4
3.2
ns
tEABDATA1
0.4
0.5
0.6
ns
tEABWE1
1.4
1.7
2.3
ns
tEABWE2
0.0
0.0
0.0
ns
tEABRE1
0
0
0
ns
tEABRE2
0.4
0.5
0.6
ns
tEABCLK
0.0
0.0
0.0
ns
tEABCO
0.8
0.9
1.2
ns
0.1
ns
tEABBYPASS
0.0
0.1
tEABSU
0.9
1.1
1.5
ns
tEABH
0.4
0.5
0.6
ns
tEABCLR
0.8
0.9
1.2
tAA
3.1
3.7
ns
4.9
ns
tWP
3.3
4.0
5.3
ns
tRP
0.9
1.1
1.5
ns
tWDSU
0.9
1.1
1.5
ns
tWDH
0.1
0.1
0.1
ns
tWASU
1.3
1.6
2.1
ns
tWAH
2.1
2.5
3.3
ns
tRASU
2.2
2.6
3.5
ns
tRAH
0.1
0.1
0.2
ns
tWO
2.0
2.4
3.2
ns
tDD
2.0
2.4
3.2
ns
tEABOUT
0.0
0.1
0.1
ns
tEABCH
1.5
2.0
2.5
ns
tEABCL
3.3
4.0
5.3
ns
Table 62. EPF10K200E Device EAB Internal Timing Macroparameters (Part 1 of 2)
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
tEABAA
Max
5.1
Max
6.4
Note (1)
Unit
Max
8.4
ns
tEABRCOMB
5.1
6.4
8.4
ns
tEABRCREG
4.8
5.7
7.6
ns
tEABWP
3.3
4.0
5.3
ns
Altera Corporation
83
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 62. EPF10K200E Device EAB Internal Timing Macroparameters (Part 2 of 2)
Symbol
-1 Speed Grade
-2 Speed Grade
Min
Min
Max
Max
-3 Speed Grade
Min
Note (1)
Unit
Max
tEABWCOMB
6.7
8.1
10.7
ns
tEABWCREG
6.6
8.0
10.6
ns
tEABDD
4.0
5.1
6.7
ns
tEABDATACO
0.8
1.0
1.3
ns
tEABDATASU
1.3
1.6
2.1
ns
tEABDATAH
0.0
0.0
0.0
ns
tEABWESU
0.9
1.1
1.5
ns
tEABWEH
0.4
0.5
0.6
ns
tEABWDSU
1.5
1.8
2.4
ns
tEABWDH
0.0
0.0
0.0
ns
tEABWASU
3.0
3.6
4.7
ns
tEABWAH
0.4
0.5
0.7
tEABWO
3.4
5.8
Table 63. EPF10K200E Device Interconnect Timing Microparameters
Symbol
ns
4.4
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
ns
Unit
Max
tDIN2IOE
4.2
4.6
5.7
ns
tDIN2LE
1.7
1.7
2.0
ns
tDIN2DATA
1.9
2.1
3.0
ns
tDCLK2IOE
2.5
2.9
4.0
ns
tDCLK2LE
1.7
1.7
2.0
ns
tSAMELAB
0.1
0.1
0.2
ns
tSAMEROW
2.3
2.6
3.6
ns
tSAMECOLUMN
2.5
2.7
4.1
ns
tDIFFROW
4.8
5.3
7.7
ns
tTWOROWS
7.1
7.9
11.3
ns
tLEPERIPH
7.0
7.6
9.0
ns
tLABCARRY
0.1
0.1
0.2
ns
tLABCASC
0.9
1.0
1.4
ns
84
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 64. EPF10K200E External Timing Parameters
Symbol
Notes (1), (2)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
tDRR
Max
10.0
Max
12.0
Unit
Max
16.0
ns
tINSU
2.8
3.4
4.4
ns
tINH
0.0
0.0
0.0
ns
tOUTCO
2.0
tPCISU
3.0
tPCIH
0.0
tPCICO
2.0
4.5
2.0
5.3
0.0
6.0
2.0
7.8
-
ns
-
-
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
tINSUBIDIR
3.0
4.0
5.5
tINHBIDIR
0.0
0.0
0.0
tOUTCOBIDIR
2.0
4.5
2.0
5.3
ns
Notes (1), (2)
-1 Speed Grade
Max
ns
ns
8.9
Table 65. EPF10K200E External Bidirectional Timing Parameters
Symbol
2.0
6.2
2.0
Unit
Max
ns
ns
7.8
ns
tXZBIDIR
8.1
9.5
13.0
ns
tZXBIDIR
8.1
9.5
13.0
ns
Notes to tables:
(1)
(2)
All timing parameters are described in Tables 24 through 30 in this data sheet.
These parameters are specified by characterization.
Tables 66 through 79 show EPF10K50S and EPF10K200S device external
timing parameters.
Table 66. EPF10K50S Device LE Timing Microparameters (Part 1 of 2)
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tLUT
0.6
0.8
1.1
ns
tCLUT
0.5
0.6
0.8
ns
tRLUT
0.6
0.7
0.9
ns
tPACKED
0.2
0.3
0.4
ns
tEN
0.6
0.7
0.9
ns
tCICO
0.1
0.1
0.1
ns
tCGEN
0.4
0.5
0.6
ns
Altera Corporation
85
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 66. EPF10K50S Device LE Timing Microparameters (Part 2 of 2)
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tCGENR
0.1
0.1
0.1
ns
tCASC
0.5
0.8
1.0
ns
tC
0.5
0.6
0.8
ns
tCO
0.6
0.6
0.7
ns
tCOMB
0.3
0.4
0.5
ns
tSU
0.5
0.6
0.7
ns
tH
0.5
0.6
0.8
ns
0.4
tPRE
tCLR
0.5
0.8
1.0
0.7
ns
1.2
ns
tCH
2.0
2.5
3.0
ns
tCL
2.0
2.5
3.0
ns
Table 67. EPF10K50S Device IOE Timing Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tIOD
1.3
1.3
1.9
ns
tIOC
0.3
0.4
0.4
ns
tIOCO
1.7
2.1
2.6
ns
tIOCOMB
0.5
0.6
0.8
ns
tIOSU
0.8
1.0
1.3
ns
tIOH
0.4
0.5
0.6
ns
tIOCLR
0.2
0.2
0.4
ns
tOD1
1.2
1.2
1.9
ns
tOD2
0.7
0.8
1.7
ns
tOD3
2.7
3.0
4.3
ns
tXZ
4.7
5.7
7.5
ns
tZX1
4.7
5.7
7.5
ns
tZX2
4.2
5.3
7.3
ns
tZX3
6.2
7.5
9.9
ns
tINREG
3.5
4.2
5.6
ns
tIOFD
1.1
1.3
1.8
ns
tINCOMB
1.1
1.3
1.8
ns
86
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 68. EPF10K50S Device EAB Internal Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tEABDATA1
1.7
2.4
3.2
ns
tEABDATA2
0.4
0.6
0.8
ns
tEABWE1
1.0
1.4
1.9
ns
tEABWE2
0.0
0.0
0.0
ns
tEABRE1
0.0
0.0
0.0
tEABRE2
0.4
0.6
0.8
tEABCLK
0.0
0.0
0.0
ns
tEABCO
0.8
1.1
1.5
ns
0.0
ns
tEABBYPASS
0.0
0.0
tEABSU
0.7
1.0
1.3
ns
tEABH
0.4
0.6
0.8
ns
tEABCLR
0.8
1.1
1.5
tAA
2.0
2.8
3.8
ns
tWP
2.0
2.8
3.8
tRP
1.0
1.4
1.9
tWDSU
0.5
0.7
0.9
ns
tWDH
0.1
0.1
0.2
ns
tWASU
1.0
1.4
1.9
ns
tWAH
1.5
2.1
2.9
ns
tRASU
1.5
2.1
2.8
tRAH
0.1
0.1
ns
0.2
tWO
2.1
2.9
4.0
ns
tDD
2.1
2.9
4.0
ns
tEABOUT
0.0
0.0
0.0
ns
tEABCH
1.5
2.0
2.5
ns
tEABCL
1.5
2.0
2.5
ns
Altera Corporation
87
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 69. EPF10K50S Device EAB Internal Timing Macroparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
tEABAA
Max
3.7
Max
5.2
Unit
Max
7.0
ns
tEABRCCOMB
3.7
5.2
7.0
ns
tEABRCREG
3.5
4.9
6.6
ns
tEABWP
2.0
2.8
3.8
ns
tEABWCCOMB
4.5
6.3
8.6
ns
tEABWCREG
5.6
7.8
10.6
ns
tEABDD
3.8
5.3
7.2
ns
tEABDATACO
0.8
1.1
1.5
ns
tEABDATASU
1.1
1.6
2.1
ns
tEABDATAH
0.0
0.0
0.0
ns
tEABWESU
0.7
1.0
1.3
ns
tEABWEH
0.4
0.6
0.8
ns
tEABWDSU
1.2
1.7
2.2
ns
tEABWDH
0.0
0.0
0.0
ns
tEABWASU
1.6
2.3
3.0
ns
tEABWAH
0.9
1.2
1.8
3.1
tEABWO
4.3
Table 70. EPF10K50S Device Interconnect Timing Microparameters
Symbol
ns
5.9
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
ns
Unit
Max
tDIN2IOE
3.1
3.7
4.6
ns
tDIN2LE
1.7
2.1
2.7
ns
tDIN2DATA
2.7
3.1
5.1
ns
tDCLK2IOE
1.6
1.9
2.6
ns
tDCLK2LE
1.7
2.1
2.7
ns
tSAMELAB
0.1
0.1
0.2
ns
tSAMEROW
1.5
1.7
2.4
ns
tSAMECOLUMN
1.0
1.3
2.1
ns
tDIFFROW
2.5
3.0
4.5
ns
tTWOROWS
4.0
4.7
6.9
ns
tLEPERIPH
2.6
2.9
3.4
ns
tLABCARRY
0.1
0.2
0.2
ns
tLABCASC
0.8
1.0
1.3
ns
88
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 71. EPF10K50S External Timing Parameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
tDRR
Max
8.0
Max
9.5
Unit
Max
12.5
ns
tINSU (2)
2.4
2.9
3.9
ns
tINH (2)
0.0
0.0
0.0
ns
tOUTCO (2)
2.0
tINSU (3)
2.4
tINH (3)
0.0
tOUTCO (3)
0.5
tPCISU
2.4
tPCIH
0.0
tPCICO
2.0
4.3
2.0
5.2
7.3
0.0
3.3
0.5
ns
4.1
2.9
2.0
ns
–
0.0
6.0
ns
–
7.7
–
ns
–
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
ns
Note (1)
-1 Speed Grade
Max
ns
ns
Table 72. EPF10K50S External Bidirectional Timing Parameters
Symbol
2.0
2.9
Unit
Max
tINSUBIDIR (2)
2.7
3.2
4.3
ns
tINHBIDIR (2)
0.0
0.0
0.0
ns
tINHBIDIR (3)
0.0
0.0
–
ns
tINSUBIDIR (3)
3.7
4.2
–
ns
tOUTCOBIDIR (2)
2.0
4.5
2.0
5.2
2.0
7.3
ns
tXZBIDIR (2)
6.8
7.8
10.1
ns
tZXBIDIR (2)
6.8
7.8
10.1
ns
tOUTCOBIDIR (3)
0.5
3.5
0.5
4.2
–
–
tXZBIDIR (3)
6.8
8.4
–
ns
tZXBIDIR (3)
6.8
8.4
–
ns
Notes to tables:
(1)
(2)
(3)
All timing parameters are described in Tables 24 through 30.
This parameter is measured without use of the ClockLock or ClockBoost circuits.
This parameter is measured with use of the ClockLock or ClockBoost circuits
Altera Corporation
89
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 73. EPF10K200S Device Internal & External Timing Parameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tLUT
0.7
0.8
1.2
ns
tCLUT
0.4
0.5
0.6
ns
tRLUT
0.5
0.7
0.9
ns
tPACKED
0.4
0.5
0.7
ns
tEN
0.6
0.5
0.6
ns
tCICO
0.1
0.2
0.3
ns
tCGEN
0.3
0.4
0.6
ns
tCGENR
0.1
0.2
0.3
ns
tCASC
0.7
0.8
1.2
ns
tC
0.5
0.6
0.8
ns
tCO
0.5
0.6
0.8
ns
tCOMB
0.3
0.6
0.8
ns
tSU
0.4
0.6
0.7
ns
tH
1.0
1.1
1.5
ns
tPRE
0.4
0.6
0.8
ns
tCLR
0.5
0.6
0.8
ns
tCH
2.0
2.5
3.0
ns
tCL
2.0
2.5
3.0
ns
Table 74. EPF10K200S Device IOE Timing Microparameters (Part 1 of 2)
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tIOD
1.8
1.9
2.6
ns
tIOC
0.3
0.3
0.5
ns
tIOCO
1.7
1.9
2.6
ns
0.8
ns
0.5
tIOCOMB
0.6
tIOSU
0.8
0.9
1.2
ns
tIOH
0.4
0.8
1.1
ns
tIOCLR
0.2
0.2
0.3
ns
tOD1
1.3
0.7
0.9
ns
tOD2
0.8
0.2
0.4
ns
tOD3
2.9
3.0
3.9
ns
tXZ
5.0
5.3
7.1
ns
tZX1
5.0
5.3
7.1
ns
90
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 74. EPF10K200S Device IOE Timing Microparameters (Part 2 of 2)
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tZX2
4.5
4.8
6.6
ns
tZX3
6.6
7.6
10.1
ns
tINREG
3.7
5.7
7.7
ns
tIOFD
1.8
3.4
4.0
ns
tINCOMB
1.8
3.4
4.0
ns
Table 75. EPF10K200S Device EAB Internal Microparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
Unit
Max
tEABDATA1
1.8
2.4
3.2
ns
tEABDATA1
0.4
0.5
0.6
ns
tEABWE1
1.1
1.7
2.3
ns
tEABWE2
0.0
0.0
0.0
ns
tEABRE1
0
0
0
ns
tEABRE2
0.4
0.5
0.6
ns
tEABCLK
0.0
0.0
0.0
ns
tEABCO
0.8
0.9
1.2
ns
tEABBYPASS
0.0
0.1
0.1
ns
tEABSU
0.7
1.1
1.5
ns
tEABH
0.4
0.5
0.6
ns
tEABCLR
0.8
0.9
1.2
tAA
2.1
3.7
ns
4.9
ns
tWP
2.1
4.0
5.3
ns
tRP
1.1
1.1
1.5
ns
tWDSU
0.5
1.1
1.5
ns
tWDH
0.1
0.1
0.1
ns
tWASU
1.1
1.6
2.1
ns
tWAH
1.6
2.5
3.3
ns
tRASU
1.6
2.6
3.5
ns
tRAH
0.1
0.1
0.2
ns
tWO
2.0
2.4
3.2
ns
tDD
2.0
2.4
3.2
ns
tEABOUT
0.0
0.1
0.1
ns
tEABCH
1.5
2.0
2.5
ns
tEABCL
2.1
2.8
3.8
ns
Altera Corporation
91
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 76. EPF10K200S Device EAB Internal Timing Macroparameters
Symbol
Note (1)
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
tEABAA
Max
3.9
Max
6.4
Unit
Max
8.4
ns
tEABRCOMB
3.9
6.4
8.4
ns
tEABRCREG
3.6
5.7
7.6
ns
tEABWP
2.1
4.0
5.3
ns
tEABWCOMB
4.8
8.1
10.7
ns
tEABWCREG
5.4
8.0
10.6
ns
tEABDD
3.8
5.1
6.7
ns
tEABDATACO
0.8
1.0
1.3
ns
tEABDATASU
1.1
1.6
2.1
ns
tEABDATAH
0.0
0.0
0.0
ns
tEABWESU
0.7
1.1
1.5
ns
tEABWEH
0.4
0.5
0.6
ns
tEABWDSU
1.2
1.8
2.4
ns
tEABWDH
0.0
0.0
0.0
ns
tEABWASU
1.9
3.6
4.7
ns
tEABWAH
0.8
0.5
0.7
3.1
tEABWO
4.4
ns
5.8
Table 77. EPF10K200S Device Interconnect Timing Microparameters (Part 1 of 2)
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
ns
Note (1)
Unit
Max
tDIN2IOE
4.4
4.8
5.5
ns
tDIN2LE
0.6
0.6
0.9
ns
tDIN2DATA
1.8
2.1
2.8
ns
tDCLK2IOE
1.7
2.0
2.8
ns
tDCLK2LE
0.6
0.6
0.9
ns
tSAMELAB
0.1
0.1
0.2
ns
tSAMEROW
3.0
4.6
5.7
ns
tSAMECOLUMN
3.5
4.9
6.4
ns
tDIFFROW
6.5
9.5
12.1
ns
tTWOROWS
9.5
14.1
17.8
ns
tLEPERIPH
5.5
6.2
7.2
ns
tLABCARRY
0.3
0.1
0.2
ns
92
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Table 77. EPF10K200S Device Interconnect Timing Microparameters (Part 2 of 2)
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
tLABCASC
Max
0.5
Max
1.0
Table 78. EPF10K200S External Timing Parameters
Symbol
Note (1)
Max
1.4
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
tDRR
9.0
ns
Note (1)
-1 Speed Grade
Max
Unit
Max
12.0
Unit
Max
16.0
ns
tINSU (2)
3.1
3.7
4.7
ns
tINH (2)
0.0
0.0
0.0
ns
tOUTCO (2)
2.0
3.7
2.0
4.4
2.0
6.3
ns
tINSU(3)
2.1
2.7
–
tINH (3)
0.0
0.0
–
tOUTCO(3)
0.5
tPCISU
3.0
4.2
–
ns
tPCIH
0.0
0.0
–
ns
tPCICO
2.0
2.7
6.0
0.5
2.0
3.4
8.9
Table 79. EPF10K200S External Bidirectional Timing Parameters
Symbol
tINSUBIDIR (2)
–
–
ns
ns
–
–
-2 Speed Grade
-3 Speed Grade
Min
Min
Min
Max
Max
ns
Note (1)
-1 Speed Grade
2.3
ns
3.4
4.4
Unit
Max
ns
tINHBIDIR (2)
0.0
0.0
0.0
ns
tINSUBIDIR (3)
3.3
4.4
–
ns
tINHBIDIR (3)
0.0
tOUTCOBIDIR (2)
2.0
0.0
3.7
2.0
–
4.4
2.0
ns
6.3
ns
tXZBIDIR (2)
6.9
7.6
9.2
ns
tZXBIDIR (2)
5.9
6.6
–
ns
tOUTCOBIDIR (3)
–
ns
tXZBIDIR (3)
0.5
2.7
6.9
0.5
3.4
7.6
–
9.2
ns
tZXBIDIR (3)
5.9
6.6
–
ns
Notes to tables:
(1)
(2)
(3)
All timing parameters are described in Tables 24 through 30 in this data sheet.
This parameter is measured without the use of the ClockLock or ClockBoost circuits.
This parameter is measured with the use of the ClockLock or ClockBoost circuits.
Altera Corporation
93
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Power
Consumption
The supply power (P) for FLEX 10KE devices can be calculated with the
following equation:
P = PINT + PIO = (I CCSTANDBY + ICCACTIVE) × VCC + PIO
The ICCACTIVE value depends on the switching frequency and the
application logic. This value is calculated based on the amount of current
that each LE typically consumes. The PIO value, which depends on the
device output load characteristics and switching frequency, can be
calculated using the guidelines given in Application Note 74 (Evaluating
Power for Altera Devices).
Compared to the rest of the device, the embedded array consumes a
negligible amount of power. Therefore, the embedded array can be
ignored when calculating supply current.
The ICCACTIVE value can be calculated with the following equation:
µA
ICCACTIVE = K × fMAX × N × togLC × --------------------------MHz × LE
Where:
fMAX
N
togLC
=
=
=
K
=
Maximum operating frequency in MHz
Total number of LEs used in the device
Average percent of LEs toggling at each clock
(typically 12.5%)
Constant
Table 80 provides the constant (K) values for FLEX 10KE devices.
Table 80. FLEX 10KE K Constant Values
Device
K Value
EPF10K30E
4.5
EPF10K50E
4.8
EPF10K50S
4.5
EPF10K100E
4.5
EPF10K130E
4.6
EPF10K200E
4.8
EPF10K200S
4.6
This calculation provides an ICC estimate based on typical conditions with
no output load. The actual ICC should be verified during operation
because this measurement is sensitive to the actual pattern in the device
and the environmental operating conditions.
94
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
To better reflect actual designs, the power model (and the constant K in
the power calculation equations) for continuous interconnect FLEX
devices assumes that LEs drive FastTrack Interconnect channels. In
contrast, the power model of segmented FPGAs assumes that all LEs drive
only one short interconnect segment. This assumption may lead to
inaccurate results when compared to measured power consumption for
actual designs in segmented FPGAs.
Figure 31 shows the relationship between the current and operating
frequency of FLEX 10KE devices.
Figure 31. FLEX 10KE ICCACTIVE vs. Operating Frequency (Part 1 of 2)
EPF10K50E
EPF10K30E
200
100
80
ICC Supply
150
ICC Supply
60
Current (mA)
Current (mA)
100
40
50
20
0
50
0
100
50
100
Frequency (MHz)
Frequency (MHz)
EPF10K100E
EPF10K50S
300
200
150
ICC Supply
ICC Supply
Current (mA)
200
Current (mA)
100
100
50
0
50
Frequency (MHz)
Altera Corporation
100
0
50
100
Frequency (MHz)
95
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 31. FLEX 10KE ICCACTIVE vs. Operating Frequency (Part 2 of 2)
EPF10K130E
EPF10K200E
400
600
300
ICC Supply
Current (mA)
ICC Supply
200
400
Current (mA)
200
100
0
50
0
100
50
100
Frequency (MHz)
Frequency (MHz)
EPF10K200S
600
ICC Supply
400
Current (mA)
200
0
50
100
Frequency (MHz)
Configuration &
Operation
The FLEX 10KE architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
configuration schemes.
Operating Modes
The FLEX 10KE architecture uses SRAM configuration elements that
require configuration data to be loaded every time the circuit powers up.
The process of physically loading the SRAM data into the device is called
configuration. Before configuration, as VCC rises, the device initiates a
Power-On Reset (POR). This POR event clears the device and prepares it
for configuration. The FLEX 10KE POR time does not exceed 50 µs.
When configuring with a configuration device, refer to the respective
configuration device data sheet for POR timing information.
96
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
During initialization, which occurs immediately after configuration, the
device resets registers, enables I/O pins, and begins to operate as a logic
device. The I/O pins are tri-stated during power-up, and before and
during configuration. Together, the configuration and initialization
processes are called command mode; normal device operation is called user
mode.
SRAM configuration elements allow FLEX 10KE devices to be
reconfigured in-circuit by loading new configuration data into the device.
Real-time reconfiguration is performed by forcing the device into
command mode with a device pin, loading different configuration data,
reinitializing the device, and resuming user-mode operation. The entire
reconfiguration process requires less than 85 ms and can be used to
reconfigure an entire system dynamically. In-field upgrades can be
performed by distributing new configuration files.
Before and during configuration, all I/O pins (except dedicated inputs,
clock, or configuration pins) are pulled high by a weak pull-up resistor.
Programming Files
Despite being function- and pin-compatible, FLEX 10KE devices are not
programming- or configuration file-compatible with FLEX 10K or
FLEX 10KA devices. A design therefore must be recompiled before it is
transferred from a FLEX 10K or FLEX 10KA device to an equivalent
FLEX 10KE device. This recompilation should be performed both to create
a new programming or configuration file and to check design timing in
FLEX 10KE devices, which has different timing characteristics than
FLEX 10K or FLEX 10KA devices.
FLEX 10KE devices are generally pin-compatible with equivalent
FLEX 10KA devices. In some cases, FLEX 10KE devices have fewer I/O
pins than the equivalent FLEX 10KA devices. Table 81 shows which
FLEX 10KE devices have fewer I/O pins than equivalent FLEX 10KA
devices. However, power, ground, JTAG, and configuration pins are the
same on FLEX 10KA and FLEX 10KE devices, enabling migration from a
FLEX 10KA design to a FLEX 10KE design.
Altera Corporation
97
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Additionally, the Altera software offers several features that help plan for
future device migration by preventing the use of conflicting I/O pins.
Table 81. I/O Counts for FLEX 10KA & FLEX 10KE Devices
FLEX 10KA
FLEX 10KE
Device
I/O Count
Device
I/O Count
EPF10K30AF256
191
EPF10K30EF256
176
EPF10K30AF484
246
EPF10K30EF484
220
EPF10K50VB356
274
EPF10K50SB356
220
EPF10K50VF484
291
EPF10K50EF484
254
EPF10K50VF484
291
EPF10K50SF484
254
EPF10K100AF484
369
EPF10K100EF484
338
Configuration Schemes
The configuration data for a FLEX 10KE device can be loaded with one of
five configuration schemes (see Table 82), chosen on the basis of the target
application. An EPC1, EPC2, or EPC16 configuration device, intelligent
controller, or the JTAG port can be used to control the configuration of a
FLEX 10KE device, allowing automatic configuration on system
power-up.
Multiple FLEX 10KE devices can be configured in any of the five
configuration schemes by connecting the configuration enable (nCE) and
configuration enable output (nCEO) pins on each device. Additional
FLEX 10K, FLEX 10KA, FLEX 10KE, and FLEX 6000 devices can be
configured in the same serial chain.
Table 82. Data Sources for FLEX 10KE Configuration
Configuration Scheme
Data Source
Configuration device
EPC1, EPC2, or EPC16 configuration device
Passive serial (PS)
BitBlaster, ByteBlasterMV, or MasterBlaster download cables,
or serial data source
Passive parallel asynchronous (PPA)
Parallel data source
Passive parallel synchronous (PPS)
Parallel data source
JTAG
BitBlaster or ByteBlasterMV download cables, or
microprocessor with a Jam STAPL file or JBC file
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Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Device
Pin-Outs
See the Altera web site (http://www.altera.com) or the Altera Digital
Library for pin-out information.
Revision
History
The information contained in the FLEX 10KE Embedded Programmable Logic
Data Sheet version 2.5 supersedes information published in previous
versions.
Version 2.5
The following changes were made to the FLEX 10KE Embedded
Programmable Logic Data Sheet version 2.5:
■
■
■
Note (1) added to Figure 23.
Text added to “I/O Element” section on page 34.
Updated Table 22.
Version 2.4
The following changes were made to the FLEX 10KE Embedded
Programmable Logic Data Sheet version 2.4: updated text on page 34 and
page 63.
Altera Corporation
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FLEX 10KE Embedded Programmable Logic Devices Data Sheet
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