TPIC6595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS010A – APRIL 1992 – REVISED OCTOBER 1995 D D D D D D D Low rDS(on) . . . 1.3 Ω Typical Avalanche Energy . . . 75 mJ Eight Power DMOS Transistor Outputs of 250-mA Continuous Current 1.5-A Pulsed Current Per Output Output Clamp Voltage at 45 V Devices Are Cascadable Low Power Consumption DW OR N PACKAGE (TOP VIEW) PGND VCC SER IN DRAIN0 DRAIN1 DRAIN2 DRAIN3 SRCLR G PGND description The TPIC6595 is a monolithic, high-voltage, highcurrent power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium-current or high-voltage loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK) respectively. The storage register transfers data to the output buffer when shiftregister clear (SRCLR) is high. When SRCLR is low, the input shift register is cleared. When output enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. The serial output (SER OUT) allows for cascading of the data from the shift register to additional devices. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 PGND LGND SER OUT DRAIN7 DRAIN6 DRAIN5 DRAIN4 SRCK RCK PGND logic symbol† G RCK SRCLR SRCK SER IN 9 EN3 12 8 13 3 C2 R SRG8 C1 1D 2 4 5 6 7 14 15 16 17 2 18 DRAIN0 DRAIN1 DRAIN2 DRAIN3 DRAIN4 DRAIN5 DRAIN6 DRAIN7 SER OUT † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Outputs are low-side, open-drain DMOS transistors with output ratings of 45 V and 250-mA continuous sink current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high, the DMOS-transistor outputs have sink current capability. Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11, and 20 are internally connected, and each pin must be externally connected to the power system ground in order to minimize parasitic inductance. A single-point connection between pin 19, logic ground (LGND), and pins 1, 10, 11, and 20, power grounds (PGND), must be externally made in a manner that reduces crosstalk between the logic and load circuits. The TPIC6595 is characterized for operation over the operating case temperature range of – 40°C to 125°C. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPIC6595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS010A – APRIL 1992 – REVISED OCTOBER 1995 logic diagram (positive logic) G RCK SRCLR 9 12 4 8 D SRCK 13 D C2 C1 CLR SER IN 5 3 D DRAIN1 D C2 C1 CLR 6 D DRAIN2 D C2 C1 7 CLR DRAIN3 D D C1 C2 CLR 14 D DRAIN4 D C2 C1 CLR 15 D DRAIN5 D C2 C1 16 CLR DRAIN6 D C2 D C1 17 CLR D DRAIN7 D C2 C1 CLR 1, 10, 11, 20 18 2 DRAIN0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SER OUT PGND TPIC6595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS010A – APRIL 1992 – REVISED OCTOBER 1995 schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS VCC DRAIN 45 V Input 25 V 12 V 12 V PGND LGND LGND absolute maximum ratings over recommended operating case temperature range (unless otherwise noted)† Logic supply voltage, VCC (see Note NO TAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Logic input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Power DMOS drain-to-source voltage, VDS (see Note NO TAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 V Continuous source-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Pulsed source-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A Pulsed drain current, each output, all outputs on, IDn, TA = 25°C (see Note NO TAG) . . . . . . . . . . . . 750 mA Continuous drain current, each output, all outputs on, IDn, TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA Peak drain current single output, IDM,TA = 25°C (see Note NO TAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A Single-pulse avalanche energy, EAS (see NO TAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mJ Avalanche current, IAS (see Note NO TAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to LGND and PGND. 2. Each power DMOS source is internally connected to PGND. 3. Pulse duration ≤ 100 µs, duty cycle ≤ 2 % 4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 100 mH, IAS = 1 A (see NO TAG). DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 125°C POWER RATING DW 1125 mW 9.0 mW/°C 225 mW N 1150 mW 9.2 mW/°C 230 mW POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPIC6595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS010A – APRIL 1992 – REVISED OCTOBER 1995 recommended operating conditions over recommended operating temperature range (unless otherwise noted) Logic supply voltage, VCC High-level input voltage, VIH MIN MAX 4.5 5.5 UNIT V 0.85 VCC Low-level input voltage, VIL V 0.15 VCC Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) – 1.8 1.5 V A Setup time, SER IN high before SRCK↑, tsu (see NO TAG) 10 ns Hold time, SER IN high after SRCK↑, th (see NO TAG) 10 ns Pulse duration, tw (see NO TAG) 20 Operating case temperature, TC – 40 ns °C 125 electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted) PARAMETER V(BR)DSX VSD TEST CONDITIONS Drain-source breakdown voltage Source-drain diode forward voltage ID = 1 mA IF = 250 mA, VOH High-level g output voltage, g , SER OUT IOH = – 20 mA, VCC = 4.5 V IOH = – 4 mA, VCC = 4.5 V VOL Low-level output voltage, g , SER OUT IOH = 20 mA, VCC = 4.5 V IOH = 4 mA, VCC = 4.5 V VDS = 15 V V(hys) IIH Input hysteresis IIL ICCL Low-level input current ICC(FRQ) Logic supply current frequency IN Nominal current IDSX Off state drain current Off-state rDS(on) Static drain-source on-state resistance High-level input current Logic supply current VCC = 5.5 V, VCC = 5.5 V, MIN See Note 3 0.85 4.49 4.1 4.3 See Notes 5, 6, and 7 0.1 0.2 0.4 VCC = 4.5 V NO TAG V V V 1 µA –1 µA 15 100 µA 0.6 5 mA 250 See Notes 5 and 6 and Figures 9 and 10 UNIT V 1.3 TC = 125°C VCC = 4.5 V TC = 125°C, 1 0.002 VI = VCC VI = 0 VDS(on) = 0.5 V, IN = ID, TC = 85°C VDS = 40 V ID = 250 mA, VCC = 4.5 V ID = 500 mA, MAX V 4.4 IO = 0, All inputs low fSRCK = 5 MHz, IO = 0, CL = 30 pF, See Figures 1, 2, and 6 VDS = 40 V, ID = 250 mA, TYP 45 mA 0.05 1 0.15 5 1.3 2 2 3.2 1.3 2 TYP MAX µA Ω switching characteristics, VCC = 5 V, TC = 25°C PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low-to-high-level output from G tr tf Rise time, drain output ta trr Reverse-recovery-current rise time Propagation delay time, high-to-low-level output from G Fall time, drain output Reverse-recovery time NOTES: 3. 5. 6. 7. 4 CL = 30 pF,, ID = 250 mA,, See Figures 1 and 2 IF = 250 mA,, di/dt = 20 A/µs, µ , See Notes 5 and 6 and Figure 3 MIN UNIT 650 ns 150 ns 750 ns 425 ns 100 300 ns Pulse duration ≤ 100 µs, duty cycle ≤ 2% Technique should limit TJ – TC to 10°C maximum. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of 0.5 V at TC = 85°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC6595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS010A – APRIL 1992 – REVISED OCTOBER 1995 thermal resistance PARAMETER RθJA TEST CONDITIONS DW package resistance junction-to-ambient junction to ambient Thermal resistance, MIN UNIT 111 All 8 outputs with equal power N package MAX °C/W 108 PARAMETER MEASUREMENT INFORMATION 24 V 5V 7 2 8 SRCLR 12 9 DRAIN SER IN 4 3 2 1 0 5V 0V 5V RL = 95 Ω DUT 3 5 ID VCC 13 SRCK Word Generator (see Note A) 6 SRCK 4 –7, 14 –17 G Output CL = 30 pF (see Note B) RCK 0V 5V 0V 5V SER IN G RCK 0V 5V SRCLR 0V LGND PGND 19 1, 10, 11, 20 24 V DRAIN1 0.5 V VOLTAGE WAVEFORMS TEST CIRCUIT Figure 1. Resistive Load Operation 5V G 5V 50% 50% 0V 24 V tPLH tPHL 2 8 13 Word Generator (see Note A) 3 12 9 V SRCLR CC SRCK DUT Output ID RL = 95 Ω 4 –7, 14 –17 Output 90% 10% G LGND PGND 19 0.5 V tf SWITCHING TIMES CL = 30 pF (see Note B) RCK 10% tr DRAIN SER IN 24 V 90% 5V 50% SRCK 0V tsu 1, 10, 11, 20 th 5V TEST CIRCUIT SER IN 50% 50% 0V tw INPUT SETUP AND HOLD WAVEFORMS Figure 2. Test Circuit, Switching Times, and Voltage Waveforms NOTES: A. Outputs DRAIN 1, 2, 5, and 6 low (PGND), all other DRAIN outputs are at 24 V. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz, ZO = 50 Ω. B. CL includes probe and jig capacitance. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPIC6595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS010A – APRIL 1992 – REVISED OCTOBER 1995 PARAMETER MEASUREMENT INFORMATION TP K DRAIN 0.25 A 2500 µF 250 V Circuit Under Test di/dt = 20 A/µs + 25 V L = 1 mH IF (see Note B) IF – 0 TP A 25% of IRM t2 t1 t3 Driver IRM RG VGG (see Note A) ta 50 Ω trr CURRENT WAVEFORM TEST CIRCUIT NOTES: A. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.25 A, where t1 = 10 µs, t2 = 7 µs, and t3 = 3 µs. B. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the TP A test point. Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-Drain Diode 5V 15 V tw 2 8 13 Word Generator (see Note A) 3 SRCK DRAIN RCK See Note B 4 –7, 14 –17 ID VDS G LGND PGND 19 1, 10, 11, 20 SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT V(BR)DSX = 45 V MIN VDS VOLTAGE AND CURRENT WAVEFORMS NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω. B. Input pulse duration, tw, is increased until peak current IAS = 1 A. Energy test level is defined as EAS = IAS × V(BR)DSX × tav/2 = 75 mJ, where tav = avalanche time. Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms 6 0V IAS = 1 A 100 mH SER IN tav 5V Input ID DUT 12 9 0.11 Ω V SRCLR CC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC6595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS010A – APRIL 1992 – REVISED OCTOBER 1995 TYPICAL CHARACTERISTICS PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE SUPPLY CURRENT vs FREQUENCY 10 3.5 3 4 I CC – Supply Current – mA IAS – Peak Avalanche Current – A TJS = 25°C 2 1 0.4 0.2 VCC = 5 V TJS = – 40°C to 125°C 2.5 2 1.5 1 0.5 0.1 0.1 0.2 0.4 1 2 4 0 0.1 10 1 tav – Time Duration of Avalanche – ms Figure 5 MAXIMUM PEAK DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY 2 VCC = 5 V TA = 25°C d = tw/tperiod = 1 ms/tperiod VCC = 5 V 700 600 500 TA = 25°C 300 TA = 100°C 200 TA = 125°C I D – Maximum Peak Drain Current of Each Output – A I D – Maximum Continuous Drain Current of Each Output – mA 800 100 100 Figure 6 MAXIMUM CONTINUOUS DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY 400 10 f – Frequency – MHz 1.5 d = 5% 1 d = 50% d = 10% 0.5 d = 80% 0 0 6 7 8 0 1 2 3 4 5 N – Number of Outputs Conducting Simultaneously 0 1 2 3 4 5 6 7 8 N – Number of Outputs Conducting Simultaneously Figure 7 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPIC6595 POWER LOGIC 8-BIT SHIFT REGISTER SLIS010A – APRIL 1992 – REVISED OCTOBER 1995 TYPICAL CHARACTERISTICS STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs LOGIC SUPPLY VOLTAGE r DS(on) – Static Drain-Source On-State Resistance – Ω rDS(on) – Static Drain-Source On-State Resistance – Ω STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 4 3.5 VCC = 5 V See Note A 3 TC = 125°C 2.5 2 TC = 25°C 1.5 1 TC = – 40°C 0.5 0 0.25 0.5 0.75 1 1.25 1.5 3 2.5 2 TC = 25°C 1.5 1 TC = – 40°C 0.5 0 3 4 5 Figure 10 Figure 9 SWITCHING TIME vs FREE-AIR TEMPERATURE 700 tr 600 t – Switching Time – ns 6 VCC – Logic Supply Voltage – V ID – Drain Current – A tPLH ID = 250 mA See Note A 500 tf 400 300 200 tPHL 100 – 50 0 50 100 TA – Free-Air Temperature – °C Figure 11 NOTE A: Technique should limit TJ – TC to 10°C maximum. 8 ID = 250 mA See Note A TC = 125°C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 150 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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