SGLS183 − AUGUST 2003 D Qualification in Accordance With D D D D D D D D D AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval ESD Protection Exceeds 1500 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Dual Output Drive Stages in Push-Pull Configuration Current Sense Discharge Transistor to Improve Dynamic Response 130-µA Typical Starting Current 1-mA Typical Run Current Operation to 1 MHz Internal Soft Start † Contact factory for details. Q100 qualification data available on request. D On-Chip Error Amplifier With 2-MHz Gain D D Bandwidth Product On Chip VDD Clamping Output Drive Stages Capable of 500-mA Peak-Source Current, 1-A Peak-Sink Current D PACKAGE (TOP VIEW) COMP FB CS RC 1 8 2 7 3 6 4 5 VDD OUTA OUTB GND PW PACKAGE (TOP VIEW) OUTA VDD COMP FB 1 2 3 4 8 7 6 5 OUTB GND RC CS description The UCC2808A is a family of BiCMOS push-pull, high-speed, low-power, pulse-width modulators. The UCC2808A contains all of the control and drive circuitry required for off-line or dc-to-dc fixed frequency current-mode switching power supplies with minimal external parts count. The UCC2808A dual output drive stages are arranged in a push-pull configuration. Both outputs switch at half the oscillator frequency using a toggle flip-flop. The dead time between the two outputs is typically 60 ns to 200 ns depending on the values of the timing capacitor and resistors, thus limiting each output stage duty cycle to less than 50%. The UCC2808A family offers a variety of package options and choice of undervoltage lockout levels. The family has UVLO thresholds and hysteresis options for off-line and battery powered systems. Thresholds are shown in the ordering information table. The UCC2808A is an enhanced version of the UCC2808 family. The significant difference is that the A versions feature an internal discharge transistor from the CS pin to ground, which is activated each clock cycle during the oscillator dead time. The feature discharges any filter capacitance on the CS pin during each cycle and helps minimize filter capacitor values and current sense delay. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003 Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SGLS183 − AUGUST 2003 ORDERING INFORMATION† TA UVLO Option −40°C to 125°C 12.5 V/8.3 V SOIC (D) −40°C to 125°C ORDERABLE PART NUMBER PACKAGE TOP-SIDE MARKING Tape and reel UCC2808AQDR−1Q1 UCC2808AD-1Q1 TSSOP (PW) Tape and reel UCC2808AQPWR−1Q1‡ 2808A1 SOIC (D) Tape and reel UCC2808AQDR−2Q1 UCC2808AD-2Q1 4.3 V/4.1 V UCC2808AQPWR−2Q1‡ TSSOP (PW) Tape and reel 2808A2 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ Product Preview. block diagram FB COMP CS 2 1 3 22 k Ω OVERCURRENT COMPARATOR PEAK CURRENT COMPARATOR 8 VDD 7 OUTA 6 OUTB 5 GND 14 V 0.75 V 0.5 V 2.0 V 2.2 V VDD OK OSCILLATOR S Q PWM LATCH R 1.2R VDD−1 V Q S S Q Q R R T Q PWM COMPARATOR VDD 0.5 V R SOFT START VOLTAGE REFERENCE SLOPE = 1 V/ms 4 Note: Pinout shown is for SOIC package. TSSOP pinout is different. RC UDG-00097 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SGLS183 − AUGUST 2003 absolute maximum ratings over operating free-air temperature (unless otherwise noted)†} Supply voltage (IDD ≤ 10 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA OUTA/OUTB source current (peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 A OUTA/OUTB sink current (peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 A Analog inputs (FB, CS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD 0.3 V, not to exceed 6 V Power dissipation at TA = 25°C (D package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW Power dissipation at TA = 25°C (PW package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mW Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to150°C Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C Lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. † Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Power Supply Control Data Book (TI Literature Number SLUD003) for thermal limitations and considerations of packages. electrical characteristics, TA = −40°C to 125°C for the UCC2808AQ-x, VDD = 10 V (see Note 6), 1-µF capacitor from VDD to GND, R = 22 kΩ, C = 330 pF TA = TJ, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 175 194 213 kHz 0.44 0.5 0.56 V/V Oscillator Section Oscillator frequency Oscillator amplitude/VDD See Note 1 NOTES: 1. Measured at RC. Signal amplitude tracks VDD. 6. For UCCx808A−1, set VDD above the start threshold before setting at 10 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SGLS183 − AUGUST 2003 electrical characteristics, TA = −40°C to 125°C for the UCC2808AQ-x, VDD = 10 V (see Note 6), 1-µF capacitor from VDD to GND, R = 22 kΩ, C = 330 pF TA = TJ, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 1.95 2 2.05 V 1 µA Error Amplifier Section Input voltage COMP = 2 V Input bias current –1 Open loop voltage gain 60 COMP sink current FB = 2.2 V, COMP = 1 V COMP source current FB = 1.3 V, COMP = 3.5 V 80 dB 0.3 2.5 mA –0.2 –0.5 mA 48 49 PWM Section Maximum duty cycle Measured at OUTA or OUTB Minimum duty cycle COMP = 0 V 50 % 0 % Current Sense Section Gain See Note 2 1.9 Maximum input signal COMP = 5 V See Note 3 CS to output delay COMP = 3.5 V, CS from 0 mV to 600 mV 0.45 CS source current 2.2 2.5 0.5 0.55 V 100 200 ns −200 CS sink current CS = 0.5 V, RC = 5.5 V See Note 7 Over current threshold COMP to CS offset CS = 0 V V/V nA 4 10 0.65 0.75 0.85 mA V 0.35 0.8 1.2 V 0.5 1.1 V Output Section OUT low level I = 100 mA OUT high level I = −50 mA, 0.5 1 V Rise time CL = 1 nF 25 60 ns Fall time CL = 1 nF 25 60 ns 11.5 12.5 13.5 V UCCx808A−2 4.1 4.3 4.5 V UCCx808A−1 7.6 8.3 9 V UCCx808A−2 3.9 4.1 4.3 V UCCx808A−1 3.5 4.2 5.1 V UCCx808A−2 0.1 0.2 0.3 V 3.5 20 ms 130 260 µA 1 2 mA 14 15 V VDD – OUT Undervoltage Lockout Section UCCx808A−1 Start threshold Minimum operating voltage after start Hysteresis See Note 6 Soft Start Section COMP rise time FB = 1.8 V, Rise from 0.5 V to 4 V Overall Section Startup current VDD < start threshold Operating supply current FB = 0 V, CS = 0 V IDD = 10 mA See Note 4 VDD zener shunt voltage 4 DV 13 COMP, 0 ≤ V CS ≤ 0.4 V. DV CS Parameter measured at trip point of latch with FB at 0 V. Start threshold and zener shunt threshold track one another. Does not include current in the external oscillator network. For UCC2808A−1, set VDD above the start threshold before setting at 10 V. The internal current sink on the CS pin is designed to discharge an external filter capacitor. It is not intended to be a dc sink path. NOTES: 2. Gain is defined by: A + 3. 4. 5. 6. 7. See Note 5 and 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SGLS183 − AUGUST 2003 pin assignments COMP: COMP is the output of the error amplifier and the input of the PWM comparator. The error amplifier in the UCC2808A is a true low-output impedance, 2-MHz operational amplifier. As such, the COMP pin can both source and sink current. However, the error amplifier is internally current limited, so that zero duty cycle can be externally forced by pulling COMP to GND. The UCC2808A family features built-in full-cycle soft start. Soft start is implemented as a clamp on the maximum COMP voltage. CS: The input to the PWM, peak current, and overcurrent comparators. The overcurrent comparator is only intended for fault sensing. Exceeding the overcurrent threshold will cause a soft start cycle. An internal MOSFET discharges the current sense filter capacitor to improve dynamic performance of the power converter. FB: The inverting input to the error amplifier. For best stability, keep FB lead length as short as possible and FB stray capacitance as small as possible. GND: Reference ground and power ground for all functions. Due to high currents, and high frequency operation of the UCC2808A, a low impedance circuit board ground plane is highly recommended. OUTA and OUTB: Alternating high current output stages. Both stages are capable of driving the gate of a power MOSFET. Each stage is capable of 500-mA peak-source current, and 1-A peak-sink current. The output stages switch at half the oscillator frequency, in a push-pull configuration. When the voltage on the RC pin is rising, one of the two outputs is high, but during fall time, both outputs are off. This dead time between the two outputs, along with a slower output rise time than fall time, insures that the two outputs can not be on at the same time. This dead time is typically 60 ns to 200 ns and depends upon the values of the timing capacitor and resistor. The high-current-output drivers consist of MOSFET output devices, which switch from VDD to GND. Each output stage also provides a very low impedance to overshoot and undershoot. This means that in many cases, external-schottky-clamp diodes are not required. RC: The oscillator programming pin. The UCC2808A’s oscillator tracks VDD and GND internally, so that variations in power supply rails minimally affect frequency stability. Figure 1 shows the oscillator block diagram. Only two components are required to program the oscillator: a resistor (tied to the VDD and RC), and a capacitor (tied to the RC and GND). The approximate oscillator frequency is determined by the simple formula: f OSCILLATOR + 1.41 RC where frequency is in Hz, resistance in Ohms, and capacitance in Farads. The recommended range of timing resistors is between 10 kΩ and 200 kΩ and range of timing capacitors is between 100 pF and 1000 pF. Timing resistors less than 10 kΩ should be avoided. For best performance, keep the timing capacitor lead to GND as short as possible, the timing resistor lead from VDD as short as possible, and the leads between timing components and RC as short as possible. Separate ground and VDD traces to the external timing network are encouraged. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SGLS183 − AUGUST 2003 pin assignments (continued) RC 4 FREQUENCY = VDD 2 S 1.41 RC (APPROXIMATE FREQUENCY) Q OSCILLATOR OUTPUT R 0.2 V UDG-00095 Figure 1. Block Diagram for Oscillator NOTE A: The oscillator generates a sawtooth waveform on RC. During the RC rise time, the output stages alternate on time, but both stages are off during the RC fall time. The output stages switch a 1/2 the oscillator frequency, with ensured duty cycle of < 50% for both outputs. VDD: The power input connection for this device. Although quiescent VDD current is very low, total supply current will be higher, depending on OUTA and OUTB current, and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from: I OUT + Qg F, where F is frequency To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible along with an electrolytic capacitor. A 1-µF decoupling capacitor is recommended. APPLICATION INFORMATION A 200-kHz push-pull application circuit with a full-wave rectifier is shown in Figure 2. The output, VO, provides 5 V at 50 W maximum and is electrically isolated from the input. Since the UCC2808A is a peak-current-mode controller the 2N2907 emitter following amplifier (buffers the CT waveform) provides slope compensation which is necessary for duty ratios greater than 50%. Capacitor decoupling is very important with a single ground IC controller, and a 1 µF is suggested as close to the IC as possible. The controller supply is a series RC for start-up, paralleled with a bias winding on the output inductor used in steady state operation. Isolation is provided by an optocoupler with regulation done on the secondary side using the TL431 adjustable precision shunt regulator. Small signal compensation with tight voltage regulation is achieved using this part on the secondary side. Many choices exist for the output inductor depending on cost, volume, and mechanicall strength. Several design options are iron powder, molypermalloy (MPP), or a ferrite core with an air gap as shown here. The main power transformer has a Magnetics Inc. ER28 size core made of P material for efficient operation at this frequency and temperature. The input voltage may range from 36 V dc to 72 V dc. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 − VIN 36 V TO 72 V + 10 µF 4700 µF POST OFFICE BOX 655303 2.80 kΩ 0.1 µF 0.47 µF • DALLAS, TEXAS 75265 86.6 kΩ 330 pF 2 kΩ 2.2 Ω 51 kΩ 1/4 W CURRENT SENSE 0.2 Ω IRF640 1000 pF 2K12907 IRF640 BYV 28−200 1000 pF 6 2 CS 3 UCC2808AD−1 7 2.2 Ω 330 pF 20 kΩ 432 Ω 4.99 kΩ RC PRIMARY GROUND 4.99 kΩ RC 4 5 OUTA OUTB GND 62 Ω COMP FB 1 8 VDD 62 Ω 20 kΩ BYV 28−200 1 mH 10 Ω 12 NP1 NP2 2 1 6 H11A1 U3 3 240 Ω 0.01 µF 1 kV EF25 7µH 5 4 DF02SGICT NS2 NS1 32CTQ030 0.1 µF ER28 8:2 0.1 µF 680 µF 3 2 1 TL431 470 pF 4700 pF 20 kΩ COMP LOOP A LOOP B 0.01 µF 19.1 kΩ 19.1 kΩ 200 Ω − VO 5 V 50 W + SGLS183 − AUGUST 2003 APPLICATION INFORMATION UDG-00096 Figure 2. Typical Application Diagram: 48-V In, 5-V, 50-W Output 7 SGLS183 − AUGUST 2003 TYPICAL CHARACTERISTICS IDD vs OSCILLATOR FREQUENCY OSCILLATOR FREQUENCY vs EXTERNAL RC VALUES COMP TO CS OFFSET vs TEMPERATURE 14 1000 1.2 C = 100 pF 12 VDD = 10 V, t = 25 5C 1.0 C = 330 pF 100 C = 1000 pF 10 8 6 C = 820 pF 4 C = 560 pF IDD without load 2 50 100 150 0.6 0.4 0 0 200 200 400 RT − Timing Resistor − k Ω 600 800 1000 −55 1200 −35 −15 Oscillator Frequency − kHz Figure 3 Figure 4 ERROR AMPLIFIER GAIN AND PHASE RESPONSE vs FREQUENCY 140 70 120 60 Phase 50 100 40 80 30 60 20 40 Phase Margin - Degrees 160 65 85 105 125 400 C = 1000 pF VDD = 5 V 350 250 300 Dead Time - ns 80 45 DEAD TIME vs TEMPERATURE 300 180 25 Figure 5 OUTPUT DEAD TIME vs EXTERNAL RC VALUES 90 5 Temperature - °C Dead Time - ns 0 0.8 0.2 0 1 Gain dB COMP - CS Offset - V IDD with 1 nF load 10 IDD -mA Frequency - kHz C = 220 pF C = 560 pF C = 820 pF 200 C = 330 pF C = 220 pF 150 VDD = 7.5 V 250 200 VDD = 10 V 150 100 10 100 50 20 Gain C = 100 pF 0 0 1 100 10000 0 50 1000000 50 100 150 250 200 RT − Timing Resistor − k Ω Frequency − Hz Figure 6 Figure 7 120 300 100 250 VDD = 5 V Ohms Ohms VDD = 5 V 80 200 VDD = 7.5 V 150 60 VDD = 7.5 V 40 100 VDD = 10 V VDD = 10 V 20 50 0 0 −100 −50 0 50 Temperature - °C Figure 9 8 100 150 −100 −50 0 50 100 150 Temperature - °C Figure 10 POST OFFICE BOX 655303 −50 0 • DALLAS, TEXAS 75265 50 Temperature - °C Figure 8 CS RDS(on) vs TEMPERATURE RC RDS(on) vs TEMPERATURE −100 100 150 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty UCC2808AQDR-1Q1 ACTIVE SOIC D 8 2500 TBD Call TI Level-1-220C-UNLIM UCC2808AQDR-2Q1 ACTIVE SOIC D 8 2500 TBD Call TI Level-1-220C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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