A29L800A Series 1M X 8 Bit / 512K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory Document Title 1M X 8 Bit / 512K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory Revision History Rev. History Issue Date 0.0 Initial issue September 27, 2004 1.0 Change voltage range from 2.7V~3.6V to 3.0V~3.6V January 10, 2005 Remark Preliminary Final Final version release 1.1 Change voltage range from 3.0V~3.6V back to 2.7V~3.6V June 24, 2005 Add –70U series products (June, 2005, Version 1.1) AMIC Technology, Corp. A29L800A Series 1M X 8 Bit / 512K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory Features Single power supply operation - Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications Access times: - 70/90 (max.) Current: - 9 mA typical active read current - 20 mA typical program/erase current - 200 nA typical CMOS standby - 200 nA Automatic Sleep Mode current Flexible sector architecture - 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX15 sectors - 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX15 sectors - Any combination of sectors can be erased - Supports full chip erase - Sector protection: A hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector Extended operating temperature range: -40°C ~ +85°C for U series; -25°C ~ +85°C for – I series Unlock Bypass Program Command - Reduces overall programming time when issuing multiple program command sequence Top or bottom boot block configurations available Embedded Algorithms - Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors - Embedded Program algorithm automatically writes and verifies data at specified addresses Typical 100,000 program/erase cycles per sector 20-year data retention at 125°C - Reliable operation for the life of the system Compatible with JEDEC-standards - Pinout and software compatible with single-power-supply Flash memory standard - Superior inadvertent write protection Data Polling and toggle bits - Provides a software method of detecting completion of program or erase operations Ready / BUSY pin (RY / BY ) - Provides a hardware method of detecting completion of program or erase operations (not available on 44-pin SOP) Erase Suspend/Erase Resume - Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation Hardware reset pin ( RESET ) - Hardware method to reset the device to reading array data Package options - 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA General Description The A29L800A is an 8Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes of 8 bits or 524,288 words of 16 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16 bits of data appear on I/O0~I/O15. The A29L800A is offered in 48-ball TFBGA, 44-pin SOP and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29L800A can also be programmed in standard EPROM programmers. The A29L800A has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29L800A has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29L800A also offers the ability to program in the Erase Suspend mode. The standard A29L800A offers access times of 70 and 90ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable ( CE ), write enable ( WE ) and output enable ( OE ) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. (June, 2005, Version 1.1) 1 The A29L800A is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin. Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. The host system can detect whether a program or erase operation is complete by observing the RY / BY pin, or by reading the I/O7 ( Data Polling) and I/O6 (toggle) status bits. AMIC Technology, Corp. A29L800A Series After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29L800A is fully erased when shipped from the factory. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved. (June, 2005, Version 1.1) 2 The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMIC Technology, Corp. A29L800A Series Pin Configurations SOP TSOP (I) RESET 1 44 2 43 WE A17 3 42 A8 A7 4 41 A9 A6 5 40 A10 A5 6 39 A11 A4 7 38 A12 A3 8 37 A13 A2 9 36 A14 A1 10 35 A15 A0 11 34 A16 A29L800A NC A18 CE 12 33 BYTE VSS 13 32 VSS OE 14 31 I/O15 (A-1) I/O0 15 30 I/O7 I/O8 16 29 I/O14 I/O1 17 28 I/O6 I/O9 18 27 I/O13 I/O2 19 26 I/O5 I/O10 20 25 I/O12 I/O3 21 24 I/O4 I/O11 22 23 VCC A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET NC NC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A29L800AV A16 BYTE VSS I/O15 (A-1) I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE VSS CE A0 TFBGA TFBGA Top View, Balls Facing Down A6 B6 C6 D6 E6 F6 G6 H6 A13 A12 A14 A15 A16 BYTE I/O15(A-1) VSS A5 B5 C5 D5 E5 F5 G5 H5 A9 A8 A10 A11 I/O7 I/O14 I/O13 I/O6 A4 B4 C4 D4 E4 F4 G4 H4 WE RESET NC NC I/O5 I/O12 VCC I/O4 A3 B3 C3 D3 E3 F3 G3 H3 NC A18 NC I/O2 I/O10 I/O11 I/O3 A2 B2 C2 D2 E2 F2 G2 H2 A7 A17 A6 A5 I/O0 I/O8 I/O9 I/O1 A1 B1 C1 D1 E1 F1 G1 H1 A3 A4 A2 A1 A0 CE OE VSS RY/BY (June, 2005, Version 1.1) 3 AMIC Technology, Corp. A29L800A Series Block Diagram RY/BY I/O 0 - I/O 15 (A-1) VCC VSS Sector Switches Input/Output Buffers Erase Voltage Generator RESET State Control WE BYTE PGM Voltage Generator Command Register Chip Enable Output Enable Logic CE OE VCC Detector Address Latch STB Timer A0-A18 STB Data Latch Y-Decoder Y-Gating X-decoder Cell Matrix Pin Descriptions Pin No. Description A0 - A18 Address Inputs I/O0 - I/O14 Data Inputs/Outputs I/O15 I/O15 (A-1) A-1 LSB Address Input, Byte Mode CE Chip Enable WE Write Enable OE Output Enable RESET Hardware Reset BYTE Selects Byte Mode or Word Mode RY/ BY Ready/ BUSY - Output VSS Ground VCC Power Supply NC (June, 2005, Version 1.1) Data Input/Output, Word Mode Pin not connected internally 4 AMIC Technology, Corp. A29L800A Series Absolute Maximum Ratings* *Comments Storage Temperature Plastic Packages. . . . . .-65°C to + 150°C Ambient Temperature with Power Applied . . . -55°C to + 125°C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.0V A9, OE & RESET (Note 2) . . . . . . . . . . . . . . . . -0.5 to +12.5V All other pins (Note 1) . . . . . . . . . .. . . .. . . -0.5V to VCC + 0.5V Output Short Circuit Current (Note 3) . . . . . . . . . . . . . 200mA Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Notes: Operating Ranges 1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0V for periods of up to 20ns. Maximum DC voltage on input and I/O pins is VCC +0.5V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0V for periods up to 20ns. 2. Minimum DC input voltage on A9, OE and RESET is 0.5V. During voltage transitions, A9, OE and RESET may overshoot VSS to -2.0V for periods of up to 20ns. Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns. 3. No more than one output is shorted at a time. Duration of the short circuit should not be greater than one second. Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . .. . . .. . . . . 0°C to +70°C Extended Range Devices Ambient Temperature (TA) For – I series . . . . . . . . . . . . . . . . . .. . . . . . . . . -25°C to + 85°C For – U series . . . . . . . . . . . . . . . . . . .. . . . . . . -40°C to + 85°C VCC Supply Voltages VCC for all devices . . . . . . . . . . . . . . . . . . . . . . +2.7V to +3.6V Operating ranges define those limits between which the functionally of the device is guaranteed. Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. A29L800A Device Bus Operations Operation CE OE WE RESET A0 – A18 (Note 1) I/O0 - I/O7 I/O8 - I/O15 BYTE =VIH BYTE =VIL Read L L H H AIN DOUT DOUT I/O8~I/O14=High-Z Write L H L H AIN DIN DIN I/O15=A-1 CMOS Standby VCC ± 0.3 V X X VCC ± 0.3 V X High-Z High-Z High-Z Output Disable L H H H X High-Z High-Z High-Z Hardware Reset X X X L X High-Z High-Z High-Z Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In Notes: 1. Addresses are A18:A0 in word mode ( BYTE =VIH), A18: A-1 in byte mode ( BYTE =VIL). 2. See the “Sector Protection/Unprotection” section and Temporary Sector Unprotect for more information. (June, 2005, Version 1.1) 5 AMIC Technology, Corp. A29L800A Series Characteristics" section contains timing specification tables and timing diagrams for write operations. Word/Byte Configuration The BYTE pin determines whether the I/O pins I/O15-I/O0 operate in the byte or word configuration. If the BYTE pin is set at logic ”1”, the device is in word configuration, I/O15-I/O0 are active and controlled by CE and OE . If the BYTE pin is set at logic “0”, the device is in byte configuration, and only I/O0-I/O7 are active and controlled by CE and OE . I/O8-I/O14 are tri-stated, and I/O15 pin is used as an input for the LSB(A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE and OE pins to VIL. CE is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at VIH all the time during read operation. The BYTE pin determines whether the device outputs array data in words and bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms, lCC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE and CE to VIL, and OE to VIH. For program operations, the BYTE pin determines whether the device accepts program data in bytes or words, Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word / Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequence. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address range that each sector occupies. A "sector address" consists of the address inputs required to uniquely select a sector. See the "Command Definitions" section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on I/O7 - I/O0. Standard read cycle timings apply in this mode. Refer to the "Autoselect Mode" and "Autoselect Command Sequence" sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC (June, 2005, Version 1.1) 6 Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on I/O7 I/O0. Standard read cycle timings and ICC read specifications apply. Refer to "Write Operation Status" for more information, and to each AC Characteristics section for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE input. The device enters the CMOS standby mode when the CE & RESET pins are both held at VCC ± 0.3V. (Note that this is a more restricted voltage range than VIH.) If CE and RESET are held at VIH, but not within VCC ± 0.3V, the device will be in the standby mode, but the standby current will be greater. The device requires the standard access time (tCE) before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 and ICC4 in the DC Characteristics tables represent the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC +30ns. The automatic sleep mode is independent of the CE , WE and OE control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification. Output Disable Mode When the OE input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. RESET : Hardware Reset Pin The RESET pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET pin low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET pulse. When RESET is held at VSS ± 0.3V, the device draws CMOS standby current (ICC4). If RESET is held at VIL but not within VSS ± 0.3V, the standby current will be greater. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling AMIC Technology, Corp. A29L800A Series the system to read the boot-up firmware from the Flash memory. If RESET is asserted during a program or erase operation, the RY/ BY pin remains a “0” (busy) until the internal reset operation is complete, which requires a time tREADY (during Embedded Algorithms). The system can thus monitor RY/ BY to determine whether the reset operation is complete. If RESET is asserted when a program or erase operation is not executing (RY/ BY pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET pin return to VIH. Refer to the AC Characteristics tables for RESET parameters and diagram. Table 2. A29L800A Top Boot Block Sector Address Table Sector A18 A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords) Address Range (in hexadecimal) Byte Mode (x 8) Word Mode (x16) SA0 0 0 0 0 X X X 64/32 00000h - 0FFFFh 00000h - 07FFFh SA1 0 0 0 1 X X X 64/32 10000h - 1FFFFh 08000h - 0FFFFh SA2 0 0 1 0 X X X 64/32 20000h - 2FFFFh 10000h - 17FFFh SA3 0 0 1 1 X X X 64/32 30000h - 3FFFFh 18000h - 1FFFFh SA4 0 1 0 0 X X X 64/32 40000h - 4FFFFh 20000h - 27FFFh SA5 0 1 0 1 X X X 64/32 50000h - 5FFFFh 28000h - 2FFFFh SA6 0 1 1 0 X X X 64/32 60000h - 6FFFFh 30000h - 37FFFh SA7 0 1 1 1 X X X 64/32 70000h - 7FFFFh 38000h - 3FFFFh SA8 1 0 0 0 X X X 64/32 80000h - 8FFFFh 40000h - 47FFFh SA9 1 0 0 1 X X X 64/32 90000h - 9FFFFh 48000h - 4FFFFh SA10 1 0 1 0 X X X 64/32 A0000h - AFFFFh 50000h - 57FFFh SA11 1 0 1 1 X X X 64/32 B0000h - BFFFFh 58000h - 5FFFFh SA12 1 1 0 0 X X X 64/32 C0000h - CFFFFh 60000h - 67FFFh SA13 1 1 0 1 X X X 64/32 D0000h - DFFFFh 68000h - 6FFFFh SA14 1 1 1 0 X X X 64/32 E0000h - EFFFFh 70000h - 77FFFh SA15 1 1 1 1 0 X X 32/16 F0000h - F7FFFh 78000h - 7BFFFh SA16 1 1 1 1 1 0 0 8/4 F8000h - F9FFFh 7C000h - 7CFFFh SA17 1 1 1 1 1 0 1 8/4 FA000h - FBFFFh 7D000h - 7DFFFh SA18 1 1 1 1 1 1 X 16/8 FC000h - FFFFFh 7E000h - 7FFFFh Note: Address range is A18 : A-1 in byte mode and A18 : A0 in word mode. See “Word/Byte Configuration” section. (June, 2005, Version 1.1) 7 AMIC Technology, Corp. A29L800A Series Table 3. A29L800A Bottom Boot Block Sector Address Table Sector A18 A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords) Address Range (in hexadecimal) Byte Mode (x 8) Word Mode (x16) SA0 0 0 0 0 0 0 X 16/8 00000h - 03FFFh 00000 - 01FFF SA1 0 0 0 0 0 1 0 8/4 04000h - 05FFFh 02000 - 02FFF SA2 0 0 0 0 0 1 1 8/4 06000h - 07FFFh 03000 - 03FFF SA3 0 0 0 0 1 X X 32/16 08000h - 0FFFFh 04000 - 07FFF SA4 0 0 0 1 X X X 64/32 10000h - 1FFFFh 08000 - 0FFFF SA5 0 0 1 0 X X X 64/32 20000h – 2FFFFh 10000 - 17FFF SA6 0 0 1 1 X X X 64/32 30000h - 3FFFFh 18000 - 1FFFF SA7 0 1 0 0 X X X 64/32 40000h - 4FFFFh 20000 - 27FFF SA8 0 1 0 1 X X X 64/32 50000h - 5FFFFh 28000 - 2FFFF SA9 0 1 1 0 X X X 64/32 60000h - 6FFFFh 30000 - 37FFF SA10 0 1 1 1 X X X 64/32 70000h - 7FFFFh 38000 - 3FFFF SA11 1 0 0 0 X X X 64/32 80000h - 8FFFFh 40000 - 47FFF SA12 1 0 0 1 X X X 64/32 90000h - 9FFFFh 48000 - 4FFFF SA13 1 0 1 0 X X X 64/32 A0000h - AFFFFh 50000 - 57FFF SA14 1 0 1 1 X X X 64/32 B0000h - BFFFFh 58000 - 5FFFF SA15 1 1 0 0 X X X 64/32 C0000h - CFFFFh 60000 - 67FFF SA16 1 1 0 1 X X X 64/32 D0000h - DFFFFh 68000 - 6FFFF SA17 1 1 1 0 X X X 64/32 E0000h - EFFFFh 70000 - 77FFF SA18 1 1 1 1 X X X 64/32 F0000h - FFFFFh 78000 - 7FFFF Note: Address range is A18 : A-1 in byte mode and A18 : A0 in word mode. See “Word/Byte Configuration” section. (June, 2005, Version 1.1) 8 AMIC Technology, Corp. A29L800A Series Autoselect Mode The autoselect mode provides manufacturer and device identification, through identifier codes output on I/O7 - I/O0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on I/O7 I/O0.To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See "Command Definitions" for details on using the autoselect mode. Table 4. A29L800A Autoselect Codes (High Voltage Method) Description Mode Manufacturer ID: AMIC Device ID: A29L800A (Top Boot Block) Word Device ID: A29L800A (Bottom Boot Block) Word Byte CE OE WE A18 to A12 A11 to A10 A9 A8 to A7 A6 A5 to A2 A1 A0 I/O8 to I/O15 I/O7 to I/O0 L L H X X VID X L X L L X 37h B3h 1Ah X 1Ah B3h 9Bh X 9Bh X 7Fh L L H X X VID X L X L H L L H X X VID X L X L H Byte Continuation ID L L H X X VID X L X H H L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care. Note: The autoselect codes may also be accessed in-system via command sequences. Hardware Data Protection Logical Inhibit The requirement of command unlocking sequence for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up transitions, or from system noise. The device is powered up to read array data to avoid accidentally writing data to the array. Write cycles are inhibited by holding any one of OE =VIL, CE = VIH or WE = VIH. To initiate a write cycle, CE and WE Write Pulse "Glitch" Protection must be a logical zero while OE is a logical one. Power-Up Write Inhibit If WE = CE = VIL and OE = VIH during power up, the device does not accept commands on the rising edge of WE . The internal state machine is automatically reset to reading array data on the initial power-up. Noise pulses of less than 5ns (typical) on OE , CE or WE do not initiate a write cycle. (June, 2005, Version 1.1) 9 AMIC Technology, Corp. A29L800A Series Command Definitions Autoselect Command Sequence Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE or CE , whichever happens later. All data is latched on the rising edge of WE or CE , whichever happens first. Refer to the appropriate timing diagrams in the "AC Characteristics" section. The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code and another read cycle at XX03h retrieves the continuation code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if I/O5 goes high, or while in the autoselect mode. See the "Reset Command" section, next. See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If I/O5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). (June, 2005, Version 1.1) 10 Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE pin. Programming is a fourbus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell margin. Table 5 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are longer latched. The system can determine the status of the program operation by using I/O7, I/O6, or RY/ BY . See “White Operation Status” for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set I/O5 to “1”, or cause the Data Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”. AMIC Technology, Corp. A29L800A Series Addresses are don’t care for both cycle. The device returns to reading array data. Figure 1 illustrates the algorithm for the program operation. See the Erase/Program Operations in “AC Characteristics” for parameters, and to Program Operation Timings for timing diagrams. START Write Program Command Sequence Embedded Program algorithm in progress Chip Erase Command Sequence Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. The system can determine the status of the erase operation by using I/O7, I/O6, or I/O2. See "Write Operation Status" for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 2 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms. Data Poll from System Verify Data ? No Yes Increment Address Last Address ? Yes Sector Erase Command Sequence Programming Completed Note : See the appropriate Command Definitions table for program command sequence. Figure 1. Program Operation Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 5 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the twocycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. (June, 2005, Version 1.1) 11 Sector erase is a six-bus-cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50µs begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50µs, the system need not monitor I/O3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor I/O3 to determine if the sector erase timer has timed out. (See the " I/O3: Sector Erase Timer" AMIC Technology, Corp. A29L800A Series section.) The time-out begins from the rising edge of the final WE pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using I/O7, I/O6, or I/O2. Refer to "Write Operation Status" for information on these status bits. Figure 2 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. The system must write the Erase Resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are "don't cares" when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on I/O7 - I/O0. The system can use I/O7, or I/O6 and I/O2 together, to determine if a sector is actively erasing or is erase-suspended. See "Write Operation Status" for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the I/O7 or I/O6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. (June, 2005, Version 1.1) 12 START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh ? Yes Erasure Completed Note : 1. See the appropriate Command Definitions table for erase command sequences. 2. See "I/O3 : Sector Erase Timer" for more information. Figure 2. Erase Operation AMIC Technology, Corp. A29L800A Series Cycles Table 5. A29L800A Command Definitions Command Sequence (Note 1) Bus Cycles (Notes 2 - 5) First Addr Data Read (Note 6) 1 RA RD Reset (Note 7) 1 XXX F0 Word Autoselect (Note 8) Manufacturer ID Device ID, Top Boot Block Device ID, Bottom Boot Block Continuation ID Byte 4 Word Byte 4 Word 4 4 Byte Word Program Byte 4 Word Byte 3 Unlock Bypass Program (Note 10) 2 Unlock Bypass Unlock Bypass Reset (Note 11) 2 Word Chip Erase Byte 6 Word Sector Erase Byte AAA 555 AA AA AAA Word Byte 555 6 555 2AA 555 2AA AA 2AA 2AA AAA 555 555 2AA AA AAA 555 AAA AA XXX A0 555 2AA 555 PA XXX 90 XXX 555 2AA AAA 555 Erase Suspend (Note 12) 1 AAA XXX Erase Resume (Note 13) 1 XXX AAA 555 55 AA AA B0 30 555 2AA 555 90 90 AAA 555 55 555 AA Third Fourth Addr Data Addr Data 555 55 555 AAA 555 Second Addr Data 90 AAA 555 55 90 555 AAA 555 AAA 55 37 X01 B31A X02 1A X01 B39B X02 9B X03 Sixth Addr Data 7F X06 AAA 55 X00 Fifth Addr Data A0 PA PD 20 PD 00 555 55 AAA 555 55 AAA 80 80 555 AAA 555 AAA AA AA 2AA 555 2AA 555 55 55 555 AAA SA 10 30 Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18 - A12 select a unique sector. Note: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operation. 4. Data bits I/O15~I/O8 are don’t care for unlock and command cycles. 5. Address bits A18 - A11 are don't cares for unlock and command cycles, unless SA or PA required. 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high (while the device is providing status data). 8. The fourth cycle of the autoselect command sequence is a read cycle. 9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information. 10. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. 12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. 13. The Erase Resume command is valid only during the Erase Suspend mode. (June, 2005, Version 1.1) 13 AMIC Technology, Corp. A29L800A Series Write Operation Status Several bits, I/O2, I/O3, I/O5, I/O6, I/O7, RY/ BY are provided in the A29L800A to determine the status of a write operation. Table 6 and the following subsections describe the functions of these status bits. I/O7, I/O6 and RY/ BY each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. START Read I/O7-I/O0 Address = VA I/O7: Data Polling The Data Polling bit, I/O7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data Polling is valid after the rising edge of the final WE pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on I/O7 the complement of the datum programmed to I/O7. This I/O7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to I/O7. The system must provide the program address to read valid status information on I/O7. If a program address falls within a protected sector, Data Polling on I/O7 is active for approximately 2µs, then the device returns to reading array data. During the Embedded Erase algorithm, Data Polling produces a "0" on I/O7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data Polling produces a "1" on I/O7.This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to "1"; prior to this, the device outputs the "complement," or "0." The system must provide an address within any of the sectors selected for erasure to read valid status information on I/O7. When the system detects I/O7 has changed from the complement to true data, it can read valid data at I/O7 - I/O0 on the following read cycles. This is because I/O7 may change asynchronously with I/O0 - I/O6 while Output Enable ( OE ) is asserted low. The Data Polling Timings (During Embedded Algorithms) in the "AC Characteristics" section illustrates this. Table 6 shows the outputs for Data Polling on I/O7. Figure 3 Yes I/O7 = Data ? No No I/O5 = 1? Yes Read I/O7 - I/O0 Address = VA Yes I/O7 = Data ? No FAIL PASS shows the Data Polling algorithm. Note : 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. I/O7 should be rechecked even if I/O5 = "1" because I/O7 may change simultaneously with I/O5. Figure 3. Data Polling Algorithm (June, 2005, Version 1.1) 14 AMIC Technology, Corp. A29L800A Series RY/ BY : Read/ Busy The RY/ BY is a dedicated, open-drain output pin that indicates whether an Embedded algorithm is in progress or complete. The RY/ BY status is valid after the rising edge of the final WE pulse in the command sequence. Since RY/ BY is an opendrain output, several RY/ BY pins can be tied together in parallel with a pull-up resistor to VCC. (The RY/ BY pin is not available on the 44-pin SOP package) If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 6 shows the outputs for RY/ BY . Refer to “ RESET Timings”, “Timing Waveforms for Program Operation” and “Timing Waveforms for Chip/Sector Erase Operation” for more information. I/O6: Toggle Bit I Toggle Bit I on I/O6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE pulse in the command sequence (prior to the program or erase operation), and during the sector erase timeout. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause I/O6 to toggle. (The system may use either OE or CE to control the read cycles.) When the operation is complete, I/O6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, I/O6 toggles for approximately 100µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use I/O6 and I/O2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), I/O6 toggles. When the device enters the Erase Suspend mode, I/O6 stops toggling. However, the system must also use I/O2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use I/O7 (see the subsection on " I/O7 : Data Polling"). I/O6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. The Write Operation Status table shows the outputs for Toggle Bit I on I/O6. Refer to Figure 4 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the "AC Characteristics" section for the timing diagram. The I/O2 vs. I/O6 figure shows the differences between I/O2 and I/O6 in graphical form. See also the subsection on " I/O2: Toggle Bit II". I/O2: Toggle Bit II use either OE or CE to control the read cycles.) But I/O2 cannot distinguish whether the sector is actively erasing or is erase-suspended. I/O6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for I/O2 and I/O6. Figure 4 shows the toggle bit algorithm in flowchart form, and the section " I/O2: Toggle Bit II" explains the algorithm. See also the " I/O6: Toggle Bit I" subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The I/O2 vs. I/O6 figure shows the differences between I/O2 and I/O6 in graphical form. Reading Toggle Bits I/O6, I/O2 Refer to Figure 4 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read I/O7 - I/O0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on I/O7 - I/O0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of I/O5 is high (see the section on I/O5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as I/O5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and I/O5 has not gone high. The system may continue to monitor the toggle bit and I/O5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 4). I/O5: Exceeded Timing Limits I/O5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions I/O5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. The I/O5 failure condition may appear if the system tries to program a "1 "to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, I/O5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data. The "Toggle Bit II" on I/O2, when used with I/O6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE pulse in the command sequence. I/O2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may (June, 2005, Version 1.1) 15 AMIC Technology, Corp. A29L800A Series I/O3: Sector Erase Timer After writing a sector erase command sequence, the system may read I/O3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, I/O3 switches from "0" to "1." The system may ignore I/O3 if the system can guarantee that the time between additional sector erase commands will always be less than 50µs. See also the "Sector Erase Command Sequence" section. After the sector erase command sequence is written, the system should read the status on I/O7 ( Data Polling) or I/O6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read I/O3. If I/O3 is "1", the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If I/O3 is "0", the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of I/O3 prior to and following each subsequent sector erase command. If I/O3 is high on the second status check, the last command might not have been accepted. Table 6 shows the outputs for I/O3. START Read I/O7-I/O0 Read I/O7-I/O0 Toggle Bit = Toggle ? (Note 1) No Yes No I/O5 = 1? Yes Read I/O7 - I/O0 Twice Toggle Bit = Toggle ? (Notes 1,2) No Yes Program/Erase Operation Not Commplete, Write Reset Command Program/Erase Operation Complete Notes : 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as I/O5 changes to "1". See text. Figure 4. Toggle Bit Algorithm (June, 2005, Version 1.1) 16 AMIC Technology, Corp. A29L800A Series Table 6. Write Operation Status I/O7 Operation I/O6 (Note 1) Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program I/O5 I/O3 (Note 2) I/O2 RY/ BY (Note 1) I/O7 Toggle 0 N/A No toggle 0 0 Toggle 0 1 Toggle 0 1 No toggle 0 N/A Toggle 1 Data Data Data Data Data 1 I/O7 Toggle 0 N/A N/A 0 Notes: 1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “I/O5: Exceeded Timing Limits” for more information. Maximum Negative Input Overshoot 20ns 20ns +0.8V -0.5V -2.0V 20ns Maximum Positive Input Overshoot 20ns VCC+2.0V VCC+0.5V 2.0V 20ns (June, 2005, Version 1.1) 20ns 17 AMIC Technology, Corp. A29L800A Series DC Characteristics CMOS Compatible (TA=0°C to 70°C or -40°C to +85°C for –U, -25°C to + 85°C for –I) Parameter Symbol Parameter Description Test Description Min. Typ. Max. Unit µA µA µA ILI Input Load Current VIN = VSS to VCC. VCC = VCC Max ILIT ILO A9 Input Load Current Output Leakage Current VCC = VCC Max, A9 =12.5V ±1.0 35 VOUT = VSS to VCC. VCC = VCC Max ±1.0 5 MHz 9 16 1 MHz 2 4 CE = VIL, OE = VIH 5 MHz 9 16 Word Mode 1 MHz 2 4 CE = VIL, OE =VIH 20 30 mA CE = VIH, RESET = VCC ± 0.3V 0.2 5 µA RESET = VSS ± 0.3V 0.2 5 µA VIH = VCC ± 0.3V; VIL = VSS ± 0.3V 0.2 5 µA -0.5 0.8 V 0.7 x VCC VCC + 0.3 V 11.5 12.5 V 0.45 V CE = VIL, OE = VIH Byte Mode ICC1 ICC2 ICC3 ICC4 ICC5 VIL VIH VID VOL VOH1 VOH2 VCC Active Read Current (Notes 1, 2) VCC Active Write (Program/Erase) Current (Notes 2, 3, 4) VCC Standby Current (Note 2) VCC Standby Current During Reset (Note 2) Automatic Sleep Mode (Note 2, 4, 5) Input Low Level Input High Level Voltage for Autoselect and Temporary Unprotect Sector Output Low Voltage Output High Voltage VCC = 3.3 V IOL = 4.0mA, VCC = VCC Min IOH = -2.0 mA, VCC = VCC Min IOH = -100 µA, VCC = VCC Min 0.85 x VCC VCC - 0.4 mA V V Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE at VIH. Typical VCC is 3.0V. 2. Maximum ICC specifications are tested with VCC = VCC max. 3. ICC active while Embedded Algorithm (program or erase) is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns. Typical sleep mode current is 200nA. 5. Not 100% tested. (June, 2005, Version 1.1) 18 AMIC Technology, Corp. A29L800A Series DC Characteristics (continued) Zero Power Flash Supply Current in mA 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 Time in ns Note: Addresses are switching at 1MHz ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 10 3.6V 8 Supply Current in mA 2.7V 6 4 2 0 1 2 3 4 5 Frequency in MHz Note : T = 25 ° C Typical ICC1 vs. Frequency (June, 2005, Version 1.1) 19 AMIC Technology, Corp. A29L800A Series AC Characteristics Read Only Operations (TA=0°C to 70°C or -40°C to +85°C for –U, -25°C to + 85°C for –I) Parameter Symbols Description Test Setup JEDEC Std tAVAV tRC Read Cycle Time (Note 1) tAVQV tACC Address to Output Delay tELQV tCE Chip Enable to Output Delay tGLQV tOE Output Enable to Output Delay tOEH Output Enable Hold Time (Note 1) Speed Unit -70 -90 Min. 70 90 ns CE = VIL OE = VIL Max. 70 90 ns OE = VIL Max. 70 90 ns Max. 30 35 ns Min. 0 0 ns Min. 10 10 Max. 25 30 ns 25 30 ns 0 0 ns Read Toggle and Data Polling tEHQZ tDF Chip Enable to Output High Z (Notes 1) tGHQZ tDF Output Enable to Output High Z (Notes 1) tAXQX tOH Output Hold Time from Addresses, CE or OE , Whichever Occurs First (Note 1) Min. ns Notes: 1. Not 100% tested. 2. See Test Conditions and Test Setup for test specifications. Timing Waveforms for Read Only Operation tRC Addresses Addresses Stable tACC CE tDF tOE OE tOEH WE tCE tOH High-Z Output Output Valid High-Z RESET 0V RY/BY (June, 2005, Version 1.1) 20 AMIC Technology, Corp. A29L800A Series AC Characteristics Hardware Reset ( RESET ) (TA=0°C to 70°C or -40°C to +85°C for –U, -25°C to + 85°C for –I) Parameter JEDEC Std Description Test Setup All Speed Options Unit tREADY RESET Pin Low (During Embedded Algorithms) to Read or Write (See Note) Max 20 µs tREADY RESET Pin Low (Not During Embedded Algorithms) to Read or Write (See Note) Max 500 ns RESET Pulse Width RESET High Time Before Read (See Note) RY/ BY Recovery Time RESET Low to Standby Mode Min 500 ns Min 50 ns tRP tRH tRB tRPD Min 0 ns Min 20 µs Note: Not 100% tested. RESET Timings RY/BY CE, OE tRH RESET tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms ~ ~ ~ ~ tReady RY/BY tRB CE, OE ~ ~ RESET tRP (June, 2005, Version 1.1) 21 AMIC Technology, Corp. A29L800A Series AC Characteristics Word/Byte Configuration ( BYTE ) (TA=0°C to 70°C or -40°C to +85°C for –U, -25°C to + 85°C for –I) Parameter JEDEC Description All Speed Options Std -70 tELFL/tELFH Unit -90 CE to BYTE Switching Low or High Max 5 ns tFLQZ BYTE Switching Low to Output High-Z Max 25 30 ns tHQV BYTE Switching High to Output Active Min 70 90 ns BYTE Timings for Read Operations CE OE BYTE tELFL BYTE Switching from word to byte mode Data Output (I/O 0-I/O 14) I/O0-I/O14 I/O 15 Output I/O15 (A-1) Data Output (I/O 0-I/O 7) Address Input tFLQZ tELFH BYTE BYTE Switching from byte to word mode I/O0-I/O14 Data Output (I/O 0-I/O 7) I/O15 (A-1) Address Input Data Output (I/O 0-I/O 14) I/O 15 Output tFHQV BYTE Timings for Write Operations CE The falling edge of the last WE signal WE BYTE tSET (tAS) tHOLD(tAH) Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. (June, 2005, Version 1.1) 22 AMIC Technology, Corp. A29L800A Series AC Characteristics Erase and Program Operations (TA=0°C to 70°C or -40°C to +85°C for –U, -25°C to + 85°C for –I) Parameter Description Speed Unit JEDEC Std tAVAV tWC Write Cycle Time (Note 1) Min. tAVWL tAS Address Setup Time Min. tWLAX tAH Address Hold Time Min. 45 45 ns tDVWH tDS Data Setup Time Min. 35 45 ns tWHDX tDH Data Hold Time Min. 0 ns tOES Output Enable Setup Time Min. 0 ns Read Recover Time Before Write Min. 0 ns tGHWL tGHWL -70 -90 70 90 0 ns ns ( OE high to WE low) tELWL tCS CE Setup Time Min. 0 ns tWHEH tCH CE Hold Time Min. 0 ns tWLWH tWP Write Pulse Width Min. tWHWL tWPH Write Pulse Width High Min. 30 Byte Typ. 35 tWHWH1 tWHWH1 Word Typ. 70 Sector Erase Operation (Note 2) Typ. 1.0 sec tvcs VCC Set Up Time (Note 1) Min. 50 µs tRB Recovery Time from RY/ BY Min 0 ns Program/Erase Valid to RY/ BY Delay Min 90 ns tWHWH2 tWHWH2 tBUSY Byte Programming Operation (Note 2) 35 35 ns ns µs Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. (June, 2005, Version 1.1) 23 AMIC Technology, Corp. A29L800A Series Timing Waveforms for Program Operation Read Status Data (last two cycles) Program Command Sequence (last two cycles) PA 555h PA tAH PA ~ ~ ~ ~ Addresses tAS ~ ~ tWC CE ~ ~ tCH OE tWP ~ ~ tWHWH1 WE tCS tWPH Data tDH A0h PD ~ ~ tDS tBUSY Status DOUT tRB ~ ~ ~ ~ RY/BY tVCS VCC Note : 1. PA = program addrss, PD = program data, Dout is the true data at the program address. 2. Illustration shows device in word mode. Timing Waveforms for Chip/Sector Erase Operation (June, 2005, Version 1.1) 24 AMIC Technology, Corp. A29L800A Series Erase Command Sequence (last two cycles) tAS ~ ~ tWC SA 2AAh VA 555h for chip erase tAH VA ~ ~ ~ ~ Addresses Read Status Data ~ ~ CE OE tCH ~ ~ tWP WE tWPH tWHWH2 tCS tDH 55h Data 30h ~ ~ tDS 10h for chip erase tBUSY In Progress Complete tRB ~ ~ RY/BY ~ ~ tVCS VCC Note : 1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus"). 2. Illustratin shows device in word mode. (June, 2005, Version 1.1) 25 AMIC Technology, Corp. A29L800A Series Timing Waveforms for Data Polling (During Embedded Algorithms) ~ ~ tRC Addresses VA tACC CE VA ~ ~ ~ ~ VA tCE tCH ~ ~ tOE OE tDF ~ ~ tOEH WE tOH Status Data ~ ~ Complement Complement True Valid Data ~ ~ High-Z I/O7 Status Data True Valid Data High-Z I/O0 - I/O6 High-Z tBUSY ~ ~ RY/BY Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle. (June, 2005, Version 1.1) 26 AMIC Technology, Corp. A29L800A Series Timing Waveforms for Toggle Bit (During Embedded Algorithms) ~ ~ tRC Addresses VA VA tACC CE VA ~ ~ ~ ~ VA tCE tCH tOE ~ ~ ~ ~ OE tDF tOEH WE I/O6 , I/O2 High-Z tBUSY Valid Status Valid Status (first read) (second read) ~ ~ tOH Valid Status Valid Data (stop togging) ~ ~ RY/BY Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Timing Waveforms for I/O2 vs. I/O6 ~ ~ Erase Complete ~ ~ ~ ~ Erase ~ ~ ~ ~ ~ ~ Erase Suspend Read ~ ~ ~ ~ ~ ~ I/O2 ~ ~ I/O6 Erase Suspend Program Erase Suspend Read ~ ~ Erase Erase Resume ~ ~ WE Enter Erase Suspend Program ~ ~ ~ ~ Erase Suspend ~ ~ Enter Embedded Erasing I/O2 and I/O6 toggle with OE and CE Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Status" for more information. (June, 2005, Version 1.1) 27 AMIC Technology, Corp. A29L800A Series Timing Waveforms for Alternate CE Controlled Write Operation PA for program SA for sector erase 555 for chip erase Data Polling ~ ~ 555 for program 2AA for erase PA ~ ~ Addresses tAS tWH tAH ~ ~ tWC ~ ~ WE OE tWHWH1 or 2 ~ ~ tCP tBUSY tCPH CE tWS tDS ~ ~ tDH Data A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase DOUT ~ ~ tRH I/O 7 RESET ~ ~ RY/BY Note : 1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O 2. Figure indicates the last two bus cycles of the command sequence. 7 = Complement of Data Input, D OUT = Array Data. Erase and Programming Performance Parameter Sector Erase Time Chip Erase Time Byte Programming Time Typ. (Note 1) 1.0 18 35 Max. (Note 2) 4 Unit sec sec 300 µs 70 500 Byte Mode 11 33 µs sec Word Mode 7.2 21.6 sec Word Programming Time Chip Programming Time (Note 3) Comments Excludes 00h programming prior to erasure Excludes system-level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 10,000 cycles. Additionally, programming typically assumes checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7V, 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set I/O5 = 1. See the section on I/O5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 5 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 10,000 cycles. (June, 2005, Version 1.1) 28 AMIC Technology, Corp. A29L800A Series Latch-up Characteristics Description Input Voltage with respect to VSS on all I/O pins VCC Current Input voltage with respect to VSS on all pins except I/O pins Min. Max. -1.0V VCC+1.0V -100 mA +100 mA -1.0V 12.5V (including A9, OE and RESET ) Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time. TSOP and SOP Pin Capacitance Parameter Symbol Parameter Description CIN Input Capacitance COUT Output Capacitance CIN2 Control Pin Capacitance Test Setup Typ. Max. Unit VIN=0 6 7.5 pF VOUT=0 8.5 12 pF VIN=0 7.5 9 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0MHz Data Retention Parameter Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Minimum Pattern Data Retention Time (June, 2005, Version 1.1) 29 AMIC Technology, Corp. A29L800A Series Test Conditions Test Specifications Test Condition -70 -90 Output Load Unit 1 TTL gate Output Load Capacitance, CL(including jig capacitance) 30 100 pF Input Rise and Fall Times 5 5 ns Input Pulse Levels 0.0 - 3.0 0.0 - 3.0 V Input timing measurement reference levels 1.5 1.5 V Output timing measurement reference levels 1.5 1.5 V Test Setup 3.3 V 2.7 KΩ Device Under Test CL (June, 2005, Version 1.1) 6.2 KΩ 30 Diodes = IN3064 or Equivalent AMIC Technology, Corp. A29L800A Series Ordering Information Top Boot Sector Flash Part No. Access Time (ns) Program/Erase Current Typ. (mA) Active Read Current Typ. (mA) Standby Current Typ. (µA) A29L800ATM-70 Package 44Pin SOP A29L800ATM-70F 44Pin Pb-Free SOP A29L800ATV-70 48Pin TSOP A29L800ATV-70F 48Pin Pb-Free TSOP A29L800ATV-70IF 48Pin Pb-Free TSOP A29L800ATV-70U 70 9 20 0.2 A29L800ATV-70UF 48Pin TSOP 48Pin Pb-Free TSOP A29L800ATG-70 48-ball TFBGA A29L800ATG-70F 48-ball Pb-Free TFBGA A29L800ATG-70U 48-ball TFBGA A29L800ATG-70UF 48-ball Pb-Free TFBGA A29L800ATM-90 44Pin SOP A29L800ATM-90F 44Pin Pb-Free SOP A29L800ATV-90 48Pin TSOP A29L800ATV-90F A29L800ATV-90U 48Pin Pb-Free TSOP 90 9 20 A29L800ATV-90UF 0.2 48Pin TSOP 48Pin Pb-Free TSOP A29L800ATG-90 48-ball TFBGA A29L800ATG-90U 48-ball TFBGA A29L800ATG-90UF 48-ball Pb-Free TFBGA Note: -U is for industrial operating temperature range: -40°C to +85°C -I is for industrial operating temperature range: -25°C to +85°C (June, 2005, Version 1.1) 31 AMIC Technology, Corp. A29L800A Series Ordering Information (continued) Bottom Boot Sector Flash Part No. Access Time (ns) Program/Erase Current Typ. (mA) Active Read Current Typ. (mA) Standby Current Typ. (µA) A29L800AUM-70 Package 44Pin SOP A29L800AUM-70F 44Pin Pb-Free SOP A29L800AUV-70 48Pin TSOP A29L800AUV-70F 48Pin Pb-Free TSOP A29L800AUV-70IF 48Pin Pb-Free TSOP A29L800AUV-70U 70 9 20 0.2 A29L800AUV-70UF 48Pin TSOP 48Pin Pb-Free TSOP A29L800AUG-70 48-ball TFBGA A29L800AUG-70F 48-ball Pb-Free TFBGA A29L800AUG-70U 48-ball TFBGA A29L800AUG-70UF 48-ball Pb-Free TFBGA A29L800AUM-90 44Pin SOP A29L800AUM-90F 44Pin Pb-Free SOP A29L800AUV-90 48Pin TSOP A29L800AUV-90F 48Pin Pb-Free TSOP A29L800AUV-90U 48Pin TSOP 90 9 20 A29L800AUV-90UF 0.2 48Pin Pb-Free TSOP A29L800AUG-90 48-ball TFBGA A29L800AUG-90F 48-ball Pb-Free TFBGA A29L800AUG-90U 48-ball TFBGA A29L800AUG-90UF 48-ball Pb-Free TFBGA Note: -U is for industrial operating temperature range: -40°C to +85°C -I is for industrial operating temperature range: -25°C to +85°C (June, 2005, Version 1.1) 32 AMIC Technology, Corp. A29L800A Series Package Information SOP 44L Outline Dimensions unit: inches/mm 23 Gauge Plane HE E 44 θ L 0.010" 1 b 22 Detail F e y A A1 S D A2 C D L1 Seating Plane See Detail F Symbol Dimensions in inches Min Nom Max Dimensions in mm Min Nom Max A - - 0.118 - - 3.00 A1 0.004 - - 0.10 - - A2 0.103 0.106 0.109 2.62 2.69 2.77 b 0.013 0.016 0.020 0.33 0.40 0.50 C 0.007 0.008 0.010 0.18 0.20 0.25 D - 1.122 1.130 - 28.50 28.70 E 0.490 0.496 0.500 12.45 12.60 12.70 e - 0.050 - - 1.27 - HE 0.620 0.631 0.643 15.75 16.03 16.33 L 0.024 0.032 0.040 0.61 0.80 1.02 L1 - 0.0675 - - 1.71 - S - - 0.045 - - 1.14 y - - 0.004 - - 0.10 θ 0° - 8° 0° - 8° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. (June, 2005, Version 1.1) 33 AMIC Technology, Corp. A29L800A Series Package Information TSOP 48L (Type I) Outline Dimensions unit: inches/mm 1 48 24 25 y D1 A1 A2 A D 0.25 c S e E b D Detail "A" L θ Detail "A" Symbol Dimensions in inches Min Nom Max Dimensions in mm Min Nom Max A - - 0.047 - - 1.20 A1 0.002 - 0.006 0.05 - 0.15 A2 0.037 0.039 0.042 0.94 1.00 1.06 b 0.007 0.009 0.011 0.18 0.22 0.27 c 0.004 - 0.008 0.12 - 0.20 D 0.779 0.787 0.795 19.80 20.00 20.20 D1 0.720 0.724 0.728 18.30 18.40 18.50 E - 0.472 0.476 - 12.00 12.10 e L 0.020 BASIC 0.016 S 0.020 0.50 BASIC 0.024 0.40 0.011 Typ. 0.50 0.60 0.28 Typ. y - - 0.004 - - 0.10 θ 0° - 8° 0° - 8° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. (June, 2005, Version 1.1) 34 AMIC Technology, Corp. A29L800A Series Package Information 48LD CSP (6 x 8 mm) Outline Dimensions unit: mm (48TFBGA) BOTTOM VIEW TOP VIEW b H B A E1 e G F E D C B A 1 2 3 4 5 6 E H G F E D C e D1 Ball*A1 CORNER D A SIDE VIEW SEATING PLANE A1 C 0.10 C Symbol A A1 b D D1 e E E1 (June, 2005, Version 1.1) Dimensions in mm Min. 0.20 0.30 5.90 Nom. 0.25 6.00 4.00 BSC 0.80 7.90 8.00 5.60 BSC 35 Max. 1.20 0.30 0.40 6.10 8.10 AMIC Technology, Corp.