SN54ABT640, SN74ABT640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS104C – FEBRUARY 1991 – REVISED JANUARY 1997 D D D D SN54ABT640 . . . J PACKAGE SN74ABT640 . . . DB, DW, N, OR PW PACKAGE (TOP VIEW) DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OE B1 B2 B3 B4 B5 B6 B7 B8 SN54ABT640 . . . FK PACKAGE (TOP VIEW) description The ’ABT640 bus transceivers are designed for asynchronous communication between data buses. These devices transmit inverted data from the A bus to the B bus or from the B bus to the A bus, depending on the level at the directioncontrol (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 B1 B2 B3 B4 B5 A8 GND B8 B7 B6 A3 A4 A5 A6 A7 OE D State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Drive Outputs (–32-mA IOH, 64-mA IOL ) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Plastic (N) and Ceramic (J) DIPs A2 A1 DIR VCC D To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT640 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT640 is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUTS OE DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT640, SN74ABT640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS104C – FEBRUARY 1991 – REVISED JANUARY 1997 logic symbol† OE DIR A1 19 1 2 G3 3 EN1 [BA] 3 EN2 [AB] 1 1 A2 A3 A4 A5 A6 A7 A8 3 18 1 2 B1 17 4 16 5 15 6 14 7 13 8 12 9 11 B2 B3 B4 B5 B6 B7 B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE DIR A1 19 1 2 18 To Seven Other Transceivers 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 B1 SN54ABT640, SN74ABT640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS104C – FEBRUARY 1991 – REVISED JANUARY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT640 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT640 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero. recommended operating conditions (see Note 3) SN54ABT640 MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC –24 Low-level output current 48 ∆t/∆v Input transition rise or fall rate High-level input voltage SN74ABT640 MIN 2 2 0.8 Input voltage 0 Outputs enabled TA Operating free-air temperature NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating. 0 5 –55 125 –40 UNIT V V 0.8 V VCC –32 V mA 64 mA 5 ns/V 85 °C PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT640, SN74ABT640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS104C – FEBRUARY 1991 – REVISED JANUARY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOL VCC = 4 4.5 5V MIN MIN –1.2 MAX SN74ABT640 MIN –1.2 MAX –1.2 2.5 2.5 IOH = –3 mA IOH = –24 mA 3 3 3 2 2 IOH = –32 mA IOL = 48 mA 2* VI = VCC or GND IOZH‡ IOZL‡ VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.5 V Ioff VCC = 0, VCC = 5.5 V, VO = 5.5 V VI or VO ≤ 4.5 V VCC = 5.5 V, VO = 2.5 V Outputs high ICEX IO§ 0.55 0.55* 0.55 A or B ports Data inp inputs ts ∆ICC¶ Control inputs Ci Control inputs Cio A or B ports VCC = 5.5 V, IO = 0, VI = VCC or GND VCC = 5.5 V, One input at 3.4 V,, Other inputs at VCC or GND Outputs high V mV ±1 ±1 ±1 ±100 ±100 ±100 50 50 50 µA –50 –50 ±100 50 –50 V 2 0.55 IOL = 64 mA VCC = 5 5.5 5V V, A or B ports UNIT V 100 Control inputs ICC SN54ABT640 2.5 Vhys II TA = 25°C TYP† MAX –100 –180 50 –50 –180 –50 µA –50 µA ±100 µA 50 µA –180 mA 5 250 250 250 µA Outputs low 24 30 30 30 mA Outputs disabled 0.5 250 250 250 µA Outputs enabled 1.5 1.5 1.5 Outputs disabled 0.05 0.05 0.05 1.5 1.5 1.5 VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V mA 4 pF 7 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ The parameters IOZH and IOZL include the input leakage current. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL OE A or B tPHZ tPLZ OE A or B PARAMETER VCC = 5 V, TA = 25°C MIN TYP MAX POST OFFICE BOX 655303 MIN MAX SN74ABT640 MIN MAX 1 2.7 4.2 1 5 1 4.9 1.5 2.7 4.3 1.5 5 1.5 4.9 1.5 3.7 4.9 1.5 5.9 1.5 5.8 1.3 5 5.9 1.3 7.4 1.3 7.3 2.5 4.1 6.5 2.5 6.9 2.5 6.8 2 3.3 5.3 2 5.6 2 5.5 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 SN54ABT640 • DALLAS, TEXAS 75265 UNIT ns ns ns SN54ABT640, SN74ABT640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS104C – FEBRUARY 1991 – REVISED JANUARY 1997 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V Input 1.5 V th 3V 1.5 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 0V 1.5 V 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note B) VOH Output 1.5 V tPZL tPHL tPLH 3V Output Control 1.5 V Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V tPZH 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74ABT640DBLE OBSOLETE SSOP DB 20 SN74ABT640DBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT640DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT640DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT640DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT640DWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT640DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT640DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT640DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT640DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT640N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ABT640NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ABT640NSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT640NSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT640NSRG4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT640PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT640PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT640PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT640PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT640PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT640PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ABT640DBR Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74ABT640DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74ABT640PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ABT640DBR SSOP DB 20 2000 346.0 346.0 33.0 SN74ABT640DWR SOIC DW 20 2000 346.0 346.0 41.0 SN74ABT640PWR TSSOP PW 20 2000 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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