AMICC A48P4616

A48P4616
Preliminary
16M X 16 Bit DDR DRAM
Document Title
16M X 16 Bit DDR DRAM
Revision History
Rev. No.
0.0
History
Issue Date
Remark
Initial issue
September 5, 2005
Preliminary
Preliminary (September, 2005, Version 0.0)
AMIC Technology, Corp.
A48P4616
Features
CAS Latency and Frequency
CAS
Latency
DQS is edge-aligned with data for reads and is centeraligned with data for writes.
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation.
Data mask (DM) for write data.
DLL aligns DQ and DQS transitions with CK transitions.
Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS.
Burst lengths: 2, 4, or 8
CAS Latency: 2/2.5(DDR333), 2.5/3(DDR400)
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
7.8µs Maximum Average Periodic Refresh Interval
2.5V (SSTL_2 compatible) I/O
VDD = VDDQ = 2.5V ± 0.2V (DDR333)
VDD = VDDQ = 2.6V ± 0.1V (DDR400)
Available in Halogen and Lead Free packaging
Maximum Operating Frequency (MHz)
DDR400 (5T)
DDR333 (6K)
2
-
133
2.5
166
166
3
200
-
DDR 256M bit, die C, based on 110nm design rules.
Double data rate architecture: two data transfers per
clock cycle.
Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver.
General Description
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate
architecture is essentially a 2n prefetch architecture with an
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 256Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write command. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edgealigned with data for Reads and center-aligned with data for
Writes.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4, or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row precharge and activation time.
The 256Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
An auto refresh mode is provided along with a power-saving
Power Down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class
II com-patible.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
Preliminary (September, 2005, Version 0.0)
1
AMIC Technology, Corp.
A48P4616
Pin Configuration
TSOP (II)
Column Address Table
Organization
Coiumn Addres
64Mb x 4
A0-A9, A11
32Mb x 8
A0-A9
16Mb x16
A0-A8
Preliminary (September, 2005, Version 0.0)
2
AMIC Technology, Corp.
A48P4616
Block Diagram (64Mb x 4)
Note:
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and
DQS signals.
Preliminary (September, 2005, Version 0.0)
3
AMIC Technology, Corp.
A48P4616
Block Diagram (32Mb x 8)
Note:
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and
DQS signals.
Preliminary (September, 2005, Version 0.0)
4
AMIC Technology, Corp.
A48P4616
Block Diagram (16Mb x 16)
Note:
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and
DQS signals.
Preliminary (September, 2005, Version 0.0)
5
AMIC Technology, Corp.
A48P4616
Pin Descriptions
Symbol
Type
Description
Clock: CK and CK are differential clock inputs. All address and control input signals
CK, CK
CKE, CKE0, CKE1
Input
Input
are sampled on the crossing of the positive edge of CK and negative edge of CK.
Output (read) data is referenced to the crossings of CK and CK (both directions of
crossing).
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock
signals and device input buffers and output drivers. Taking CKE Low provides
Precharge Power Down and Self Refresh operation (all banks idle), or Active Power
Down (row Active in any bank). CKE is synchronous for power down entry and exit,
and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be
maintained high throughout read and write accesses. Input buffers, excluding CK,
CK and CKE are disabled during Power Down. Input buffers, excluding CKE, are
disabled during self refresh. The standard pinout includes one CKE pin. Optional
pinouts might include CKE1 on a different pin, in addition to CKE0, to facilitate
independent power down control of stacked devices.
Chip Select: All commands are masked when CS is registered high. CS provides
for external bank selection on systems with multiple banks. CS is considered part of
CS , CS0 , CS1
Input
the command code. The standard pinout includes one CS pin. Optional pinouts
might include CS1 on a different pin, in addition to CS0 , to allow upper or lower
deck selection on stacked devices.
Input
Command Inputs: RAS , CAS , WE (along with CS ) define the command being
entered.
DM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled high coincident with that input data during a Write access. DM
is sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading. During a Read, DM can be driven high, low, or
floated.
BS0, BS1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or
Precharge command is being applied. BA0 and BA1 also determines if the mode
register or extended mode register is to be accessed during a MRS or EMRS cycle.
A0-A12
Input
Address Inputs: Provide the row address for Active commands, and the column
address and Auto Precharge bit for Read/Write commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 low) or all
banks (A10 high). If only one bank is to be precharged, the bank is selected by BA0,
BA1. The address inputs also provide the op-code during a Mode Register Set
command.
DQ
Input / Output
Data Input/Output: Data bus.
DQS. LDQS, UDQS
Input / Output
Data Strobe: Output with read data, input with write data. Edge-aligned with read
data, centered in write data. Used to capture write data. For the x16, LDQS
corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15
RAS , CAS , WE
NC
No Connect: No internal electrical connection is present.
NU
Electrical connection is present. Should not be connected at second level of
assembly.
VDDQ
Supply
DQ Power Supply: 2.5V ± 0.2V.
VSSQ
Supply
DQ Ground
VDD
Supply
Power Supply: 2.5V ± 0.2V.
VSS
Supply
Ground
VREF
Supply
SSTL_2 reference voltage: (VDDQ / 2) ± 1%.
Preliminary (September, 2005, Version 0.0)
6
AMIC Technology, Corp.
A48P4616
Functional Description
Initialization
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 268, 435, 456 bits. The
256Mb DDR SDRAM is internally configured as a quad-bank
DRAM.
Only one of the following two conditions must be met.
• No power sequencing is specified during power up or power
down given the following criteria: VDD and VDDQ are driven
from a single power converter output VTT meets the
specification A minimum resistance of 42 ohms limits the
input current from the VTT supply into any pin and VREF tracks
VDDQ /2
The 256Mb DDR SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The doubledata-rate architecture is essentially a 2n prefetch architecture,
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access for
the 256Mb DDR SDRAM consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half clock cycle data transfers
at the I/O pins.
or
• The following relationships must be followed: VDDQ is driven
after or with VDD such that VDDQ < VDD + 0.3V VTT is driven
after or with VDDQ such that VTT < VDDQ + 0.3V VREF is driven
after or with VDDQ such that VREF < VDDQ + 0.3V
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write
command. The address bits registered coincident with the
Active command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-A12 select the row).
The address bits registered coincident with the Read or Write
command are used to select the starting column location for
the burst access.
The DQ and DQS outputs are in the High-Z state, where they
remain until driven in normal operation (by a read access).
After all power supply and reference voltages are stable, and
the clock is stable, the DDR SDRAM requires a 200μs delay
prior to applying an executable command.
Once the 200 μ s delay has been satisfied, a Deselect or
NOP command should be applied, and CKE must be brought
HIGH. Following the NOP command, a Precharge ALL
command must be applied. Next a Mode Register Set
command must be issued for the Extended Mode Register,
to enable the DLL, then a Mode Register Set command must
be issued for the Mode Register, to reset the DLL, and to
program the operating parameters. 200 clock cycles are
required between the DLL reset and any read command. A
Precharge ALL command should be applied, placing the
device in the “all banks idle” state
Prior to normal operation, the DDR SDRAM must be
initialized. The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
Once in the idle state, two auto refresh cycles must be
performed. Additionally, a Mode Register Set command for
the Mode Register, with the reset DLL bit deactivated (i.e. to
program operating parameters without resetting the DLL)
must be performed. Following these cycles, the DDR
SDRAM is ready for normal operation.
DDR SDRAM’s may be reinitialized at any time during
normal operation by asserting a valid MRS command to
either the base or extended mode registers without affecting
the contents of the memory array. The contents of either the
mode register or extended mode register can be modified at
any valid time during device operation without affecting the
state of the internal address refresh counters used for device
refresh.
Preliminary (September, 2005, Version 0.0)
7
AMIC Technology, Corp.
A48P4616
Register Definition
Mode Register
Burst Length
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, and
an operating mode. The Mode Register is programmed via
the Mode Register Set command (with BA0 = 0 and BA1 = 0)
and retains the stored information until it is programmed
again or the device loses power (except for bit A8, which is
self-clearing).
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable. The
burst length determines the maximum number of column
locations that can be accessed for a given Read or Write
command. Burst lengths of 2, 4, or 8 locations are available
for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
Mode Register bits A0-A2 specify the burst length, A3
specifies the type of burst (sequential or interleaved), A4-A6
specify the CAS latency, and A7-A12 specify the operating
mode.
When a Read or Write command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst wraps within the block if a boundary is reached.
The block is uniquely selected by A1-Ai when the burst
length is set to two, by A2-Ai when the burst length is set to
four and by A3-Ai when the burst length is set to eight (where
Ai is the most significant column address bit for a given
configuration). The remaining (least significant) address bit(s)
is (are) used to select the starting location within the block.
The programmed burst length applies to both Read and
Write bursts.
The Mode Register must be loaded when all banks are idle,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these
requirements results in unspecified operation.
Mode Register Operation
BA1
BA0
0*
0*
A12
A11
A10
A9
A8
A7
A6
Operating Mode
A6-A0
0
0
0
Valid
0
1
0
Valid
0
0
1
VS**
-
-
-
A4
CAS Latency
Type
Normal operation
Do not reset DLL
Normal operation
in DLL Reset
Vendor-Specific
Test Mode
Reserved
A3
CAS Latency
Operating Mode
A12-A9 A8 A7
A5
BT
A2
A1
A0
Burst Length
A3 Burst Type
Address Bus
Mode Register
Burst Length
A6
A5
A4
Type
0
Sequential
A2
A1
A0
Type
0
0
0
Reserved
1
Interleave
0
0
0
Reserved
0
0
1
Reserved
0
0
1
2
0
1
0
2
0
1
0
4
0
1
1
3 (Option)
0
1
1
8
1
0
0
Reserved
1
0
0
Reserved
1
0
1
1.5
(Option)
1
0
1
Reserved
1
1
0
2.5
1
1
0
Reserved
1
1
1
Reserved
1
1
1
Reserved
Note:
1. VS** Vendor Specific
2. * BA0 and BA1 must be 0, 0 to select the Mode Register
(vs. the Extended Mode Register).
Preliminary (September, 2005, Version 0.0)
8
AMIC Technology, Corp.
A48P4616
Burst Type
Read Latency
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3.
The Read latency, or CAS latency, is the delay, in clock
cycles, between the registration of a Read command and the
availability of the first burst of output data. The latency can
be programmed 2 or 2.5 clocks.
The ordering of accesses within a burst is determined by the
burst length, the burst type and the starting column address,
as shown in Burst Definition on page 10.
If a Read command is registered at clock edge n, and the
latency is m clocks, the data is available nominally coincident
with clock edge n + m.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
Burst Definition
Starting Column Address
Burst Length
A2
A1
Type = Sequential
Type = Interleaved
0
0-1
0-1
1
1-0
1-0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
2
4
8
Order of Accesses Within a Burst
A0
Note:
1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Preliminary (September, 2005, Version 0.0)
9
AMIC Technology, Corp.
A48P4616
Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero, and bits A0-A6 set
to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to
zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should
always be followed by a Mode Register Set command to select normal operating mode.
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states
should not be used as unknown operation or incompatibility with future versions may result.
CAS Latencies
Preliminary (September, 2005, Version 0.0)
10
AMIC Technology, Corp.
A48P4616
Extended Mode Register
DLL Enable/Disable
The Extended Mode Register controls functions beyond
those controlled by the Mode Register; these additional
functions include DLL enable/disable, bit A0; output drive
strength selection, bit A1; and QFC output enable/disable, bit
A2 (NTC optional). These functions are controlled via the bit
settings shown in the Extended Mode Register Definition.
The Extended Mode Register is programmed via the Mode
Register Set command (with BA0 = 1 and BA1 = 0) and
retains the stored information until it is programmed again or
the device loses power. The Extended Mode Register must
be loaded when all banks are idle, and the controller must
wait the specified time before initiating any subsequent
operation. Violating either of these requirements result in
unspecified operation.
The DLL must be enabled for normal operation. DLL enable
is required during power up initialization, and upon returning
to normal operation after having disabled the DLL for the
purpose of debug or evaluation. The DLL is automatically
disabled when entering self refresh operation and is
automatically re-enabled upon exit of self refresh operation.
Any time the DLL is enabled, 200 clock cycles must occur to
allow time for the internal clock to lock to the externally
applied clock before a Read command can be issued. This is
the reason for introducing timing parameter tXSRD for DDR
SDRAM’s (Exit Self Refresh to Read Command). Non- Read
commands can be issued 2 clocks after the DLL is enabled
via the EMRS command (tMRD) or 10 clocks after the DLL is
enabled via self refresh exit command (tXSNR, Exit Self
Refresh to Non-Read Command).
QFC Enable/Disable
Output Drive Strength
The QFC signal is an optional DRAM output control used to
isolate module loads (DIMMs) from the system memory bus
by means of external FET switches when the given module
(DIMM) is not being accessed. The QFC function is an
optional feature for NANYA and is not included on all DDR
SDRAM devices.
The normal drive strength for all outputs is specified to be
SSTL_2, Class II.
Extended Mode Register Definition
BA1
BA0
0*
1*
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
Operating Mode
Operating Mode
A2
QFC
A2
A1
A0
QFC
DS
DLL
Drive Strength
Address Bus
Extended
Mode Register
A0
DLL
A12-A3
A2-A0
Type
0
Disable
A1
Type
0
Enable
0
Valid
Normal Operation
1
Enable (Optional)
0
Normal
1
Disable
-
All Other States
Reserved
1
Reserved
-
Note:
* BA0 and BA1 must be 1, 0 to select the Extended Mode Register
(vs. the base Mode Register)
Preliminary (September, 2005, Version 0.0)
11
AMIC Technology, Corp.
A48P4616
Commands
Truth Tables 1a and 1b prvide a reference of the commands supported by DDR SDRAM device. A verbal description of each
commands follows.
Name (Function)
CS
RAS
CAS
WE
Address
MNE
Note
Deselect (Nop)
H
X
X
X
X
NOP
1, 9
No Openration (Nop)
L
H
H
H
X
NOP
1, 9
Active (Select Bank And Activate Row)
L
L
H
H
Bank/Row
ACT
1, 3
Read (Select Bank And Activate Column, And Start Read Burst)
L
H
L
H
Bank/Col
Read
1, 4
Write (Select Bank And Activate Column, And Start Write Burst)
L
H
L
L
Bank/Col
Write
1, 4
Burst Terminate
L
H
H
L
X
BST
1, 8
Precharge (Deactivate Row In Bank Or Banks)
L
L
H
L
Code
PRE
1, 5
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
L
L
L
H
X
AR/SR
1, 6, 7
Mode Register Set
L
L
L
L
Op-Code
MRS
1, 2
Note:
1. CKE is high for all commands shown except Self Refresh.
2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0
selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to
the selected Mode Register.)
3. BA0-BA1 provide bank address and A0-A12 provide row address.
4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the
Auto Precharge feature (non-persistent), A10 low disables the Auto Precharge feature.
5. A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”
6. This command is auto refresh if CKE is high; Self Refresh if CKE is low.
7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read
bursts with Auto Precharge enabled or for write bursts
9. Deselect and NOP are functionally interchangeable.
Truth Table 1b: DM Operation
Name (Function)
DM
DQs
Note
Write Enable
L
Valid
1
Write Inhibit
H
X
1
Note: Used to mask write data; provided coincident with the corresponding data.
Preliminary (September, 2005, Version 0.0)
12
AMIC Technology, Corp.
A48P4616
Deselect
The Deselect function prevents new commands from
being executed by the DDR SDRAM. The DDR
SDRAM is effectively deselected. Operations already
in progress are not affected.
If Auto Precharge is selected, the row being accessed is
precharged at the end of the Write burst; if Auto Precharge is
not selected, the row remains open for subsequent accesses.
Input data appearing on the DQs is written to the memory
array subject to the DM input logic level appearing coincident
with the data. If a given DM signal is registered low, the
corresponding data is written to memory; if the DM signal is
registered high, the corresponding data inputs are ignored,
and a Write is not executed to that byte/column location.
No Operation (NOP)
The No Operation (NOP) command is used to perform a
NOP to a DDR SDRAM. This prevents unwanted commands
from being registered during idle or wait states. Operations
already in progress are not affected.
Precharge
The Precharge command is used to deactivate (close) the
open row in a particular bank or the open row(s) in all banks.
The bank(s) will be available for a subsequent row access a
specified time (tRP) after the Precharge command is issued.
Input A10 determines whether one or all banks are to be
precharged, and in the case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. Otherwise BA0,
BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated prior
to any Read or Write commands being issued to that bank. A
precharge command is treated as a NOP if there is no open
row in that bank, or if the previously open row is already in
the process of precharging.
Mode Register Set
The mode registers are loaded via inputs A0-A12, BA0 and
BA1 while issuing the Mode Register Set Command. See
mode register descriptions in the Register Definition section.
The Mode Register Set command can only be issued when
all banks are idle and no bursts are in progress. A
subsequent executable command cannot be issued until tMRD
is met.
Active
The Active command is used to open (or activate) a row in a
particular bank for a subsequent access. The value on the
BA0, BA1 inputs selects the bank, and the address provided
on inputs A0-A12 selects the row. This row remains active
(or open) for accesses until a Precharge (or Read or Write
with Auto Precharge) is issued to that bank. A Precharge (or
Read or Write with Auto Precharge) command must be
issued and completed before opening a different row in the
same bank.
Auto Precharge
Auto Precharge is a feature which performs the same
individual-bank precharge function described above, but
without requiring an explicit command. This is accomplished
by using A10 to enable Auto Precharge in conjunction with a
specific Read or Write command. A precharge of the
bank/row that is addressed with the Read or Write command
is automatically performed upon completion of the Read or
Write burst. Auto Precharge is non-persistent in that it is
either enabled or disabled for each individual Read or Write
command. Auto Precharge ensures that the precharge is
initiated at the earliest valid stage within a burst. This is
determined as if an explicit Precharge command was issued
at the earliest possible time without violating tRAS(min). The
user must not issue another command to the same bank until
the precharge (tRP) is completed.
Read
The Read command is used to initiate a burst read access to
an active (open) row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-Ai,
Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for
x4) selects the starting column location. The value on input
A10 determines whether or not Auto Precharge is used. If
Auto Precharge is selected, the row being accessed is
precharged at the end of the Read burst; if Auto Precharge is
not selected, the row remains open for subsequent accesses.
The NTC DDR SDRAM devices supports the optional tRAS
lockout feature. This feature allows a Read command with
Auto Precharge to be issued to a bank that has been
activated (opened) but has not yet satisfied the tRAS(min)
specification. The tRAS lockout feature essentially delays the
onset of the auto precharge operation until two conditions
occur. One, the entire burst length of data has been
successfully prefetched from the memory array; and two,
tRAS(min) has been satisfied.
Write
The Write command is used to initiate a burst write access to
an active (open) row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-Ai,
Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for
x4) selects the starting column location. The value on input
A10 determines whether or not Auto Precharge is used.
Preliminary (September, 2005, Version 0.0)
13
AMIC Technology, Corp.
A48P4616
The refresh addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care” during
an Auto Refresh command. The 256Mb DDR SDRAM
requires Auto Refresh cycles at an average periodic interval
of 7.8⎧s (maximum).
As a means to specify whether a DDR SDRAM device
supports the tRAS lockout feature, a new parameter has been
defined, tRAP (RAS Command to Read Command with Auto
Precharge or better stated Bank Activate to Read Command
with Auto Precharge). For devices that support the tRAS
lockout feature, tRAP = tRCD(min). This allows any Read
Command (with or without Auto Precharge) to be issued to
an open bank once tRCD(min) is satisfied.
Self Refresh
The Self Refresh command can be used to retain data in the
DDR SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the DDR SDRAM
retains data without external clocking. The Self Refresh
command is initiated as an Auto Refresh command
coincident with CKE transitioning low. The DLL is
automatically disabled upon entering Self Refresh, and is
automatically enabled upon exiting Self Refresh (200 clock
cycles must then occur before a Read command can be
issued). Input signals except CKE (low) are “Don’t Care”
during Self Refresh operation.
Burst Terminate
The Burst Terminate command is used to truncate read
bursts (with Auto Precharge disabled). The most re-cently
registered Read command prior to the Burst Terminate
command is truncated, as shown in the Operation section of
this data sheet. Write burst cycles are not to be terminated
with the Burst Terminate command.
Auto Refresh
Auto Refresh is used during normal operation of the DDR
SDRAM and is analogous to CAS Before RAS (CBR)
Refresh in previous DRAM types. This command is
nonpersistent, so it must be issued each time a refresh is
required.
The procedure for exiting self refresh requires a sequence of
commands. CK (and CK) must be stable prior to CKE
returning high. Once CKE is high, the SDRAM must have
NOP commands issued for tXSNR because time is required
for the completion of any internal refresh in progress. A
simple algorithm for meeting both refresh and DLL
requirements is to apply NOPs for 200 clock cycles before
applying any other command.
tRAP Definition
Preliminary (September, 2005, Version 0.0)
14
AMIC Technology, Corp.
A48P4616
Operations
Bank/Row Activation
During Read bursts, the valid data-out element from the
starting column address is available following the CAS
latency after the Read command. Each subsequent data-out
element is valid nominally at the next positive or negative
clock edge (i.e. at the next crossing of CK and CK). The
following timing figure entitled “Read Burst: CAS Latencies
(Burst Length=4)” illustrates the general timing for each
supported CAS latency setting. DQS is driven by the DDR
SDRAM along with output data. The initial low state on DQS
is known as the read preamble; the low state coincident with
the last data-out element is known as the read postamble.
Upon completion of a burst, assuming no other commands
have been initiated, the DQS and DQS goes High-Z. Data
from any Read burst may be concatenated with or truncated
with data from a subsequent Read command. In either case,
a continuous flow of data can be maintained. The first data
element from the new burst follows either the last element of
a completed burst or the last desired data element of a
longer burst which is being truncated. The new Read
command should be issued x cycles after the first Read
command, where x equals the number of desired data
element pairs (pairs are required by the 2n prefetch
architecture). This is shown in timing figure entitled
“Consecutive Read Bursts: CAS Latencies (Burst Length =4
or 8)”. A Read command can be initiated on any positive
clock cycle following a previous Read command.
Nonconsecutive Read data is shown in timing figure entitled
“Non-Consecutive Read Bursts: CAS Latencies (Burst
Length = 4)”. Full-speed Random Read Accesses: CAS
Latencies (Burst Length = 2, 4 or 8) within a page (or pages)
can be performed as shown on page 20.
Before any Read or Write commands can be issued to a
bank within the DDR SDRAM, a row in that bank must be
“opened” (activated). This is accomplished via the Active
command and addresses A0-A12, BA0 and BA1 (see
Activating a Specific Row in a Specific Bank), which decode
and select both the bank and the row to be activated. After
opening a row (issuing an Active command), a Read or Write
command may be issued to that row, subject to the tRCD
specification. A subsequent Active command to a different
row in the same bank can only be issued after the previous
active row has been “closed” (precharged). The minimum
time interval between successive Active commands to the
same bank is defined by tRC. A subsequent Active command
to another bank can be issued while the first bank is being
accessed, which results in a reduction of total row-access
overhead. The minimum time interval between successive
Active commands to different banks is defined by tRRD.
Reads
Subsequent to programming the mode register with CAS
latency, burst type, and burst length, Read bursts are
initiated with a Read command.
The starting column and bank addresses are provided with
the Read command and Auto Precharge is either enabled or
disabled for that burst access. If Auto Precharge is enabled,
the row that is accessed starts precharge at the completion
of the burst, provided tRAS has been satisfied. For the generic
Read commands used in the following illustrations, Auto
Precharge is disabled.
Activating a Specific Row in a Specific Bank
Preliminary (September, 2005, Version 0.0)
15
AMIC Technology, Corp.
A48P4616
tRCD and tRRD Definition
Read Command
Preliminary (September, 2005, Version 0.0)
16
AMIC Technology, Corp.
A48P4616
Read Burst: CAS Latencies (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
17
AMIC Technology, Corp.
A48P4616
Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)
Preliminary (September, 2005, Version 0.0)
18
AMIC Technology, Corp.
A48P4616
Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
19
AMIC Technology, Corp.
A48P4616
Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)
Preliminary (September, 2005, Version 0.0)
20
AMIC Technology, Corp.
A48P4616
The Precharge command should be issued x cycles after the
Read command, where x equals the number of desired data
element pairs (pairs are required by the 2n prefetch
architecture). This is shown in timing figure Read to
Precharge: CAS Latencies (Burst Length = 4 or 8) on page
25 for Read latencies of 2 and 2.5. Following the Precharge
command, a subsequent command to the same bank cannot
be issued until tRP is met. Note that part of the row precharge
time is hidden during the access of the last data elements.
Data from any Read burst may be truncated with a Burst
Terminate command, as shown in timing figure entitled
Terminating a Read Burst: CAS Latencies (Burst Length = 8)
on page 22. The Burst Terminate latency is equal to the read
(CAS) latency, i.e. the Burst Terminate command should be
issued x cycles after the Read command, where x equals the
number of desired data element pairs.
Data from any Read burst must be completed or truncated
before a subsequent Write command can be issued. If
truncation is necessary, the Burst Terminate command must
be used, as shown in timing figure entitled Read to Write:
CAS Latencies (Burst Length = 4 or 8) on page 24. The
example is shown for tDQSS(min). The tDQSS(max) case, not
shown here, has a longer bus idle time. tDQSS(min) and
tDQSS(max) are defined in the section on Writes.
In the case of a Read being executed to completion, a
Precharge command issued at the optimum time (as
described above) provides the same operation that would
result from the same Read burst with Auto Precharge
enabled. The disadvantage of the Precharge command is
that it requires that the command and address busses be
available at the appropriate time to issue the command. The
advantage of the Precharge command is that it can be used
to truncate bursts.
A Read burst may be followed by, or truncated with, a
Precharge command to the same bank (provided that Auto
Precharge was not activated).
Preliminary (September, 2005, Version 0.0)
21
AMIC Technology, Corp.
A48P4616
Terminating a Read Burst: CAS Latencies (Burst Length = 8)
Preliminary (September, 2005, Version 0.0)
22
AMIC Technology, Corp.
A48P4616
Read to Write: CAS Latencies (Burst Length = 4 or 8)
Preliminary (September, 2005, Version 0.0)
23
AMIC Technology, Corp.
A48P4616
Read to Precharge: CAS Latencies (Burst Length = 4 or 8)
Preliminary (September, 2005, Version 0.0)
24
AMIC Technology, Corp.
A48P4616
Read with Auto Precharge: CAS Latencies (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
25
AMIC Technology, Corp.
A48P4616
Writes
Write bursts are initiated with a Write command, as shown in
timing figure Write Command on page 27.
Data for any Write burst may be followed by a subsequent
Read command. To follow a Write without truncating the
write burst, tWTR (Write to Read) should be met as shown in
timing figure Write to Read: Non-Interrupting (CAS Latency =
2; Burst Length = 4) on page 32.
The starting column and bank addresses are provided with
the Write command, and Auto Precharge is either enabled or
disabled for that access. If Auto Precharge is enabled, the
row being accessed is precharged at the completion of the
burst. For the generic Write commands used in the following
illustrations, Auto Precharge is disabled.
Data for any Write burst may be truncated by a subsequent
(interrupting) Read command. This is illustrated in timing
figures “Write to Read: Interrupting (CAS Latency =2; Burst
Length = 8)”, “Write to Read: Minimum DQSS, Odd Number
of Data (3 bit Write), Interrupting (CAS Latency = 2; Burst
Length = 8)”, and “Write to Read: Nominal DQSS,
Interrupting (CAS Latency = 2; Burst Length = 8)”. Note that
only the data-in pairs that are registered prior to the tWTR
period are written to the internal array, and any subsequent
data-in must be masked with DM, as shown in the diagrams
noted previously.
During Write bursts, the first valid data-in element is
registered on the first rising edge of DQS following the write
command, and subsequent data elements are registered on
successive edges of DQS. The Low state on DQS between
the Write command and the first rising edge is known as the
write preamble; the Low state on DQS following the last datain element is known as the write postamble. The time
between the Write command and the first corresponding
rising edge of DQS (tDQSS) is specified with a relatively wide
range (from 75% to 125% of one clock cycle), so most of the
Write diagrams that follow are drawn for the two extreme
cases (i.e. tDQSS(min) and tDQSS(max)). Timing figure Write Burst
(Burst Length = 4) on page 28 shows the two extremes of
tDQSS for a burst of four. Upon completion of a burst,
assuming no other commands have been initiated, the DQS
and DQS enters High-Z and any additional input data is
ignored.
Data for any Write burst may be followed by a subsequent
Precharge command. To follow a Write without truncating the
write burst, tWR should be met as shown in timing figure
Write to Precharge: Non-Interrupting (Burst Length = 4) on
page 36. Data for any Write burst may be truncated by a
subsequent Precharge command, as shown in timing figures
Write to Precharge: Interrupting (Burst Length = 4 or 8) on
page 37 to Write to Precharge: Nominal DQSS (2 bit Write),
Interrupting (Burst Length = 4 or 8) on page 40. Note that
only the data-in pairs that are registered prior to the tWR
period are written to the internal array, and any subsequent
data in should be masked with DM. Following the Precharge
command, a subsequent command to the same bank cannot
be issued until tRP is met.
Data for any Write burst may be concatenated with or
truncated with a subsequent Write command. In either case,
a continuous flow of input data can be maintained. The new
Write command can be issued on any positive edge of clock
following the previous Write command. The first data element
from the new burst is applied after either the last element of a
completed burst or the last desired data element of a longer
burst which is being truncated. The new Write command
should be issued x cycles after the first Write command,
where x equals the number of desired data element pairs
(pairs are required by the 2n prefetch architecture). Timing
figure Write to Write (Burst Length = 4) on page 29 shows
concatenated bursts of 4. An example of nonconsecutive
Writes is shown in timing figure Write to Write: Max DQSS,
Non-Consecutive (Burst Length = 4) on page 30. Fullspeed
random write accesses within a page or pages can be
performed as shown in timing figure Random Write Cycles
(Burst Length = 2, 4 or 8) on page 31.
Preliminary (September, 2005, Version 0.0)
In the case of a Write burst being executed to completion, a
Precharge command issued at the optimum time (as
described above) provides the same operation that would
result from the same burst with Auto Precharge. The
disadvantage of the Precharge command is that it requires
that the command and address busses be available at the
appropriate time to issue the command. The advantage of
the Precharge command is that it can be used to truncate
bursts.
26
AMIC Technology, Corp.
A48P4616
Write Command
Preliminary (September, 2005, Version 0.0)
27
AMIC Technology, Corp.
A48P4616
Write Burst (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
28
AMIC Technology, Corp.
A48P4616
Write to Write (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
29
AMIC Technology, Corp.
A48P4616
Write To Write: Max DQSS, Non-Consecutive (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
30
AMIC Technology, Corp.
A48P4616
Random Write Cycles (Burst Length = 2, 4 or 8)
.
Preliminary (September, 2005, Version 0.0)
31
AMIC Technology, Corp.
A48P4616
Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
32
AMIC Technology, Corp.
A48P4616
Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)
Preliminary (September, 2005, Version 0.0)
33
AMIC Technology, Corp.
A48P4616
Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting
(CAS Latency = 2; Burst Length = 8)
Preliminary (September, 2005, Version 0.0)
34
AMIC Technology, Corp.
A48P4616
Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)
Preliminary (September, 2005, Version 0.0)
35
AMIC Technology, Corp.
A48P4616
Write to Precharge: Non-Interrupting (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
36
AMIC Technology, Corp.
A48P4616
Write to Precharge: Interrupting (Burst Length = 4 or 8)
Preliminary (September, 2005, Version 0.0)
37
AMIC Technology, Corp.
A48P4616
Write to Precharge: Minimum DQSS, Odd Number of Data (1 bit Write), Interrupting (Burst Length = 4 or 8)
Preliminary (September, 2005, Version 0.0)
38
AMIC Technology, Corp.
A48P4616
Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8)
Preliminary (September, 2005, Version 0.0)
39
AMIC Technology, Corp.
A48P4616
Precharge
The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) is
available for a subsequent row access some specified time (tRP) after the Precharge command is issued. Input A10 determines
whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1
select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated prior to any Read or Write commands being issued to that bank.
Precharge Command
Preliminary (September, 2005, Version 0.0)
40
AMIC Technology, Corp.
A48P4616
Power Down
Power Down is entered when CKE is registered low (no
accesses can be in progress). If Power Down occurs when
all banks are idle, this mode is referred to as Precharge
Power Down; if Power Down occurs when there is a row
active in any bank, this mode is referred to as Active Power
Down. Entering Power Down deactivates the input and
output buffers, excluding CK, CK and CKE. The DLL is still
running in Power Down mode, so for maximum power
savings, the user has the option of disabling the DLL prior to
entering Power Down. In that case, the DLL must be enabled
after exiting Power Down, and 200 clock cycles must occur
before a Read command can be issued.
Preliminary (September, 2005, Version 0.0)
In Power Down mode, CKE Low and a stable clock signal
must be maintained at the inputs of the DDR SDRAM, and all
other input signals are “Don’t Care”. However, Power Down
duration is limited by the refresh requirements of the device,
so in most applications, the self refresh mode is preferred
over the DLL-disabled Power Down mode.
The Power Down state is synchronously exited when CKE is
registered high (along with a Nop or Deselect command). A
valid, executable command may be applied one clock cycle
later.
41
AMIC Technology, Corp.
A48P4616
Power Down
Preliminary (September, 2005, Version 0.0)
42
AMIC Technology, Corp.
A48P4616
Truth Table 2: Clock Enble(CKE)
Current
CKE n-1
CKE n
Command n
Action n
Note
Previous Cycle Previous Cycle
Self Refresh
L
L
X
Maintain Self-Refresh
Self Refresh
L
H
Deselect or NOP
Exit Self-Refresh
Power Down
L
L
X
Maintain Power Down
Power Down
L
H
Deselect or NOP
Exit Power Down
All Banks Idle
H
L
Deselect or NOP
Precharge Power Down Entry
All Banks Idle
H
L
Auto Refresh
Self Refresh Entry
Bank(s) Active
H
L
Deselect or NOP
Active Power Down Entry
H
H
1
See “Truth Table 3: Current State
Bank n - Command to Bank n
(Same Bank)” on page 44
Note:
1. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. Command n is the command registered at clock edge n, and action n is a result of command n.
4. All states and sequences not shown are illegal or reserved.
5. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A
minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
Preliminary (September, 2005, Version 0.0)
43
AMIC Technology, Corp.
A48P4616
Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)
Current State
Any
Idle
Row Active
Read
(Auto Precharge
Disabled)
Write
(Auto Precharge
Disabled)
CS
RAS
CAS
WE
Command
H
X
X
X
Deselect
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
H
L
H
L
H
H
H
L
H
H
L
L
L
L
H
L
H
H
L
L
H
H
H
H
L
H
L
L
H
L
L
H
L
L
No Operation
Active
Auto Refresh
Mode Register Set
Read
Write
Precharge
Read
Precharge
Burst Terminate
Read
Write
Precharge
Action
NOP. Continue previous operation
NOP. Continue previous operation
Select and Activate Row
Select column and start Read Burst
Select column and start Write Burst
Deactivate row in bank(s)
Select column and start new Read Burst
Burst Terminate
Select column and start Read Burst
Select column and start Write Burst
Truncate Write burst, start Precharge
Note
1-6
1-6
1-6
1-7
1-7
1-6, 10
1-6, 10
1-6, 8
1-6, 10
1-6, 8
1-6, 9
1-6, 10, 11
1-6, 10
1-6, 8, 11
Note:
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD
has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are
those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses
are in progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank.
Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle
state.
Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the
“row active” state.
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when
tRP has been met. Once tRP is met, the bank is in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when
tRP has been met. Once tRP is met, the bank is in the idle state.
Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during
these states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4.
5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on
each positive clock edge during these states.
Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR
SDRAM is in the “all banks idle” state.
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once
tMRD is met, the DDR SDRAM is in the “all banks idle” state.
Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in
the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
9. Not bank-specific; Burst terminate affects the most recent Read burst, regardless of bank.
10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or
Writes with Auto Precharge disabled.
11. Requires appropriate DM masking.
Preliminary (September, 2005, Version 0.0)
44
AMIC Technology, Corp.
A48P4616
Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
Current State
Any
Idle
Row Activating,
Active, or
Precharging
Read
(Auto Precharge
Disabled)
Write
(Auto Precharge
Disabled)
CS
RAS
CAS
WE
Command
H
X
X
X
Deselect
L
H
H
H
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
H
L
L
H
H
L
H
L
L
H
H
L
H
H
L
L
H
H
H
L
L
H
H
L
H
H
L
L
No Operation
Any Command Otherwise
Allowed to Bank m
Active
Read
Write
Precharge
Active
Read
Precharge
Active
Read
Write
Precharge
Action
NOP/Continue previous operation
NOP/Continue previous operation
Note
1-6
1-6
1-6
Select and Activate Row
Select column and start Read Burst
Select column and start Write Burst
Select and Activate Row
Select column and start new Read Burst
Select and Activate Row
Select column and start Read Burst
Select column and start new Write Burst
1-6
1-7
1-7
1-6
1-6
1-7
1-6
1-6
1-8
1-7
1-6
Note:
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD
has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands
shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is
allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses
are in progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.
4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.
5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or
Writes with Auto Precharge disabled.
8. Requires appropriate DM masking.
9. A Write command may be applied after the completion of data output.
10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the
access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst
was executed with Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses
all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if
Auto Precharge was disabled. The access period starts with registration of the command and ends where the precharge period
(or tRP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled
states, Active, Precharge, Read, and Write commands to the other bank may be applied; during the access period, only Active
and Precharge commands to the other bank may be applied. In either case, all other related limitations apply (e.g. contention
between Read data and Write data must be avoided).
Preliminary (September, 2005, Version 0.0)
45
AMIC Technology, Corp.
A48P4616
Truth Table 4: Current State Bank n - Command to Bank m (Different bank) (continued)
Current State
Read
(With Auto
Precharge)
Write
(With Auto
Precharge)
CS
RAS
CAS
WE
Command
L
L
L
L
L
L
L
L
L
H
H
L
L
H
H
L
H
L
L
H
H
L
L
H
H
H
L
L
H
H
L
L
Active
Read
Write
Precharge
Active
Read
Write
Precharge
Action
Select and Activate Row
Select column and start new Read Burst
Select column and start Write Burst
Select and Activate Row
Select column and start Read Burst
Select column and start new Write Burst
Note
1-6
1-7, 10
1-7, 9, 10
1-6
1-6
1-7, 10
1-7, 10
1-6
Note:
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD
has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands
shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is
allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses
are in progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.
4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.
5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or
Writes with Auto Precharge disabled.
8. Requires appropriate DM masking.
9. A Write command may be applied after the completion of data output.
10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the
access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst
was executed with Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses
all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if
Auto Precharge was disabled. The access period starts with registration of the command and ends where the precharge period
(or tRP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled
states, Active, Precharge, Read, and Write commands to the other bank may be applied; during the access period, only Active
and Precharge commands to the other bank may be applied. In either case, all other related limitations apply (e.g. contention
between Read data and Write data must be avoided).
Preliminary (September, 2005, Version 0.0)
46
AMIC Technology, Corp.
A48P4616
Simplified State Diagram
Preliminary (September, 2005, Version 0.0)
47
AMIC Technology, Corp.
A48P4616
Absolute Maximum Ratings*
Symbol
VIN, VOUT
Parameter
Rating
−
Voltage on I/O pins relative to VSS
Unit
0.5 to VDDQ+ 0.5
V
VIN
Voltage on Inputs relative to VSS
-0.5 to +3.6
V
VDD
Voltage on VDD supply relative to VSS
-0.5 to +3.6
V
VDDQ
Voltage on VDDQ supply relative to VSS
-0.5 to +3.6
V
0 to +70
°C
-55 to +150
°C
TA
TATG
Operating Temperature (Ambient)
Storage Temperature (Plastic)
PD
Power Dissipation
1.0
W
IOUT
Short Circuit Output Current
5.0
mA
Notes: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
DQS/DQ/DM Slew Rate
Parameter
DCS/DQ/DM
Slew Rate
DDR333
DDR400
(6K)
(5T)
Symbol
DCSLEW
Min
Max
Min
Max
TBD
TBD
TBD
TBD
Unit
Note
V/ns
1.2
Notes: 1. Measured between V IH (DC), V IL (DC), and V IL (DC), V IH (DC).
2. DQS, DQ, and DM input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transition through the DC region must be monotonic.
Capacitance
Parameter
Input Capacitance: CK, CK
Symbol
Min
Max
Unit
Note
CI1
2.0
3.0
pF
1
0.25
pF
1
3.0
pF
1
0.5
pF
1
5.0
pF
1.2
0.5
pF
1
Delta CI1
Delta Input Capacitance: CK, CK
Input Capacitance: All Other Input-only pins (except DM)
CI2
Delta Input Capacitance: All Other Input-only pins (except DM)
Input/Output Capacitance: DQ, DQS, DM
Delta CI2
CI/O
Delta Input/Output Capacitance: DQ, DQS, DM
2.0
Delta CI/O
4.0
Notes:
1. VDDQ = VDD = 2.5V ± 0.2V (minimum range to maximum range), f = 100MHz, TA = 25°C, VODC = VDDQ/2, VOPeak -Peak = 0.2V.
2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.
This is required to match input propagation times of DQ, DQS and DM in the system.
Preliminary (September, 2005, Version 0.0)
48
AMIC Technology, Corp.
A48P4616
DC Electrical Characteristics and Operating Conditions
(0°C £ TA £ 70×C; VDDQ = 2.5V ± 0.2V, VDD = + 2.5V ± 0.2V, see AC Characteristics)
Symbol
Parameter
Min
Max
Unit Note
VDD
Supply Voltage
2.3
2.7
V
1
VDDQ
I/O Supply Voltage
2.3
2.7
V
1
0
0
V
VSS, VSSQ
Supply Voltage
I/O Supply Voltage
VREF
I/O Reference Voltage
0.49 x VDDQ
0.51 x VDDQ
V
1.2
VTT
I/O Termination Voltage (System)
VREF + 0.04
VREF + 0.04
V
1.3
VIH (DC)
Input High (Logic 1) Voltage
VREF + 0.15
VDDQ + 0.3
V
1
VIL (DC)
Input Low (logic 0) Voltage
- 0.3
VREF - 0.15
V
1
VIN (DC)
Input Voltage Level, CK and CK Inputs
- 0.3
VDDQ + 0.3
V
1
VID (DC)
Input Differential Voltage, CK and CK Inputs
0.30
VDDQ + 0.6
V
1.4
VIX (DC)
Input Crossing Point Voltage, CK and CK Inputs
0.30
VDDQ + 0.6
V
1.4
VIRatio
V-I Matching Pulup Current to Puldown Current Ratio
0.71
1.4
-5
5
μA
1
-5
5
μA
1
μA
1
Input Leakage Current
II
Any Input 0V ≤ VOUT ≤ VDD; (All other pins not under test = 0V)
IOZ
Output Leakage Current
(DQs are disabled; 0V ≤ VOUT ≤ VDDQ
IOH
Output Current: Nominal Strength Driver
- 16.8
High current (VOUT= VDDQ -0.373V, min VREF, min VTT)
IOL
5
Low current (VOUT= 0.373V, max VREF, max VTT)
16.8
Notes:
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peakto-peak noise on VREF may not exceed ± 2% of the DC value.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF.
4. VID is the magnitude of the difference between the input level on CK and the input level on CK .
5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents
the maximum difference between pullup and pulldown drivers due to process variation.
Preliminary (September, 2005, Version 0.0)
49
AMIC Technology, Corp.
A48P4616
DC Electrical Characteristics and Operating Conditions
(0°C £ TA £ 70×C; VDDQ = 2.5V ± 0.2V, VDD = + 2.5V ± 0.2V, see AC Characteristics)
Symbol
IOHW
Parameter
Min
Output Current: Half- Strength Driver
Unit
Note
mA
1
- 9.0
High current (VOUT= VDDQ -0.763V, min VREF, min VTT)
IOLW
Max
Low current (VOUT= 0.763V, max VREF, max VTT)
9.0
Notes:
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peakto-peak noise on VREF may not exceed ± 2% of the DC value.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF.
4. VID is the magnitude of the difference between the input level on CK and the input level on CK .
5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents
the maximum difference between pullup and pulldown drivers due to process variation.
Preliminary (September, 2005, Version 0.0)
50
AMIC Technology, Corp.
A48P4616
Normal Strength Driver Pulldown and Pullup Characteristics
1. The full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the
outer bounding lines of the V-I curve.
2. It is recommended that the “typical” IBIS pulldown V-I curve lie within the shaded region of the V-I curve.
3. The full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve.
4. It is recommended that the “typical” IBIS pullup V-I curve lie within the shaded region of the V-I curve.
5. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to
source voltages from 0.1 to 1.0.
6. The full variation in the ratio of the “typical” IBIS pullup to “typical” IBIS pulldown current should be unity ± 10%, for device
drain to source voltages from 0.1 to 1.0. This specification is a design objective only. It is not guaranteed.
7. These characteristics are intended to obey the SSTL_2 class II standard.
8. This specification is intended for DDR SDRAM only.
Preliminary (September, 2005, Version 0.0)
51
AMIC Technology, Corp.
A48P4616
Normal Strength Driver Pulldown and Pullup Currents
Pulldown Current (mA)
Voltage (V)
Typical Low Tycpial High
Min
Pullup Current (mA)
Max
Tycpial Low Tycpial High
Min
Max
0.1
6.0
6.8
4.6
9.6
-6.1
-7.6
-4.6
-10.0
0.2
12.2
13.5
9.2
18.2
-12.2
-14.5
-9.2
-20.0
0.3
18.1
20.1
13.8
26.0
-18.1
-21.2
-13.8
-29.8
0.4
24.1
26.6
18.4
33.9
-24.0
-27.7
-18.4
-38.8
0.5
29.8
33.0
23.0
41.8
-29.8
-34.1
-23.0
-46.8
0.6
34.6
39.1
27.7
49.4
-34.3
-40.5
-27.7
-54.4
0.7
39.4
44.2
32.2
56.8
-38.1
-46.9
-32.2
-61.8
0.8
43.7
49.8
36.8
63.2
-41.1
-53.1
-36.0
-69.5
0.9
47.5
55.2
39.6
69.9
-43.8
-59.4
-38.2
-77.3
1.0
51.3
60.3
42.6
76.3
-46.0
-65.5
-38.7
-85.2
1.1
54.1
65.2
44.8
82.5
-47.8
-71.6
-39.0
-93.0
1.2
56.2
69.9
46.2
88.3
-49.2
-77.6
-39.2
-100.6
1.3
57.9
74.2
47.1
93.8
-50.0
-83.6
-39.4
-108.1
1.4
59.3
78.4
47.4
99.1
-50.5
-89.7
-39.6
-115.5
1.5
60.1
82.3
47.7
103.8
-50.7
-95.5
-39.9
-123.0
1.6
60.5
85.9
48.0
108.4
-51.0
-101.3
-40.1
-130.4
1.7
61.0
89.1
48.4
112.1
-51.1
-107.1
-40.2
-136.7
1.8
61.5
92.2
48.9
115.9
-51.3
-112.4
-40.3
-144.2
1.9
62.0
95.3
49.1
119.6
-51.5
-118.7
-40.4
-150.5
2.0
62.5
97.2
49.4
123.3
-51.6
-124.0
-40.5
-156.9
2.1
62.9
99.1
49.6
126.5
-51.8
-129.3
-40.6
-163.2
2.2
63.3
100.9
49.8
129.5
-52.0
-134.6
-40.7
-169.6
2.3
63.8
101.9
49.9
132.4
-52.2
-139.9
-40.8
-176.0
2.4
64.1
102.8
50.0
135.0
-52.3
-145.2
-40.9
-181.3
2.5
64.6
103.8
50.2
137.3
-52.5
-150.5
-41.0
-187.6
2.6
64.8
104.6
50.4
139.2
-52.7
-155.3
-41.1
-192.9
2.7
65.0
105.4
50.5
140.8
-52.8
-160.1
-41.2
-198.2
Normal Strength Driver Evaluation Conditions
typical
Minimum
Maximum
Temperature (Tambient)
25 °C
70 °C
0 °C
VDDQ
2.5V
2.3V
2.7V
Process conditions
Typical process
Slow-slow process
Fast-fast process
Preliminary (September, 2005, Version 0.0)
52
AMIC Technology, Corp.
A48P4616
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD
Specifications and Conditions, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to
VREF (or to the crossing point for CK, CK ), and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a
result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below)
the DC input low (high) level.
AC Output Load Circuit Diagrams
Preliminary (September, 2005, Version 0.0)
53
AMIC Technology, Corp.
A48P4616
AC Input Operating Conditions
(0 °C ≤ TA ≤ 70 °C; VDD = VDDQ = 2.5V ± 0.2V (DDR333); VDD = VDDQ = 2.6V ± 0.1V (DDR400), See AC Characteristics)
Symbol
Parameter/Condition
Min
VIH (AC)
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals
VIL (AC)
Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals
VID (AC)
Input Differential Voltage, CK and CK Inputs
VIX (AC)
Input Crossing Point Voltage, CK and CK Inputs
Max
Unit
Note
V
1, 2
VREF – 0.31
V
1, 2
0.7
VDDQ + 0.6
V
1, 2, 3
0.5*VDDQ – 0.2
0.5* VDDQ + 0.2
V
1, 2, 4
VREF + 0.31
Notes: 1. Input slew rate = 1V/ns.
2. Inputs are not recognized as valid until VREF stabilizes.
3. VID is the magnitude of the difference between the input level on CK and the input level on CK .
4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of
the same.
IDD Specifications and Conditions
(0 °C ≤ TA ≤ 70 °C; VDD = VDDQ = 2.5V ± 0.2V(DDR333); VDD = VDDQ = 2.6V ± 0.1V (DDR400), See AC Characteristics)
Parameter/Condition
Symbol
IDD0
IDD1
IDD2P
IDD2N
IDD3P
Operating Current: One bank; active / precharge; tRC = tRC (min);
DQ, DM, and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating Current: One bank; active / read / precharge; Burst =
2; tRC = tRC (min); CL = 2.5; IOUT = 0mA; address and control inputs
changing once per clock cycle
Precharge Power Down Standby Current: All banks idle;
Power Down mode; CKE ≤ VIL (max)
Idle Standby Current: CS ≥ VIH (min); all banks idle; CKE ≥ VIH
address and control inputs changing once per clock cycle
Active Power Down Standby Current: one bank active; Power
Down mode; CKE ≤ VIL (max)
(min);
DDR333 (6K)
tCK = 6ns
DDR333
(6KL)
tCK = 6ns
DDR400 (5T)
tCK = 5.0ns
68
68
76
mA
1
72
72
79
mA
1
4
4
4
mA
1
25
25
29
mA
1
10
10
11
mA
1
39
39
46
mA
1
87
87
105
mA
1
98
98
119
mA
1
Unit Note
Active Standby Current: One bank; active / precharge; CS ≥
IDD3N
IDD4R
IDD4W
VIH (min); CKE ≥ VIH (min); tRC = tRAS (max); DQ, DM, and DQS
inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
Operating Current: One bank; Burst = 2; reads; continuous
burst; address and control inputs changing once per clock cycle;
DQ and DQS outputs changing twice per clock cycle; CL = 2.5;
IOUT = 0mA
Operating Current: One bank; Burst = 2; writes; continuous
burst; address and control inputs changing once per clock cycle;
DQ and DQS inputs changing twice per clock cycle; CL = 2.5
IDD5
Auto-Refresh Current: tRC = tRFC (min)
118
118
124
mA
1
IDD6
Self-Refresh Current: CKE ≤ 0.2V
2
1.5
2
mA
1.2
IDD7
Operating current: Four bank; four bank interleaving with BL =
4, address and control inputs randomly changing; 50% of data
changing at every transfer; tRC = t RC (min); IOUT = 0mA.
207
207
246
mA
1
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Enables on-chip refresh and address counters.
Preliminary (September, 2005, Version 0.0)
54
AMIC Technology, Corp.
A48P4616
Electrical Characteristics & AC Timing - Absolute Specifications
(0 °C ≤ TA ≤ 70 °C; VDD = VDDQ = 2.5V ± 0.2V (DDR333); VDD = VDDQ = 2.6V ± 0.1V (DDR400), See AC Characteristics)
Symbol
tAC
DDR333 (6K)
Parameter
DQ output access time from CK/ CK
tDQSCK DQS output access time from CK/ CK
DDR400 (5T)
Unit
Note
+0.65
ns
1-4
-0.55
+0.55
ns
1-4
Min
Max
Min
Max
-0.70
+0.70
-0.65
-0.60
+0.60
tCH
CK high-level width
0.45
0.55
0.45
0.55
tCK
1-4
tCL
CK low-level width
0.45
0.55
0.45
0.55
tCK
1-4
7.5
12
-
-
CL = 2.5
6
12
6
12
ns
1-4
CL = 3
-
-
5
8
CL = 2
tCK
Clock cycle time
tDH
DQ and DM input hold time
0.45
0.40
ns
1-4, 15, 16
tDS
DQ and DM input setup time
0.45
0.40
ns
1-4, 15, 16
tIPW
Input pulse width
2.2
2.2
ns
2-4,12
tDIPW
DQ and DM input pulse width (each input)
1.75
1.75
ns
1-4
tHZ
Data-out high-impedance time from CK/ CK
-0.7
+0.7
-0.65
+0.65
ns
1-4,5
tLZ
Data-out low-impedance time from CK/ CK
-0.7
+0.7
-0.65
+0.65
ns
1-4,5
+0.40
ns
1-4
tDQSQ
tHP
DQS-DQ skew
(DQS & associated DQ signals)
TSOP Package
Minimum half clk period for any given cycle;
Defined by clk high (tCH) or low (tCL) time.
+0.45
min tCL, tCH
min tCL, tCH
tCK
1-4
tHP, tQHS
tHP, tQHS
tCK
1-4
0.5
tCK
1-4
1.25
tCK
1-4
tQH
Data output hold time from DQS
tQHS
Data hold Skew Factor
tDQSS
Write command to 1st DQS latching transition
0.75
tDQSH
DQS input high pulse width (write cycle)
0.35
0.35
tCK
1-4
tDQSL
DQS input low pulse width (write cycle)
0.35
0.35
tCK
1-4
tDSS
DQS falling edge to CK setup time (write cycle)
0.2
0.2
tCK
1-4
tDSH
DQS falling edge hold time from CK (write cycle)
0.2
0.2
tCK
1-4
tMRD
Mode register set command cycle time
12
12
tCK
1-4
0
0
tCK
1-4,7
tCK
1-4,6
TSOP Package
0.55
tWPRES Write preamble setup time
1.25
tWPST
Write postamble
0.40
tWPRE
Write postamble
0.25
0.25
tCK
1-4
tIH
Address and control input hold time (fast slew rate)
0.75
0.6
ns
2-4,9,11,12
tIS
Address and control input hold time (fast slew rate)
0.75
0.6
ns
2-4,9,11,12
Preliminary (September, 2005, Version 0.0)
55
0.60
0.72
0.40
0.60
AMIC Technology, Corp.
A48P4616
Electrical Characteristics & AC Timing - Absolute Specifications (continued)
(0 °C ≤ TA ≤ 70 °C; VDD = VDDQ = 2.5V ± 0.2V (DDR333); VDD = VDDQ = 2.6V ± 0.1V (DDR400), See AC Characteristics)
DDR333
6K
Parameter
Symbol
Min
tRCD
Address and control input hold time
(slow slew rate)
Address and control input setup time
(slow slew rate)
Read preamble
Read postamble
Active to Precharge
Active to Active/Auto-refresh command period
Auto-refresh to Active/Auto-refresh command
period
Active to Read or write dalay
tRAP
Active to read command with Autoprecharge
tRP
tRRD
tWR
tDAL
tWTR
tPDEX
tXSNR
tXSRD
Precharge command period
Active bank A to Active bank B command
Write vecovery time
Auto precharge write recovery + precharge time
Intemal write to read command delay
Power down exit time
Exit self-refresh to non-read command
tREFI
Average Periodic Refresh Interval
tIH
tIH
tRPRE
tRPST
tRAS
tRC
tRFC
Exit self-refresh to read command
Max
DDR400
5T
Min
Unit
Note
Max
0.8
0.65
ns
2-4,10,11,
12,14
0.8
0.65
ns
2-4,10,11,
12,14
tCK
tCK
ns
ns
1-4
1-4
1-4
1-4
0.9
0.40
40
60
1.1
0.60
70K
0.9
2.0
42
55
1.1
0.6
70K
72
70
tCK
1-4
18
min
(tRCD, tRAS)
18
12
15
1
6
75
200
15
min
(tRCD, tRAS)
15
10
15
2
6
75
200
tCK
1-4
tCK
1-4
tCK
tCK
tCK
tCK
tCK
ns
tCK
tCK
μs
1-4
1-4
1-4
1-4,13
1-4
1-4
1-4
7.8
7.8
1-4
1-4,8
Notes:
1. Input slew rate = 1V/ns.
2. The CK/ CK input reference level (for timing reference to CK/ CK ) is the point at which CK and CK cross; the input reference
level for signals other than CK/ CK is VREF.
3. Inputs are not recognized as valid until VREF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT.
5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to
a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A
valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS
could be HIGH, LOW, or transitioning from high to low at this time, depending on tDQSS.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate ≥ 1.0V/ns. Slew rate is measured between VOH (AC) and VOL (AC).
10. For command/address input slew rate ≥ 0.5V/ns and < 1.0V/ns. Slew rate is measured between VOH (AC) and VOL (AC).
Preliminary (September, 2005, Version 0.0)
56
AMIC Technology, Corp.
A48P4616
Electrical Characteristics & AC Timing - Absolute Specifications (continued)
11. CK/ CK slew rates are ≥ 1.0V/ns.
12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be
guaranteed by design or tester characterization.
13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. tCK is equal to the actual
system clock cycle time. For example, for DDR266B at CL = 2.5, tDAL = (15ns/7.5ns) + (20ns/7.5ns) = 2 + 3 = 5.
14. An input setup and hold time derating table is used to increase tIS and tIH in the case where the input slew rate is below 0.5
V/ns.
Input Slew Rate
Delta (tIS)
Delta (tIH)
Unit
Note
0.5 V/ns
0
0
ps
1, 2
0.4 V/ns
+50
0
ps
1, 2
0.3 V/ns
+100
0
ps
1, 2
1. Input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising
transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
15. An input setup and hold time derating table is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5
V/ns.
Input Slew Rate
Delta (tDS)
Delta (tDH)
Unit
Note
0.5 V/ns
0
0
ps
1, 2
0.4 V/ns
+75
+75
ps
1, 2
0.3 V/ns
+150
+150
ps
1, 2
1. I/O slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising
transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
16. An I/O Delta Rise, Fall Derating table is used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ.
Input Slew Rate
Delta (tDS)
Delta (tDH)
Unit
Note
0.0 V/ns
0
0
ps
1, 2, 3, 4
0.25 V/ns
+50
+50
ps
1, 2, 3, 4
0.5 V/ns
+100
+100
ps
1, 2, 3, 4
1. Input slew rate is based on the lesser of the slew rates determined by either VIH (AC) to VIL (AC) or VIH (DC) to VIL (DC), similarly for rising
transitions.
2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.
3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns
Delta rise, fall = (1/0.5) - (1/0.4) [ns/V]
= -0.5 ns/V
Using the table above, this would result in an increase in t DS and t DH of 100 ps.
4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
Preliminary (September, 2005, Version 0.0)
57
AMIC Technology, Corp.
A48P4616
Data Input (Write) (Timing Burst Length = 4)
Data Output (Read) (Timing Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
58
AMIC Technology, Corp.
A48P4616
Initialize and Mode Register Sets
Preliminary (September, 2005, Version 0.0)
59
AMIC Technology, Corp.
A48P4616
Power Down Mode
Preliminary (September, 2005, Version 0.0)
60
AMIC Technology, Corp.
A48P4616
Auto Refresh Mode
Preliminary (September, 2005, Version 0.0)
61
AMIC Technology, Corp.
A48P4616
Self Refresh Mode
Preliminary (September, 2005, Version 0.0)
62
AMIC Technology, Corp.
A48P4616
Read without Auto Precharge (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
63
AMIC Technology, Corp.
A48P4616
Read with Auto Precharge (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
64
AMIC Technology, Corp.
A48P4616
Bank Read Access (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
65
AMIC Technology, Corp.
A48P4616
Write without Auto Precharge (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
66
AMIC Technology, Corp.
A48P4616
Write with Auto Precharge (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
67
AMIC Technology, Corp.
A48P4616
Bank Write Access (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
68
AMIC Technology, Corp.
A48P4616
Write DM Operation (Burst Length = 4)
Preliminary (September, 2005, Version 0.0)
69
AMIC Technology, Corp.
A48P4616
Package Dimensions (400mil; 66 lead TSOP Package)
Preliminary (September, 2005, Version 0.0)
70
AMIC Technology, Corp.