LP61L1024 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM Document Title 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM Revision History Rev. No. History Issue Date Remark 2.0 Add product family and 32-pin TSSOP package May 9, 2002 Final 2.1 Add 36 ball BGA package type August 22, 2002 (August, 2002, Version 2.1) AMIC Technology, Inc. LP61L1024 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM Features General Description n Single +3.3V power supply n Access times: 12/15 ns (max.) n Current: Operating: 170mA (max.) Standby: 10mA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2.0V (min.) n Available in 32-pin SOJ 300 mil, 32-pin TSOP and 32pin TSSOP and 36-pin CSP packages The LP61L1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2.0V. Product Family Product Family Operating Temperature VCC Range Power Dissipation Speed Data Retention (ICCDR, Typ.) Standby (ISB1, Typ.) Operating (ICC1, Typ.) Package Type 32L SOJ 32L TSOP LP61L1024 0°C ~ 70°C 3V ~ 3.6V 12/15 ns 0.4mA 0.5mA 130mA 32L TSSOP 36B µBGA 1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested. 2. Data retention current VCC = 2.0V. (August, 2002, Version 2.1) 1 AMIC Technology, Inc. LP61L1024 Pin Configurations n SOJ n TSOP / TSSOP n CSP (Chip Size Package) 36-pin Top View 1 32 VCC 2 31 A15 A14 3 30 CE2 1 2 3 4 5 6 A12 4 29 WE A A0 A1 NC A3 A6 A8 A7 5 28 A13 B I/O4 A2 WE A4 A7 I/O0 A6 6 27 A8 A5 A5 26 A9 NC 7 8 A3 9 A2 10 A1 11 25 A11 24 OE 23 A10 22 CE1 16 1 LP61L1024V(X) A4 LP61L1024S NC A16 C I/O5 D GND E VCC F I/O6 I/O1 VCC GND NC NC I/O2 A0 12 21 I/O8 G I/O7 OE CE1 A16 A15 I/O3 I/O1 13 20 I/O7 H A9 A10 A11 A12 A13 A14 I/O2 14 19 I/O6 I/O3 15 18 I/O5 GND 16 17 I/O4 32 17 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name A3 A2 A1 A0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 I/O8 CE1 A10 OE Block Diagram Pin Description VCC GND A0 Pin No. Symbol Description 2 - 12, 23, 25 - 28, 31 A0 - A16 29 WE Write Enable 24 OE Output Enable 22 CE1 Chip Enable 30 CE2 Chip Enable 1 NC No Connection 13 - 15, 17 - 21 I/O1 - I/O8 32 VCC Power Supply 16 GND Ground Address Inputs 256 X 4096 DECODER MEMORY ARRAY A14 A15 A16 I/O1 INPUT DATA CIRCUIT COLUMN I/O I/O8 CE2 CE1 OE Data Input/Outputs CONTROL CIRCUIT WE (August, 2002, Version 2.1) 2 AMIC Technology, Inc. LP61L1024 Recommended DC Operating Conditions (TA = 0°C to + 70°C) Symbol Parameter VCC Supply Voltage GND Ground Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 0 0 V VIH Input High Voltage 2.2 - VCC + 0.3 V VIL Input Low Voltage -0.3 0 +0.8 V CL Output Load - - 30 pF TTL Output Load - - 1 - Absolute Maximum Ratings* *Comments VCC to GND .............................................. -0.5V to +7.0V IN, IN/OUT Volt to GND .....................-0.5V to VCC +0.5V Operating Temperature, Topr ...................... 0°C to +70°C Storage Temperature, Tstg..................... -55°C to +125°C Temperature Under Bias, Tbias................ -10°C to +85°C Power Dissipation, Pt................................................1.0W Soldering Temp. & Time .............................260°C, 10 sec Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Symbol (TA = 0°C to + 70°C, VCC = 3.3V + 10%, GND = 0V) Parameter LP61L1024-12/15 Min. Max. Unit Conditions ILI Input Leakage Current - 2 µA ILO Output Leakage Current - 2 µA Dynamic Operating Current - 170 mA CE1 = VIL, CE2 = VIH II/O = 0 mA - 30 mA CE1 = VIH or CE2 = VIL - 10 mA CE1 ≥ VCC - 0.2V, CE2 ≥ VCC - 0.2V, VIN ≤ 0.2V or VIN ≥ VCC - 0.2V - 10 mA CE1 ≤ 0.2V, CE2 ≤ 0.2V VIN ≤ 0.2V or VIN ≥ VCC - 0.2V ICC1 (1) ISB ISB1 Standby Power Supply Current ISB2 VIN = GND to VCC CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GND to VCC VOL Output Low Voltage - 0.4 V IOL = 8 mA VOH Output High Voltage 2.4 - V IOH = -4 mA Note: 1. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns (August, 2002, Version 2.1) 3 AMIC Technology, Inc. LP61L1024 Truth Table Mode CE1 CE2 OE WE H X X X High Z ISB, ISB1 X L X X High Z ISB, ISB2 Output Disable L H H H High Z ICC1 Read L H L H DOUT ICC1 Write L H X L DIN ICC1 Standby I/O Operation Supply Current Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 8 pF VIN = 0V CI/O* Input/Output Capacitance 10 pF VI/O = 0V * These parameters are sampled and not 100% tested. AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V + 10, GND = 0V) Symbol LP61L1024-12 Parameter LP61L1024-15 Unit Min. Max. Min. Max. 12 - 15 - ns - 12 - 15 ns CE1 - 12 - 15 ns CE2 - 12 - 15 ns - 7 - 9 ns CE1 3 - 5 - ns CE2 3 - 5 - ns 2 - 2 - ns CE1 - 7 - 10 ns CE2 - 7 - 10 ns Read Cycle tRC Read Cycle Time tAA Address Access Time tACE1 Chip Enable Access Time tACE2 tOE tCLZ1 Output Enable to Output Valid Chip Enable to Output in Low Z tCLZ2 tOLZ Output Enable to Output in Low Z tCHZ1 Chip Disable to Output in High Z tCHZ2 tOHZ Output Disable to Output in High Z 2 7 2 9 ns tOH Output Hold from Address Change 3 - 5 - ns (August, 2002, Version 2.1) 4 AMIC Technology, Inc. LP61L1024 AC Characteristics (continued) Symbol LP61L1024-12 Parameter LP61L1024-15 Min. Max. Min. Max. Unit Write Cycle tWC Write Cycle Time 12 - 15 - ns tCW Chip Enable to End of Write 10 - 12 - ns tAS Address Setup Time of Write 0 - 0 - ns tAW Address Valid to End of Write 10 - 12 - ns tWP Write Pulse Width 8 - 10 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z 0 7 0 8 ns tDW Data to Write Time Overlap 8 - 10 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 5 - 5 - ns Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. Timing Waveforms (1, 2, 4) Read Cycle 1 tRC Address tAA tOH tOH DOUT (August, 2002, Version 2.1) 5 AMIC Technology, Inc. LP61L1024 Read Cycle 2 (1, 3, 4, 6) CE1 tACE1 tCLZ15 tCHZ15 DOUT Read Cycle 3 (1, 4, 7, 8) CE2 tACE2 tCHZ25 tCLZ25 DOUT (August, 2002, Version 2.1) 6 AMIC Technology, Inc. LP61L1024 Timing Waveforms (continued) Read Cycle 4 (1) tRC Address tAA OE tOE tOH tOLZ5 CE1 tACE1 tCHZ15 tCLZ25 CE2 tOHZ5 tACE2 tCLZ25 tCHZ25 DOUT Notes: 1. 2. 3. 4. 5. 6. 7. 8. WE is high for Read Cycle. Device is continuously enabled CE1 = VIL and CE2 = VIH. Address valid prior to or coincident with CE1 transition low. OE = VIL. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. CE2 is high. CE1 is low. Address valid prior to or coincident with CE2 transition high. (August, 2002, Version 2.1) 7 AMIC Technology, Inc. LP61L1024 Timing Waveforms (continued) (6) Write Cycle 1 (Write Enable Controlled) tWC Address tAW tWR 3 tCW5 CE1 (4) CE2 (4) tAS1 tWP 2 WE tDW tDH DIN tWHZ tOW DOUT (August, 2002, Version 2.1) 8 AMIC Technology, Inc. LP61L1024 Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address tWR 3 tAW tCW5 CE1 CE2 tAS1 (4) (4) tCW5 tWP 2 WE tDW tDH DIN tWHZ7 DOUT Notes: 1. 2. 3. 4. tAS is measured from the address valid to the beginning of Write. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE . tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE going low or CE2 going high to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. (August, 2002, Version 2.1) 9 AMIC Technology, Inc. LP61L1024 AC Test Conditions Input Pulse Levels 0V to 3.0V Input Rise and Fall Time 3 ns Input and Output Timing Reference Levels 1.5V Output Load See Figures 1 and 2 +3.3V +3.3V 320Ω 320Ω I/O I/O 350Ω 30pF* 350Ω * Including scope and jig. 5pF* * Including scope and jig. Figure 1. Output Load Figure 2. Output Load for tCLZ1, tCLZ2, tOHZ, tOLZ, tCHZ1, tCHZ2, tWHZ, and tOW Data Retention Characteristics (TA = 0°C to 70°C) Symbol Parameter VDR1 Min. Max. Unit 2 3.6 V CE1 ≥ VCC - 0.2V CE2 ≥ VCC - 0.2V or CE2 ≤ 0.2V 2 3.6 V CE2 ≤ 0.2V CE1 ≥ VCC - 0.2V or CE1 ≤ 0.2V mA VCC = 3.0V CE1 ≥ VCC - 0.2V CE2 ≥ VCC - 0.2V VIN ≥ VCC - 0.2V or VIN ≤ 0.2V VCC = 3.0V CE2 ≤ 0.2V CE1 ≤ 0.2V VIN ≥ VCC - 0.2V or VIN ≤ 0.2V VCC for Data Retention VDR2 ICCDR1 5 Data Retention Current ICCDR2 tCDR Chip Disable to Data Retention Time - 5 mA 0 - ns Conditions See Retention Waveform tR Operation Recovery Time (August, 2002, Version 2.1) 5 - 10 ms AMIC Technology, Inc. LP61L1024 Low VCC Data Retention Waveform (1) ( CE1 Controlled) DATA RETENTION MODE VCC 3.0V 3.0V tCDR tR VDR ≥ 2V VIH CE1 VIH CE1 ≥ VDR - 0.2V Low VCC Data Retention Waveform (2) (CE2 Controlled) DATA RETENTION MODE VCC 3.0V 3.0V tCDR CE2 tR VDR ≥ 2V VIL VIL CE2 ≤ 0.2V Ordering Information Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mA) LP61L1024S-12 12 170 10 32L SOJ (300 mil) LP61L1024V-12 12 170 10 32L TSOP LP61L1024X-12 12 170 10 32L TSSOP LP61L1024U-12 12 170 10 36L CSP LP61L1024S-15 15 170 10 32L SOJ (300 mil) LP61L1024V-15 15 170 10 32L TSOP LP61L1024X-15 15 170 10 32L TSSOP LP61L1024U-15 15 170 10 36L CSP Part No. (August, 2002, Version 2.1) 11 Package AMIC Technology, Inc. LP61L1024 Package Information SOJ 32/32LD (300mil BODY) Outline Dimensions unit: inches/mm b D 17 c 32 E F F BASE METAL WITH PLATING DETAIL "A" SECTION F-F 1 16 DETAIL "A" HE s b e D SEATING PLANE Symbol A1 y MIN 0.026" y A A2 b1 e1 0.004 y Dimensions in inches Dimensions in mm Min. Nom. Max. Min. Nom. Max. A 0128 0.132 0.140 3.25 3.35 3.56 A1 0.052 - - 2.08 - - A2 0.095 0.100 0.105 2.41 2.54 2.67 b 0.016 0.018 0.020 0.41 0.46 0.51 b1 0.026 0.028 0.032 0.66 0.71 0.81 c 0.006 0.008 0.012 0.15 0.20 0.30 D 0.820 0.825 0.830 20.83 20.96 21.08 HE 0.330 0.335 0.340 8.39 8.51 8.63 E 0.295 0.300 0.305 7.49 7.62 7.75 e1 0.260 0.267 0.274 6.61 6.78 6.96 e - 0.050 - - 1.27 - s - - 0.048 - - 1.22 y - - 0.004 - - 0.10 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E doesn't include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (August, 2002, Version 2.1) 12 AMIC Technology, Inc. LP61L1024 Package Information TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm e D A c E A2 12.0° A1 GAUGE PLANE 0.25 BSC θ L LE HD Detail "A" D Detail "A" y S Symbol Dimensions in inches Dimensions in mm A 0.047 Max. 1.20 Max. A1 0.004±0.002 0.10±0.05 A2 0.039±0.002 1.00±0.05 b 0.008±0.001 0.20±0.03 c 0.006±0.001 0.15±0.02 D 0.724±0.004 18.40±0.10 E 0.315±0.004 8.00±0.10 e 0.020 TYP. 0.50 TYP. HD 0.787±0.007 20.00±0.20 L 0.020±0.004 0.50±0.10 LE 0.031 TYP. 0.80 TYP. S 0.0167 TYP. 0.425 TYP. Y 0.004 Max. 0.10 Max. θ 0° ~ 6° 0° ~ 6° b 0.10(0.004) M Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. (August, 2002, Version 2.1) 13 AMIC Technology, Inc. LP61L1024 Package Information unit: inches/mm A A1 c E A2 e TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions θ L LE D1 D Detail "A" D Detail "A" 0.076MM S b SEATING PLANE Dimensions in inches Symbol Min Nom Max Dimensions in mm Min Nom Max A - - 0.049 - - 1.25 A1 0.002 - - 0.05 - - A2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.007 0.008 0.009 0.17 0.20 0.23 c 0.0056 0.0059 0.0062 0.142 0.150 0.158 E 0.311 0.315 0.319 7.90 8.00 8.10 e 0.020 TYP 0.50 TYP D 0.520 0.528 0.535 13.20 13.40 13.60 D1 0.461 0.465 0.469 11.70 11.80 11.90 L 0.012 0.020 0.028 0.30 0.50 0.70 LE 0.0275 0.0315 0.0355 0.700 0.800 0.900 S θ 0.0109 TYP 0° 3° 0.278 TYP 5° 0° 3° 5° Notes: 1. The maximum value of dimension D1 includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. (August, 2002, Version 2.1) 14 AMIC Technology, Inc. LP61L1024 Package Information 36LD CSP (6 x 8 mm) Outline Dimensions unit: mm BOTTOM VIEW TOP VIEW Ball#A1 CORNER 0.10 S C 0.25 S C A B Ball*A1 CORNER b (36X) 6 5 4 3 2 1 1 2 3 4 5 6 A B A C D E F G H C D E F G H E E1 e B B A 0.10 C SIDE VIEW D 0.20(4X) A2 SEATING PLANE A1 (0.36) C Symbol A A1 A2 D E D1 E1 e b A // 0.25 C e D1 Dimensions in mm MIN. NOM. MAX. 1.00 0.16 0.48 5.80 7.80 ------0.25 1.10 0.21 0.53 6.00 8.00 3.75 5.25 0.75 0.30 1.20 0.26 0.58 6.20 8.20 ------0.35 Note: 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. 4. THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. (August, 2002, Version 2.1) 15 AMIC Technology, Inc.