CDCF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS628B – APRIL 1999 REVISED NOVEMBER 1999 D D D D D D D D D D D D D PW PACKAGE (TOP VIEW) Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9 Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 140 MHz Static tPhase Error Distribution at 66MHz to 133 MHz is ±125 ps Jitter (cyc – cyc) at 66 MHz to 133 MHz Is |70| ps Available in Plastic 24-Pin TSSOP Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Ten Outputs Output Enable Pin to Enable/Disable All 10 Outputs External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input On-Chip Series Damping Resistors No External RC Network Required Operates at 3.3 V AGND VCC 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VCC G FBOUT 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 CLK AVCC VCC 1Y9 1Y8 GND GND 1Y7 1Y6 1Y5 VCC FBIN description The CDCF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCF2510 operates at 3.3 V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. The outputs can be enabled/disabled with the control (G) input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDCF2510 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDCF2510 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The CDCF2510 is characterized for operation from 0°C to 85°C. For application information refer to application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (literature number SCAA039). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CDCF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS628B – APRIL 1999 REVISED NOVEMBER 1999 FUNCTION TABLE OUTPUTS INPUTS G CLK 1Y (0:9) X L L L L H L H H H H H FBOUT functional block diagram G 11 3 4 5 8 9 15 16 CLK 24 ÎÎÎÎÎÎÎ ÁÁÁÁÁÁ ÎÎÎÎÎÎÎ ÁÁÁÁÁÁ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ 17 PLL FBIN AVCC 13 20 21 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 1Y9 23 12 AVAILABLE OPTIONS PACKAGE 2 1Y0 TA SMALL OUTLINE (PW) 0°C to 85°C CDCF2510PWR POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FBOUT CDCF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS628B – APRIL 1999 REVISED NOVEMBER 1999 Terminal Functions TERMINAL NAME NO. TYPE DESCRIPTION CLK 24 I Clock input. CLK provides the clock signal to be distributed by the CDCF2510 clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FBIN 13 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. G 11 I Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the same frequency as CLK. FBOUT 12 O Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an integrated 25-Ω series-damping resistor. 1Y (0:9) 3, 4, 5, 8, 9, 15, 16, 17, 20, 21 O Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via the G input. These outputs can be disabled to a logic-low state by deasserting the G control input. Each output has an integrated 25-Ω series-damping resistor. AVCC 23 Power Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry. VCC GND 2, 10, 14, 22 Power Power supply 6, 7, 18, 19 Ground Ground POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CDCF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS628B – APRIL 1999 REVISED NOVEMBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, AVCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVCC < VCC +0.7 V Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. AVCC must not exceed VCC. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 4.6 V maximum. 4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. recommended operating conditions (see Note 5) VCC, AVCC Supply voltage VIH High-level input voltage MIN MAX 3 3.6 2 UNIT V V VIL VI Low-level input voltage 0.8 IOH IOL High-level output current VCC –12 mA Low-level output current 12 mA 85 °C Input voltage 0 TA Operating free-air temperature NOTE 5: Unused inputs must be held high or low to prevent them from floating. 0 V V timing requirements over recommended ranges of supply voltage and operating free-air temperature fclk Clock frequency Input clock duty cycle Stabilization time† MIN MAX UNIT 25 140 MHz 40% 60% 1 ms † Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDCF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS628B – APRIL 1999 REVISED NOVEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Input clamp voltage II = –18 mA IOH = –100 µA VOH High-level output voltage IOH = –12 mA IOH = – 6 mA VOL Low-level output voltage IOL = 100 µA IOL = 12 mA VCC, AVCC 3V MIN MIN to MAX 3V VCC–0.2 2.1 3V 2.4 High-level output current UNIT –1.2 V 0.2 3V 0.8 3V 0.55 3.135 V VO = 1.65 V VO = 3.135 V MAX V MIN to MAX IOL = 6 mA VO = 1 V IOH TYP‡ V –32 3.3 V –36 3.465 V –12 Low-level output current VO = 1.95 V VO = 1.65 V 3.135 V IOL 34 14 Input current VO = 0.4 V VI = VCC or GND 3.465 V II 3.6 V ±5 µA 3.6 V 10 µA 3.3 V to 3.6 V 500 µA 3.3 V ICC§ Supply current VI = VCC or GND, Outputs: low or high IO = 0, ∆ICC Change in supply current One input at VCC – 0.6 V, Other inputs at VCC or GND Ci Input capacitance VI = VCC or GND VO = VCC or GND 40 3.3 V Co Output capacitance 3.3 V ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § For ICC of AVCC, and ICC vs Frequency (see Figures 8 and 9). 4 pF 6 pF switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF (see Note 6 and Figures 1 and 2)‡ PARAMETER Phase error time – static (normalized) (See Figures 3 – 6) tsk(o) Output skew time§ Phase error time – jitter (see Note 7) Jitter(cycle (cycle-cycle) cycle) (See Figure 7) Duty cycle FROM (INPUT)/CONDITION TO (OUTPUT) CLKIN↑ = 66 MHz to133 MHz FBIN↑ Any Y or FBOUT Any Y or FBOUT Clkin = 66 MHz to 133 MHz Any Y or FBOUT VCC, AVCC = 3.3 V ± 0.3 V MIN TYP –125 –50 Any Y or FBOUT UNIT MAX 125 ps 200 ps 50 |70| Clkin = 100 MHz to 133 MHz Any Y or FBOUT F(clkin > 60 MHz) Any Y or FBOUT 45% |65| 55% ps ps tr Rise time (See Notes 8 and 9) VO = 1.2 V to 1.8 V, IBIS simulation Any Y or FBOUT 2.5 1 V/ns tf Fall time (See Notes 8 and 9) VO = 1.2 V to 1.8 V, IBIS simulation Any Y or FBOUT 2.5 1 V/ns ‡ These parameters are not production tested. § The tsk(o) specification is only valid for equal loading of all outputs. NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 7. Calculated per PC DRAM SPEC (tphase error, static – jitter(cycle-to-cycle)). 8. This is equivalent to 0.8 ns/2.5 ns and 0.8 ns/2.7 ns into standard 500 Ω/ 30 pf load for output swing of 04. V to 2 V. 9. 64 MB DIMM configuration according to PC SDRAM Registered DIMM Design Support Document, Figure 20 and Table 13. Intel is a trademark of Intel Corporation. PC SDRAM Register DIMM Design Support Document is published by Intel Corporation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CDCF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS628B – APRIL 1999 REVISED NOVEMBER 1999 PARAMETER MEASUREMENT INFORMATION 3V Input 50% VCC 0V tpd From Output Under Test 500 25 pF W Output 2V 0.4 V tr LOAD CIRCUIT FOR OUTPUTS 50% VCC VOH 2V 0.4 V VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 133 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns. C. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms CLKIN FBIN tphase error FBOUT Any Y tsk(o) Any Y Any Y tsk(o) Figure 2. Phase Error and Skew Calculations 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDCF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS628B – APRIL 1999 REVISED NOVEMBER 1999 TYPICAL CHARACTERISTICS PHASE ADJUSTMENT SLOPE AND PHASE ERROR vs LOAD CAPACITANCE 200 VCC = 3.3 V fc = 133 MHz C(LY) = 25pF TA = 25°C See Notes A and B 10 100 0 0 Phase Error –10 –100 –20 –200 –30 –300 Phase Error – ps Phase Adjustment Slope – ps/pF 20 Phase Adjustment Slope –40 –400 0 5 10 15 20 25 30 35 40 45 50 C(LF) – Lumped Feedback Capacitance at FBIN – pF Figure 3 NOTES: A. Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50 Ω Phase error measured from CLK to Y B. CLF = Lumped feedback capacitance at FBIN PHASE ERROR vs CLOCK FREQUENCY PHASE ERROR vs SUPPLY VOLTAGE 0 0 VCC = 3.3 V C(LY) = 25 pF C(LF) = 12 pF TA = 25°C See Note A –50 –150 –100 –150 Phase Error – ps Phase Error – ps –100 –200 –250 –300 –200 –250 –300 –350 –350 –400 –400 –450 –450 –500 fc = 133 MHz C(LY) = 25 pF C(LF) = 12 pF TA = 25°C See Note A –50 50 60 70 80 90 100 110 120 130 140 –500 3 3.1 fc – Clock Frequency – MHz 3.2 3.3 3.4 3.5 3.6 VCC – Supply Voltage – V Figure 4 Figure 5 NOTE A: Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50 Ω POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 CDCF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS628B – APRIL 1999 REVISED NOVEMBER 1999 TYPICAL CHARACTERISTICS STATIC PHASE ERROR vs CLOCK FREQUENCY JITTER vs CLOCK FREQUENCY 300 0 VCC = 3.3 V C(LY) = 25 pF C(LF) = 12 pF TA = 25°C See Note A –50 –150 250 200 Jitter – ps Phase Error – ps –100 VCC = 3.3 V C(LY) = 25 pF C(LF) = 12 pF TA = 25°C See Notes A and B –200 –250 150 –300 Peak to Peak 100 –350 –400 50 Cycle to Cycle –450 –500 50 60 70 80 90 100 110 120 130 0 50 140 60 Figure 6 NOTES: A. B. C. D. 8 70 80 90 Figure 7 Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50 Ω Phase error measured from CLK to FBIN CLY = Lumped capacitive load at Y CLF = Lumped feedback capacitance at FBIN POST OFFICE BOX 655303 100 110 120 130 140 fc – Clock Frequency – MHz fc – Clock Frequency – MHz • DALLAS, TEXAS 75265 CDCF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS628B – APRIL 1999 REVISED NOVEMBER 1999 TYPICAL CHARACTERISTICS ANALOG SUPPLY CURRENT vs CLOCK FREQUENCY SUPPLY CURRENT vs CLOCK FREQUENCY 14 12 10 300 AVCC = VCC = 3.465 V Bias = 0/3 V C(LY) = 25 pf C(LF) = 0 TA = 25°C See Notes A and B 250 I CC – Supply Current – mA AI CC – Analog Supply Current – mA 16 8 6 4 150 100 50 2 0 10 200 AVCC = VCC = 3.465 V Bias = 0/3 V C(LY) = 25 pf C(LF) = 0 TA = 25°C See Notes A and B 30 50 70 90 110 130 150 0 10 30 fc – Clock Frequency – MHz 50 70 90 110 130 150 fc – Clock Frequency – MHz Figure 8 Figure 9 NOTES: A. C(LY) = Lumped capacitive load at Y B. C(LF) = Lumped feedback capacitance at FBIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 CDCF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS628B – APRIL 1999 REVISED NOVEMBER 1999 MECHANICAL INFORMATION PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° 0,75 0,50 A Seating Plane 1,20 MAX 0,10 0,05 MIN PINS ** 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064 / E 08/96 NOTES: A. B. C. D. 10 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated