AMSCO AS8202

AS8202
TTP/C-C2 Communication
Controller
Preliminary Data Sheet
Rev. 1.0, October 2000
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Key Features
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•
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Dedicated controller supporting TTP/C (time triggered protocol class C)
Suited for dependable distributed real-time systems with guaranteed response time
Application fields: Automotive (by-wire braking, steering, vehicle dynamics control, drive
train control), Aerospace (aircraft electronic systems), Industrial systems, Railway systems
TTP/C asynchronous data rate up to 5 MBit/s @ clock 40 MHz, synchronous data rate 25
MBit/s @ clock 40 MHz
Single power supply 3.3V
0.35µm CMOS process
Temperature range: -40°C to 125° C
2k x 16 RAM message, status and control area (communication network interface)
RAM for instruction code and configuration data
16 Bit non-multiplexed host CPU interface
16 Bit RISC architecture
16k x 16 internal FLASH memory for firmware and scheduling information
software tools, design-in support, development boards available ( http://www.tttech.com)
80 pin TQFP Package
General Description
The AS8202 communications controller is an integrated device supporting serial
communication according to the TTP/C specification. It performs all communications tasks such
as reception and transmission of messages in a TTP cluster without interaction of the host
CPU.
TTP provides mechanisms that allow the deployment in high-dependability distributed realtime systems. It provides following services:
•
•
•
•
predictable transmission of messages with minimal jitter
fault-tolerant distributed clock synchronisation
consistent membership service with small delay
masking of single faults
Host
Processor
Interface
ram_data[15:0]
ram_address[11:0]
ram_ceb
ram_oeb
ram_web
ram_readyb
time_signalb
led[0]/time_tick
led[1]/time_overflow
led[2]/microtick
Quartz or
Oscillator
Receiver
Controller
network
interface
(CNI)
xin0
xout0
resetb
plloff
TTP/C
protocol
processor core
Reset &
Time
base
FLASH
memory
Instruction
RAM memory
Bus
guardian
rxd[1:0]
rxclk[1:0]
rxdv[1:0]
rxer[1:0]
TTP/C
Bus Media
Drivers
xin1
xout1
Transmitter
txd[1:0]
cts[1:0]
txclk[1:0]
Network
configuration
memory
(MEDL)
test_se
ftest
stest
fidis
mtest
Test
Interface
Figure 1 AS8202 Block Diagram
Rev. 1.0, October 2000
Page 2 of 2
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
The CNI (communication network interface) forms a temporal firewall. It decouples the
controller network from the host subsystem by use of a dual ported RAM. This prevents the
propagation of control errors. The interface to the host CPU is implemented as 16 bit wide nonmultiplexed asynchronous bus interface.
TTP/C follows a conflict-free media access strategy called time-division-multiple access
(TDMA). This means, TTP/C deploys a time slot technique based on a global time which is
permanently synchronised. Each node is assigned a time slot in which it is allowed to perform
transmit operation. The sequence of time slots is called TDMA round, a set of TDMA rounds
forms a cluster cycle. After one cluster cycle the operation of the network repeats. The
sequence of interactions forming the cluster cycle is defined in a static time schedule, called
message-descriptor-list (MEDL). The definition of the MEDL in conjunction with the global time
determines the response time for a service request.
The membership of all nodes in the network is evaluated by the communication controller. This
information is presented in a consistent fashion to all correct cluster members. During
operation, the status of every other node is propagated within one TDMA round. The MEDL is
loaded into the configuration memory when the system starts up.
P a c k a g e a n d P i n As s i g n m e n t
60
ram-data[7]
ram-data[6]
ram-data[5]
ram-data[4]
ram-data[3]
ram-data[2]
ram-data[1]
ram-data[0]
Vss
Vdd
ram-address[11]
ram-address[10]
ram-address[9]
ram-address[8]
ram-address[7]
ram-address[6]
ram-address[5]
Vss
ram-address[4]
ram-address[3]
Type: TQFP 80, plastic package
41
61
40
Vdd
Vss
ram-data[8]
ram-data[9]
ram-data[10]
ram-data[11]
ram-data[12]
ram-data[13]
ram-data[14]
ram-data[15]
Vdd
Vss
ram-ceb
ram-oeb
ram-web
ram-readyb
to Vss
to Vdd
n.c.
n.c.
80
ram-address[2]
ram-address[1]
ram-address[0]
mtest
led[2]/time-overflow
led[1]/time-tick
led[0]/microtick
Vss
Vdd
time-signalb
resetb
fidis
ftest
plloff
stest
test-se
Vss
xin1
xout1
Vdd
AS8202
TTP/C
Communications
Controller
(TOP VIEW)
1
Vdd
xout0
xin0
Vss
txd[0]
cts[0]
txclk[0]
rxer[0]
rxclk[0]
rxdv[0]
rxd[0]
Vdd
Vss
txd[1]
cts[1]
txclk[1]
rxer[1]
rxclk[1]
rxdv[1]
rxd[1]
21
20
Figure 2 TQFP 80 pin package and pin assignment
Rev. 1.0, October 2000
Page 3 of 3
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Pin Description
Pin
Name
Dir
Description
1,12,21,32,51,61,71
4,13,24,33,43,52,62,72
2
Vdd
Vss
xout0
P
P
O
3
xin0
I
5
6
7
8
9
10
11
14
15
16
17
18
19
20
22
txd[0]
cts[0]
txclk[0]
rxer[0]
rxclk[0]
rxdv[0]
rxd[0]
txd[1]
cts[1]
txclk[1]
rxer[1]
rxclk[1]
rxdv[1]
rxd[1]
xout1
OPU
OPD
IPD
IPU
IPD
IPU
IPU
OPU
OPD
IPD
IPU
IPD
IPU
IPU
O
23
xin1
I
positive power supply
Negative power supply
Main clock: analog pad from oscillator / leave open
when providing external clock
Main clock: analog pad from oscillator / use as input
when providing external clock
Transmit data channel 0
Transmit enable channel 0
TTP/C synchronous: Transmit clock channel 0
TTP/C synchronous: Receive error channel 0
TTP/C synchronous: Receive clock channel 0
TTP/C synchronous: Receive data valid channel 0
Receive data channel 0
Transmit data channel 1
Transmit enable channel 1
TTP/C synchronous: Transmit clock channel 1
TTP/C synchronous: Receive error channel 1
TTP/C synchronous: Receive clock channel 1
TTP/C synchronous: Receive data valid channel 1
Receive data channel 1
Bus guardian clock: analog pad from oscillator / leave
open when providing external clock
Bus guardian clock: analog pad from oscillator / use as
input when providing external clock
25
26
27
28
29
30
31
34
test_se
stest
plloff
ftest
fidis
resetb
time_signalb
led[0]/microtick
IPD
IPD
IPD
IPD
IPD
I
OPU
OPD
35
led[1]/time_tick
OPD
36
led[2]/time_overflow
OPD
37
38-42,44-50
53-60,63-70
73
74
75
76
77
78
79
80
mtest
ram_address[0:11]
ram_data[0:15]
ram_ceb
ram_oeb
ram_web
ram_readyb
to Vss
to Vdd
high Z
high Z
IPD
I
I/O
IPU
IPU
IPU
OPU
P
IPU
I
IPD
OPD
I/O
Input CMOS
Input CMOS with pull down
Output with pull down when tristate
Input/Output CMOS tristate
Rev. 1.0, October 2000
IPU
O
OPU
P
Test input, connect to Vss
Test input, connect to Vss
PLL disable pin
Test input, connect to Vss
Test input, connect to Vss
main reset input signal, active low
CNI control signal, CNI time signal
Configurable: either generic output port (f.e. to drive
LEDs) or timing signal TIME_TICK
Configurable: either generic output port (f.e. to drive
LEDs) or timing signal TIME_OVERFLOW
Configurable: either generic output port (f.e. to drive
LEDs) or timing signal TIME_OVERFLOW
Test input, connect to Vss
Host interface (CNI) address bus
Host interface (CNI) data bus, tristate
Host interface (CNI) chip enable, active low
Host interface (CNI) output enable, active low
Host interface (CNI) write enable, active low
Host interface (CNI) transfer finish signal, active low
Connect to Vss
Connect to Vdd
Do not connect
Do not connect
Input CMOS with pull up
Output CMOS
Output with pull up when tristate
Power Pin
Page 4 of 4
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Electrical Specifications
Absolute Maximum Ratings (Non Operating)
SYMBOL
VDD
Vin
Iin
Tstrg
PARAMETER
DC Supply Voltage
Input Voltage on any Pin
Input Current on any Pin
Storage Temperature
Tsold
Soldering Temperature
tsold
H
ESD
Soldering Time
Humidity
Electrostatic Discharge
1.
MIN
-0.3 V
- 0.3 V
-100 mA
-55 oC
5%
1000 V
MAX
5.0 V
VDD + 0.3 V
100 mA
150 oC
NOTE
260 oC
10 sec
85 %
1)
25°C
Reflow and Wave
HBM: R = 1.5 k , C = 100 pF
300 oC all ceramic packages and DIL plastic packages, 260 oC for surface mounting plastic packages
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may effect device reliability (e.g. hot carrier
degradation).
Recommended Operating Conditions
PARAMETER
DC Supply Voltage
Circuit Ground
Static Supply Current
Operating Supply Current
SYMBOL
VDD
VSS
IDDS
IDD
MIN
3.0 V
0.0 V
-------
Main clock frequency
Bus Guardian clock
frequency
Ambient Temperature
CLK
CLK2
Ta
1.
2.
3.
TYP
3.3 V
0.0 V
700 µA
45 mA
MAX
3.6 V
0.0 V
800 µA
56 mA
NOTE
fCLK = 40 MHz, VDD = 3.6 V
5 MHz
4 MHz
20 MHz
16 MHz
oscillator pins xin0, xout0
oscillatpr pins xin1, xout1
-40 oC
+125 oC
1)
1)
2)
3)
The input and output parameter values in this table are directly related to ambient temperature and DC supply
voltage. A temperature range other Tamin to Tamax or a supply voltage range other than VDDmin to VDDmax will
affect these values and must be evaluated extra.
Static supply current IDDS is exclusive of input/output drive requirements and is measured at maximum VDD
with the clocks stopped and all inputs tied to VDD or VSS, configured to draw minimum current.
Operating current is exclusive of input/output drive requirements and is measured at maximum VDD and
maximum clock frequency 40 MHz.
DC Characteristics and Voltage Levels
CMOS I/O levels for specified voltage and temperature range unless otherwise noted.
Inputs Pins
Pin Name
All inputs and IO pins
without pull-up/down
Inputs with pull-up
Inputs with pull-down
1.
2.
3.
Vil
max
30%
VDD
30%
VDD
30%
VDD
Vih
min
70%
VDD
70%
VDD
70%
VDD
Iil (1)
min
NA
-50
µA
NA
max
-1.0
µA
-160
µA
NA
Iih(2)
min
NA
NOTE
NA
max
1.0
µA
NA
30
µA
160
µA
CMOS input (3)
CMOS with
pull up (3)
CMOS with
pull down (3)
Iil ist tested at VDDmax and Vin = 0
Iih ist tested at VDDmax and Vin = VDDmax
CMOS input levels are in percentage of VDD, for pull-up/down refer to pin description above.
Rev. 1.0, October 2000
Page 5 of 5
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Output Pins
Pin Name
txd[0,1],cts[0,1],led[0,2]
All other output pins
(except xout0, xout1)
All I/O pins
1.
2.
3.
Vol
V
0.4
0.4
Voh
V
2.4
2.4
Iol (1)
mA
4.0
2.0
Ioh(2)
mA
-4.0
-2.0
Ioz(3)
µA
NA
NA
NOTE
CMOS output
CMOS output
0.4
2.4
2.0
-2.0
+/-10
CMOS output, Tristate
Vol, Iol is tested at VDD = 3.3V
Voh, Ioh is tested at VDD = 3.3V
Ioz is tested at VDD = 3.6V
AC Characteristics
PARAMETER
main clock external operating
frequency
main clock XTAL0 frequency
SYMBOL
clkext
PIN
xin0
MIN
0
MAX
40 MHz
NOTE
pin plloff = high
PLL not used
clkxt0
xin0/xout0
1 MHz
20 MHz
main internal clock frequency
clk0
---
---
40 MHz
oscillator cell 1 1)
pin plloff = low PLL
in use 1)
XTAL1 operating frequency
clkxt1
xin1/xout1
1 MHz
20 MHz
oscillator cell 2
1.
1)
XTAL frequency or external clock frequency for PLL input is fixed to 10 MHz, other frequencies applicable only
without PLL function in use.
Rev. 1.0, October 2000
Page 6 of 6
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Ap p l i c a t i o n I n f o r m a t i o n
Host CPU Interface
The host CPU interface also referred as CNI (communication network interface) connects the
application circuitry to the TTP controller. All ram_-lines provide asynchronous read/write
access to a dual ported RAM. There are no setup/hold constraints referred to the microtick
(main clock “clk0”). The signals have to be applied for certain duration to be synchronized to
the main internal clock (microtick). The time_-lines signal to host CPU the global synchronous
time of the TTP network and determine when to deliver, resp. to fetch data from the host
interface. One of the lines may be connected to an interrupt input of the host CPU. Note that
the microtick, time_overflow and the time_tick pins can be configured as general purpose
output LED pins (see the LED Interface section below).
Host Interface Ports
Pin Name
ram_address[0:11]
ram_data[0:15]
ram_ceb
ram_web
ram_oeb
ram_readyb
time_overflow
microtick
time_signal
time_tick
mode
in
inout (tri)
In
In
In
out
out
out
out
out
width
12
16
1
1
1
1
1
1
1
1
comment
DPRAM address bus, 12 bit
DPRAM data bus, 16 bit
DPRAM chip enable
DPRAM write enable
DPRAM output enable
DPRAM ready
Overflow of global time (global time is Zero)
Microtick (internal main clock)
CNI time signal
Macrotick (global time is incremented)
Asynchronous DPRAM interface
Signals ram_address[0:11] and ram_web have to be stable before the falling edge of ram_ceb
For a write access the host sets ceb, web, address and data until the DPRAM has taken the
data and set readyb active low. The next access may start with readyb inactive again. A read
cycle starts with valid address and ceb, the data is valid with readyb active low. A low level on
oeb and ceb switches the data bus from tristate to output. Access times depend on the
controller clock rate and controller activity, typical values are:
controller cycle time
write time
read time
readyb low time
Tc
Tw
Tr
Trb
Min 25 ns (40 MHz)
Min 4 Tc
Min 5 Tc
Min 1 Tc
write
read
addres
valid
valid
data
valid
ceb
tristate
xx
valid
web
oeb
ready
b
Rev. 1.0, October 2000
Tw
Trb
Tr
Trb
Page 7 of 7
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Reset and Oscillator
Pin Name
xin0
xout0
xin1
xout1
plloff
resetb
mode
in
out
in
out
in
in
width
1
1
1
1
1
1
Comment
main oscillator input
main oscillator output
bus guardian oscillator input
bus guardian oscillator output
PLL disable
external reset
Table 1: Reset and Oscillator Ports
External Reset Signal
To issue a reset of the chip the resetb port has to be driven low for at least
µs. After
power-up the reset must overlap the build-up time of the oscillator circuit.
Integrated Power-On Reset
The Device has an internal Power-On Reset generator. When supply voltage ramps up, the
internal reset signal is kept active (low) for about 33 µs typical.
Parameter
supply voltage slope
power on reset active time after VDD > 1,0V
Symbol
dV/dt
tpon_res
Min
250
25
Typ
33
Max
49
Unit
kV/s
us
Oscillator circuitry
The internal oscillator cell requires an external quartz or an external oscillator respectively. The
frequency applied on the main clock input (xin0, xout0) can be reduced by a factor of four by
using the internal PLL. In order to generate an internal frequency of 40 MHz using the internal
PLL, an external quartz or quartz oscillator with a frequency of 10 MHz is connected and the
plloff input is tied low. The bus guardian clock has no internal PLL.
20MHz
16MHz
10MHz
‚1‘
16MHz
40MHz
oscillator
16MHz
oscillator
‚1‘
‚0‘
xout1
AS8202
xin1
20 MHz
Figure 3: Quartz Circuit PLL off
Rev. 1.0, October 2000
xout0
xin0
AS8202
xout1
xin1
40 MHz
Figure 4: Quartz Circuit PLL on
xout0
n.c.
xin0
AS8202
plloff
xin0
plloff
xout0
plloff
n.c.
xout1
xin1
40 MHz
Figure 5: Oscillator Circuit
Page 8 of 8
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
TTP/C Asynchronous Bus Interface
The TTP/C asynchronous bus interface uses MFM patterns to transmit/receive signals at a
maximum data rate of 5 MBit/s on a shared media (physical bus). The pins can either be
connected to drivers using recessive/dominant states on the wire as well as drivers using active
push/pull functionality.
Pin Name
txd[0]
cts[0]
txclk[0]
rxer[0]
rxclk[0]
rxdv[0]
rxd[0]
txd[1]
cts[1]
txclk[1]
rxer[1]
rxclk[1]
rxdv[1]
rxd[1]
mode
out
out
in
in
in
in
in
out
out
in
in
in
in
in
comment
Transmit data channel 0
Transmit enable channel 0
no function (do not connect)
no function (do not connect)
no function (do not connect)
no function (do not connect)
Receive data channel 0
Transmit data channel 1
Transmit enable channel 1
no function (do not connect)
no function (do not connect)
no function (do not connect)
no function (do not connect)
Receive data channel 1
Table 2: TTP/C Asynchronous Bus Interface Pins
TTP/C Synchronous Bus Interface
The TTP/C synchronous bus interface uses a synchronous transfer method to transfer data at
a rate of 25 MBit/s. PHY drivers used in commercial 100 MBit Ethernet applications can be
connected to this interface.
Pin Name
txd[0]
cts[0]
txclk[0]
rxer[0]
rxclk[0]
rxdv[0]
rxd[0]
txd[1]
cts[1]
txclk[1]
rxer[1]
rxclk[1]
rxdv[1]
rxd[1]
mode
out
out
in
in
in
in
in
out
out
in
in
in
in
in
comment
Transmit data channel 0
Transmit enable channel 0
Transmit clock channel 0
Receive error channel 0
Receive clock channel 0
Receive data valid channel 0
Receive data channel 0
Transmit data channel 1
Transmit enable channel 1
Transmit clock channel 1
Receive error channel 1
Receive clock channel 1
Receive data valid channel 1
Receive data channel 1
Table 3: TTP/C Synchronous Bus Interface Pins
Rev. 1.0, October 2000
Page 9 of 9
TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Test Interface
The Test Interface supports the manufacturing test and characterisation of the chip. In the
application environment test pins and special pins have to be connected as following:
test_se, stest, ftest, fidis, mtest, Vpp : connect to Vss
Tmr : connect to Vdd
Tm0, Tm1 : do not connect
Warning:
Any other connection of this pins may cause permanent damage to the device.
LED Signals
The LED signals can be used as a universal output port. The driver strength of the LED ports is
4mA. Note that the pins can be configured as special-function host interface pins (see the Host
Interface section for more details).
Ordering Information
Part Number:
Part Name:
Package:
AS8202
TTP/C-C2 Communication Controller
TQFP 80
Support
Software tools, hardware development boards, evaluation systems and extensive support on
TTP system integration as well as consulting is provided by:
TTTech Computertechnik AG
Time-Triggered Technology
and
TTChip GmbH – a TTTech Company
Schoenbrunnerstrasse 7
A1040 Vienna
Austria
Voice: +43 1 5853434 - 0
Fax: +43 1 5853434 - 90
email: office@tttech.com
web: http://www.tttech.com
Note: TTP is a registered trademark of FTS Computertechnik GmbH. All other trademarks are the property oftheir respective
holders.
Copyright  2000 TTTech Computertechnik AG
Copyright  2000, Austria Mikro Systeme International AG, Schloß Premstätten, 8141 Unterpremstätten, Austria.
Telefon +43-(0)3136-500-0, Telefax +43-(0)3136-52501, E-Mail info@amsint.com
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any
means, without the prior permission in writing by the copyright holder. To the best of its knowledge, Austria Mikro Systeme
International asserts that the information contained in this publication is accurate and correct.
Rev. 1.0, October 2000
Page 10 of 10