AMSCO PECL_RX

ANALOG IP BLOCK
PECL_RX - CMOS PECL Receiver
PROCESS
C35B3 (0.35um)
FEATURES
!
PECL_RX area: 0.1 mm2,
!
size: x = 300 µm y = 340 µm
PERXBIAS
!
3.3 V ±10% supply voltage
!
622 Mb/s transmission speed
size: x = 382 µm y = 375 µm
!
1 ns max. propagation delay
!
Power dissipation 23 mW at 3.3 V static without
PERXBIAS
!
!
Junction temperature –40 - 125°C
Output levels fully compatible with F100K PECL
Family
Power down mode
!
Revision B, 10.09.02
DATA SHEET
DESCRIPTION
The PECL_RX is a 3.3 V PECL differential line receiver
featuring an operating frequency up to 311 MHz (622 Mb/s)
and accepting standard F100K levels (referred to the positive
supply).
The PECL_RX accepts (750 mV) differential input signals and
translates them to CMOS output levels.
With the companion line driver (PECL_TX ) it can be used for
high speed applications.
The cell PECL_RX requires the PERXBIAS cell for biasing.
PERXBIAS can drive up to 3 PECL_RX cells. An external
voltage reference must be used.
The PECL_RX can be set in power down mode.
Page 1 of 6
Datasheet: PECL_RX - C35
TECHNICAL DATA FOR PECL_RX
(Tjunction = −40 to 125 °C, VDDPECL = VDDCMOS = VDDA = +3.0 V to +3.6 V, XPD = High, SIM = Low, unless otherwise specified)
DC CHARACTERISTICS
Symbol
VID
Parameter
Differential Input
Conditions
Min
250
Typ
750
Max
900
Units
mV
Referred to VDDPECL
–1.5
−1.3
−1.1
V
VID = |VINP – VINN|
VICM
Common Mode Input Voltage
VICM = (VINP + VINN) / 2
VIH
Input Voltage High
Referred to VDDPECL
–1.165
–0.870
V
VIL
Input Voltage Low
Referred to VDDPECL
–1.830
–1.475
V
VHYS
Hysteresis
25
100
VOH
Output Voltage High
VOL
Output Voltage Low
mV
V
CMOS levels
V
AC CHARACTERISTICS
CL = 1 pF at each output, unless otherwise specified
Symbol
tPD
Parameter
1)
Propagation Delay
Conditions
Min
600
Typ
800
tSKD1
Differential Pulse Skew 1)
80
ps
tSKD2
Differential Channel to Channel Skew 1)
100
ps
tTLH
Rise Time 2)
150
300
600
ps
tTHL
Fall Time 2)
150
300
600
ps
Cload
Load Capacitance
1
pF
Cin
Input Capacitance
700
900
fF
fMAX
Operating Frequency
311
311
MHz
TXS
Transmission Rate
622
622
Mb/s
Typ
7
Max
10
Unit
mA
11
15
mA
300
µA
@622 Mb/s
Max
1000
Unit
ps
POWER REQUIREMENTS
Symbol
ICCDC
Parameter
DC Current Consumption
Conditions
Without PERXBIAS
ICCAC
AC Current Consumption
Cload = 1 pF @622 Mb/s,
without PERXBIAS
ICCPD
Power Down Current Consumption
XPD = Low, without
PERXBIAS
Pdiss_DC
DC Power Consumption
Without PERXBIAS
23
36
mW
Pdiss_AC
AC Power Consumption
Cload = 1 pF @622 Mb/s,
without PERXBIAS
36
54
mW
Pdiss_PD
Power Consumption in Power
Down Mode
XPD = Low, without
PERXBIAS
1.08
mW
1)
2)
Min
Including the package: SOIC28, pins 5–10 or 19–24 for VOUTP and VOUTN
Specified at 20% and 80% of the output voltage
Revision B, 10.09.02
Page 2 of 6
Datasheet: PECL_RX - C35
TECHNICAL DATA FOR PERXBIAS
(Tjunction = −40 to 125 °C, VDDA = +3.0 V to +3.6 V, XSIM = High, unless otherwise specified)
POWER REQUIREMENTS
Symbol
ICC
Parameter
DC Current Consumption
Pdiss
Power Consumption
Conditions
Min
Typ
1.2
Max
2
Unit
mA
4
7.2
mW
Typ
1.22
Max
1.24
Unit
V
REFERENCE CHARACTERISTICS
Symbol
VREF
Parameter
Reference Voltage
Revision B, 10.09.02
Conditions
Min
1.20
Page 3 of 6
Datasheet: PECL_RX - C35
SYMBOL OF PECL_RX
PIN LIST OF PECL_RX
Pin
VDDPECL
Description
Positive Supply for PECL
Receiver
Type
Supply
VDDA
Positive Supply
Supply
VDDCMOS
Positive Supply for CMOS
Output Buffer
Supply
VSSPECL
Negative Supply
Supply
VSSCMOS
Negative Supply
Supply
IREFP
Bias Current
Analog
IREFN
Bias Current
Analog
VMID
Voltage Reference
Analog
XPD
High
VINP
High
VINN
Low
VOUTP
High
VOUTN
Low
XPD
Power Down
Digital
SIM
Test Pin
Digital
High
Low
High
Low
High
VINP
Positive Input
Analog
Low
X
X
High
Low
VINN
Negative Input
Analog
VOUTP
Pos. PECL Output
Digital
VOUTN
Neg. PECL Output
Digital
SYMBOL OF PERXBIAS
PIN LIST OF PERXBIAS
Pin
VDDA
Description
Positive Supply
Type
Supply
VSSA
Negative Supply
Supply
IREFP1
Bias Current
Analog
IREFP2
Bias Current
Analog
IREFP3
Bias Current
Analog
IREFN1
Bias Current
Analog
IREFN2
Bias Current
Analog
IREFN3
Bias Current
Analog
VMID
Voltage Reference
Analog
XSIM
Test Pin
Digital
VREF
External Reference
Voltage
Analog
THEORY OF OPERATION
The PECL_RX is a differential line receiver which accepts low
voltage input signals according to F100K standard.
The input signal lines must be 50 Ω transmission lines. At the
receiver input each signal has to be terminated to the voltage level
Revision B, 10.09.02
VT (where VT = VDDPECL – 2 V) with an external termination
resistor of 50 Ω, but also other termination schemes are possible.
The cell PECL_RX can be set in power down mode. It requires the
PERXBIAS cell for biasing. PERXBIAS can drive up to 3
PECL_RX cells. An external voltage reference must be used.
Page 4 of 6
Datasheet: PECL_RX - C35
APPLICATION
!
!
!
!
!
!
!
!
!
High Speed Backplane Driver
Complementary Clock Drivers
Level Translator
System Interconnects
ATM Applications
SDH Applications
High-Resolution Imaging Applications
Laser Printers
Digital Copiers
TYPICAL APPLICATION1)
external
VDDA
chip internal
SNAP BACK
1 µF
100pF
22pF
6)
1) 4)
VDDA
VSSA 3)
VDDA
1)
VDD
4)
VDD
7)
7)
1 µF
VSS
100pF
22pF
3)
VT
7)
50Ω
DATA
complementary
CMOS signals
50Ω transmission lines
DATAN
(to digital core)
50Ω
from transmitter
VT
VSS 3) 4)
VDDA
+
2V
-
1 µF
VT
VREF
100pF
22pF
VSSA
VREF (external reference)
5)
3) 4)
2)
SNAP BACK
1nF
VSSA
1)
2)
3)
4)
5)
6)
7)
6)
180pF
3)
Each power pin must have its own set of blocking capacitors.
An external reference must be used.
VSSA and VSS must be connected on the PCB level.
The two power pads can be bonded to one package pin (double bonding).
Two more PECL_RX cells can be driven with IREFxx of the PERXBIAS cell. If an output IREFxx is not used it must be left unconnected.
The PECL part of the chip has to be separated from the rest of the chip by use of snap backs (cell PWRCUT_DIG_P_SNAP_SNAP).
The cells VDD3R1P and VDD3R2P are not in the standard library, they are part of the IP-block.
Revision B, 10.09.02
Page 5 fo 6
Datasheet: PECL_RX - C35
Contact
Copyright
austriamicrosystems AG
A 8141 Schloss Premstätten, Austria
T. +43 (0) 3136 500 5333
F. +43 (0) 3136 500 5755
support@austriamicrosystems.com
Copyright © 2002 austriamicrosystems. Trademarks registered ®.
All rights reserved. The material herein may not be reproduced,
adapted, merged, translated, stored, or used without the prior
written consent of the copyright owner. To the best of its
knowledge, austriamicrosystems asserts that the information
contained in this publication is accurate and correct.
Revision B, 10.09.02
Page 6 fo 6