PCM1803 www.ti.com SLES125 – NOVEMBER 2004 SINGLE-ENDED, ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER FEATURES APPLICATIONS • • • • • • • • • • • • • • • 24-Bit Delta-Sigma Stereo A/D Converter Single-Ended Voltage Input: 3 Vp-p Oversampling Decimation Filter: – Oversampling Frequency: ×64, ×128 – Pass-Band Ripple: ±0.05 dB – Stop-Band Attenuation: –65 dB – On-Chip High-Pass Filter: 0.84 Hz (44.1 kHz) High-Performance: – THD+N: –95 dB (Typically) – SNR: 103 dB (Typically) – Dynamic Range: 103 dB (Typically) PCM Audio Interface: – Master/Slave Mode Selectable – Data Formats: • 24-Bit Left-Justified • 24-Bit I2S • 20-, 24-Bit Right-Justified Sampling Rate: 16 kHz to 96 kHz System Clock: 256 fS, 384 fS, 512 fS, 768 fS Dual Power Supplies: 5 V for Analog, 3.3 V for Digital Package: 20-Pin SSOP Pb-Free Product AV Amplifier Receiver MD Player CD Recorder Multitrack Receiver Electric Musical Instrument DESCRIPTION The PCM1803 is high-performance, low-cost, single-chip stereo analog-to-digital converter with single-ended analog voltage input. The PCM1803 uses a delta-sigma modulator with 64-, 128-times oversampling, and includes a digital decimation filter and high-pass filter which removes the DC component of the input signal. For various applications, the PCM1803 supports master and slave modes and four data formats in serial interface. The PCM1803 is suitable for a wide variety of cost-sensitive consumer applications where good performance and operation from a 5-V analog supply and 3.3-V digital supply are required. The PCM1803 is fabricated using a highly advanced CMOS process and is available in a small 20-pin SSOP package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated PCM1803 www.ti.com SLES125 – NOVEMBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PIN ASSIGNMENTS PCM1803 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 VINL VINR VREF1 VREF2 VCC AGND PDWN BYPAS TEST LRCK 20 19 18 17 16 15 14 13 12 11 MODE1 MODE0 FMT1 FMT0 OSR SCKI VDD DGND DOUT BCK P0009-01 ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE PACKAGE MARKING PCM1803DB 20-Pin SSOP DB PCM1803 ORDERING NUMBER TRANSPORT MEDIA QUANTITY PCM1803DB Tube 65 PCM1803DBR Tape and Reel 2000 BLOCK DIAGRAM Delta-Sigma Modulator VINL BCK ×1/64 , ×1/128 Decimation Filter With High-Pass Filter VREF1 Reference VREF2 Serial Interface Mode/ Format Control Delta-Sigma Modulator VINR LRCK DOUT FMT0 FMT1 MODE0 MODE1 BYPAS TEST Clock and Timing Control Power Supply VCC AGND DGND OSR PDWN SCKI VDD B0004-06 2 PCM1803 www.ti.com SLES125 – NOVEMBER 2004 DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION AGND 6 – BCK 11 I/O Analog GND BYPAS 8 I HPF bypass control. LOW: Normal mode (dc reject); HIGH: Bypass mode (through) (2) DGND 13 – Digital GND DOUT 12 O Audio data digital output FMT0 17 I Audio data format select input 0. See Data Format section. (2) FMT1 18 I Audio data format select input 1. See Data Format section. (2) LRCK 10 I/O MODE0 19 I Mode select input 0. See Data Format section. (2) MODE1 20 I Mode select input 1. See Data Format section. (2) OSR 16 I Oversampling ratio select input. LOW: ×64 fS, HIGH: ×128 fS PDWN 7 I Power-down control, active-low (2) SCKI 15 I System clock input: 256 fS, 384 fS, 512 fS or 768 fS Audio data bit clock input/output (1) Audio data latch enable input/output (1) (3) (2) TEST 9 I Test, must be connected to DGND VCC 5 – Analog power supply, 5-V VDD 14 – Digital power supply, 3.3-V VINL 1 I Analog input, L-channel VINR 2 I Analog input, R-channel VREF1 3 – Reference-voltage-1 decoupling capacitor VREF2 4 – Reference-voltage-2 decoupling capacitor (1) (2) (3) (2) Schmitt-trigger input Schmitt-trigger input with internal pulldown (50 kΩ typically), 5-V tolerant Schmitt-trigger input, 5-V tolerant ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Supply voltage VCC –0.3 V to 6.5 V Supply voltage VDD –0.3 V to 4 V Ground voltage differences AGND, DGND Digital input voltage, VI LRCK, BCK, DOUT Digital input voltage, VI PDWN, BYPAS, TEST, SCKI, OSR, FMT0, FMT1, MODE0, MODE1 Analog input voltage, VI VINL, VINR, VREF1, VREF2 –0.3 V to (VCC + 0.3 V) < 6.5 V Input current, II Any pins except supplies ±10 mA ±0.1 V –0.3 V to (VDD + 0.3 V) < 4 V –0.3 V to 6.5 V Ambient temperature under bias, Tbias –40°C to 125°C Storage temperature, Tstg –55°C to 150°C Junction temperature, TJ 150°C Lead temperature (soldering) Package temperature (IR reflow, peak) (1) 260°C, 5 s 260°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 3 PCM1803 www.ti.com SLES125 – NOVEMBER 2004 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range MIN NOM MAX Analog supply voltage, VCC 4.5 5 5.5 Digital supply voltage, VDD 2.7 3.3 3.6 Analog input voltage, full-scale (–0 dB) V V 3 Digital input logic family Digital input clock frequency UNIT Vp-p TTL System clock Sampling clock 8.192 49.152 MHz 32 96 kHz Digital output load capacitance 10 Operating free-air temperature, TA pF –25 85 °C MAX UNIT ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Resolution TYP 24 Bits DATA FORMAT Left-justified, I2S, right-justified Audio data interface format Audio data bit length 20, 24 Audio data format fS MSB-first, 2s complement Sampling frequency System clock frequency Bits 16 44.1 96 256 fS 4.096 11.2896 24.576 384 fS 6.144 16.9344 36.864 512 fS 8.192 22.5792 49.152 768 fS 12.288 33.8688 – kHz MHz INPUT LOGIC VIH (1) 2 VDD VIL (1) 0 0.8 2 5.5 VIH (2) (3) Input logic-level voltage VIL (2) (3) 0 IIH (1) (2) IIL (1) (2) IIH (3) Input logic-level current IIL (3) 0.8 VIN = VDD ±10 VIN = 0 ±10 VIN = VDD VDC 65 100 µA ±10 VIN = 0 OUTPUT LOGIC VOH (4) VOL (4) Output logic-level voltage IOUT = –4 mA 2.8 IOUT = 4 mA 0.5 VDC DC ACCURACY Gain mismatch, channel-to-channel Gain error Bipolar zero error (1) (2) (3) (4) 4 HPF bypass ±1 ±3 % of FSR ±2 ±4 % of FSR ±0.4 % of FSR Pins 10–11: LRCK, BCK (Schmitt-trigger input, in slave mode) Pin 15: SCKI (Schmitt-trigger input, 5-V tolerant) Pins 7–9, 16–20: PDWN, BYPAS, TEST, OSR, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, 5-V tolerant) Pins 10–12: LRCK, BCK (in master mode), DOUT PCM1803 www.ti.com SLES125 – NOVEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX VIN = –0.5 dB, fS = 44.1 kHz –95 –89 kHz (6) –93 UNIT DYNAMIC PERFORMANCE (5) THD+N Total harmonic distortion + noise Dynamic range SNR Signal-to-noise ratio Channel separation VIN = –0.5 dB, fS = 96 VIN = –60 dB, fS = 44.1 kHz –41 VIN = –60 dB, fS = 96 kHz (6) –41 fS = 44.1 kHz, A-weighted 100 fS = 96 kHz, A-weighted (6) fS = 44.1 kHz, A-weighted fS = 96 kHz, 103 dB 103 100 A-weighted (6) fS = 44.1 kHz dB 103 dB 103 95 fS = 96 kHz (6) 98 dB 99 ANALOG INPUT VI Input voltage 0.6 VCC Center voltage (VREF1) 0.5 VCC Input impedance Vp-p V 40 kΩ DIGITAL FILTER PERFORMANCE Pass band 0.431 fS Stop band 0.569 fS Hz ±0.05 Pass-band ripple Stop-band attenuation tGD –65 Group delay time HPF frequency response dB dB 17.4/fS –3 dB Hz s 0.019 fS mHz POWER SUPPLY REQUIREMENTS VCC VDD Supply voltage range 4.5 5 5.5 VDC 2.7 3.3 3.6 VDC 7.7 10 mA 9 mA ICC Power down (8) IDD Supply current (7) Power dissipation µA 5 fS = 44.1 kHz 6.5 fS = 96 kHz (6) 11.7 Power down (8) 1 fS = 44.1 kHz 60 fS = 96 kHz (6) 77 mW down (8) 28 µW Power mA µA 80 mW TEMPERATURE RANGE TA Operating free-air temperature θJA Thermal resistance (5) (6) (7) (8) –40 20-Pin SSOP 85 115 °C °C/W Analog performance specifications are tested using the System Two™ audio measurement system by Audio Precision™, using 400-Hz HPF, 20-kHz LPF in rms mode. fS = 96 kHz, system clock = 256 fS, oversampling ratio = ×64. Minimum load on DOUT (pin 12), BCK (pin 11), LRCK (pin 10) Halt SCKI, BCK, LRCK. 5 PCM1803 www.ti.com SLES125 – NOVEMBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data, unless otherwise noted Decimation Filter Frequency Response OVERALL CHARACTERISTICS OVERALL CHARACTERISTICS 50 50 Oversampling Ratio = 128 Oversampling Ratio = 64 0 Amplitude − dB Amplitude − dB 0 −50 −100 −150 −50 −100 −150 −200 −200 0 8 16 24 32 40 48 56 64 Normalized Frequency [× fS] 0 8 16 24 32 Normalized Frequency [× fS] G001 G002 Figure 1. Figure 2. STOP-BAND ATTENUATION CHARACTERISTICS PASS-BAND RIPPLE CHARACTERISTICS 0 0.2 −10 0.0 −20 Amplitude − dB Amplitude − dB −30 −40 −50 −60 −70 −80 −90 −0.4 −0.6 −0.8 Oversampling Ratio = 128 and 64 −100 0.00 0.25 Oversampling Ratio = 128 and 64 0.50 0.75 Normallized Frequency [× fS] Figure 3. 6 −0.2 1.00 G003 −1.0 0.0 0.1 0.2 0.3 0.4 Normalized Frequency [× fS] Figure 4. 0.5 0.6 G004 PCM1803 www.ti.com SLES125 – NOVEMBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data, unless otherwise noted LOW-CUT FILTER FREQUENCY RESPONSE HPF STOP-BAND CHARACTERISTICS HPF PASS-BAND CHARACTERISTICS 0.2 0 −10 0.0 −20 Amplitude − dB Amplitude − dB −30 −40 −50 −60 −70 −80 −0.2 −0.4 −0.6 −0.8 −90 −100 0.0 −1.0 0.1 0.2 0.3 Normalized Frequency [× fS/1000] Figure 5. 0.4 G005 0 1 2 3 Normalized Frequency [× fS/1000] 4 G006 Figure 6. 7 PCM1803 www.ti.com SLES125 – NOVEMBER 2004 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data, unless otherwise noted −90 110 −91 109 −92 108 −93 −94 −95 −96 −97 −98 −99 −100 −50 −25 0 25 50 75 106 105 103 SNR 102 −25 0 25 50 75 100 TA − Free-Air Temperature − °C G007 G008 Figure 7. Figure 8. TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE DYNAMIC RANGE and SIGNAL-TO-NOISE RATIO vs SUPPLY VOLTAGE −90 110 −91 109 −92 108 −93 −94 −95 −96 −97 −98 −99 −100 4.25 Dynamic Range 104 100 −50 100 Dynamic Range and SNR − dB THD+N − Total Harmonic Distortion + Noise − dB 107 101 TA − Free-Air Temperature − °C 107 106 105 104 Dynamic Range 103 SNR 102 101 4.50 4.75 5.00 5.25 VCC − Supply Voltage − V Figure 9. 8 DYNAMIC RANGE and SIGNAL-TO-NOISE RATIO vs TEMPERATURE Dynamic Range and SNR − dB THD+N − Total Harmonic Distortion + Noise − dB TOTAL HARMONIC DISTORTION + NOISE vs TEMPERATURE 5.50 5.75 G009 100 4.25 4.50 4.75 5.00 5.25 VCC − Supply Voltage − V Figure 10. 5.50 5.75 G010 PCM1803 www.ti.com SLES125 – NOVEMBER 2004 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data, unless otherwise noted DYNAMIC RANGE and SIGNAL-TO-NOISE RATIO vs fSAMPLE CONDITION −90 110 −91 109 −92 108 Dynamic Range and SNR − dB THD+N − Total Harmonic Distortion + Noise − dB TOTAL HARMONIC DISTORTION + NOISE vs fSAMPLE CONDITION −93 −94 −95 −96 −97 (1)f S = 48 kHz, System Clock = 256 fS, Oversampling Ratio = ×128. (2)f = 96 kHz, System Clock = 256 f , S S Oversampling Ratio = ×64. −98 −99 (1)f S = 48 kHz, System Clock = 256 fS, Oversampling Ratio = ×128. (2)f = 96 kHz, System Clock = 256 f , S S Oversampling Ratio = ×64. 107 106 105 Dynamic Range 104 103 SNR 102 101 100 −100 0 10 20(1) 30(2) 44.1 48 96 fSAMPLE Condition − kHz 0 40 G011 10 20(1) 30(2) 44.1 48 96 fSAMPLE Condition − kHz Figure 11. Figure 12. OUTPUT SPECTRUM OUTPUT SPECTRUM 40 G012 OUTPUT SPECTRUM 0 0 Input Level = −60 dB Data Points = 8192 −20 −20 −40 −40 Amplitude − dB Amplitude − dB Input Level = −0.5 dB Data Points = 8192 −60 −80 −60 −80 −100 −100 −120 −120 −140 −140 0 5 10 15 20 f − Frequency − kHz G013 Figure 13. 0 5 10 15 20 f − Frequency − kHz G014 Figure 14. 9 PCM1803 www.ti.com SLES125 – NOVEMBER 2004 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data, unless otherwise noted THD+N − Total Harmonic Distortion + Noise − dB TOTAL HARMONIC DISTORTION + NOISE vs SIGNAL LEVEL 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 Signal Level − dB G015 Figure 15. SUPPLY CURRENT SUPPLY CURRENT vs fSAMPLE CONDITION ICC and IDD − Supply Current − mA 15 IDD 10 ICC 5 (1)f S = 48 kHz, System Clock = 256 fS, Oversampling Ratio = ×128. (2)f = 96 kHz, System Clock = 256 f , S S Oversampling Ratio = ×64. 0 0 10 20(1) 30(2) 44.1 48 96 fSAMPLE Condition − kHz 40 G016 Figure 16. 10 PCM1803 www.ti.com SLES125 – NOVEMBER 2004 DEVICE INFORMATION SYSTEM CLOCK The PCM1803 supports 256 fS, 384 fS, 512 fS, and 768 fS as the system clock, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 15). The PCM1803 has a system clock-detection circuit that automatically senses if the system clock is operating at 256 fS, 384 fS, 512 fS, or 768 fS in slave mode. In master mode, the system clock frequency must be selected by MODE0 (pin 19) and MODE1 (pin 20), and 768 fS is not available. The system clock is divided automatically into 128 fS and 64 fS, and these frequencies are used to operate the digital filter and the delta-sigma modulator. Table 1 shows the relationship of typical sampling frequency and system clock frequency, and Figure 17 shows system clock timing. Table 1. Sampling Frequency and System Clock Frequency SAMPLING FREQUENCY (kHz) (1) SYSTEM CLOCK FREQUENCY (MHz) 256 fS 384 fS 512 fS 768 fS (1) 32 8.1920 12.2880 16.3840 24.5760 44.1 11.2896 16.9344 22.5792 33.8688 48 12.2880 18.4320 24.5760 36.8640 64 16.3840 24.5760 32.7680 49.1520 88.2 22.5792 33.8688 45.1584 – 96 24.5760 36.8640 49.1520 – Slave mode only. t(SCKH) t(SCKL) SCKI 2.0 V SCKI 0.8 V T0005-07 SYMBOL PARAMETER MIN MAX UNIT t(SCKH) System clock pulse duration, HIGH 8 ns t(SCKL) System clock pulse duration, LOW 8 ns Figure 17. System Clock Timing POWER-ON RESET SEQUENCE The PCM1803 has an internal power-on reset circuit, and initialization (reset) is performed automatically at the time when power-supply voltage (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical) and for 1024 system clock cycles after VDD > 2.2 V (typical), the PCM1803 stays in the reset state and the digital output is forced to zero. The digital output becomes valid when a time period of 4480/fS has elapsed following release from the reset state. Figure 18 illustrates the internal power-on reset timing and the digital output for power-on reset. 11 PCM1803 www.ti.com SLES125 – NOVEMBER 2004 VDD 2.6 V 2.2 V 1.8 V Reset Reset Removal Internal Reset 1024 System Clocks 4480 / fS System Clock DOUT Zero Data Normal Data T0014-05 Figure 18. Internal Power-On Reset Timing SERIAL AUDIO DATA INTERFACE The PCM1803 interfaces the audio system through BCK (pin 11), LRCK (pin 10), and DOUT (pin 12). INTERFACE MODE The PCM1803 supports master mode and slave mode as interface modes, and they are selected by MODE1 (pin 20) and MODE0 (pin 19) as shown in Table 2. In master mode, the PCM1803 provides the timing of serial audio data communications between the PCM1803 and the digital audio processor or external circuit. While in slave mode, the PCM1803 receives the timing for data transfers from an external controller. Table 2. Interface Mode MODE1 MODE0 INTERFACE MODE 0 0 Slave mode (256 fS, 384 fS, 512 fS, 768 fS) 0 1 Master mode (512 fS) 1 0 Master mode (384 fS) 1 1 Master mode (256 fS) Master Mode In master mode, BCK and LRCK work as output pins, and these pins are controlled by timing which is generated in the clock circuit of the PCM1803. The frequency of BCK is fixed at LRCK × 64. The 768-fS system clock is not available in master mode. Slave Mode In slave mode, BCK and LRCK work as input pins. The PCM1803 accepts the 64-BCK/LRCK or 48-BCK/LRCK format (only for 384 fS and 768 fS system clocks), not the 32-BCK/LRCK format. DATA FORMAT The PCM1803 supports four audio data formats in both master and slave modes, and the data formats are selected by FMT1 (pin 18) and FMT0 (pin 17) as shown in Table 3. Figure 19 illustrates the data formats in slave and master modes. 12 PCM1803 www.ti.com SLES125 – NOVEMBER 2004 Table 3. Data Formats FORMAT FMT1 FMT0 0 0 0 Left-justified, 24-bit DESCRIPTION 1 0 1 I2S, 24-bit 2 1 0 Right-justified, 24-bit 3 1 1 Right-justified, 20-bit FORMAT 0: FMT[1:0] = 00 24-Bit, MSB-First, Left-Justified Left-Channel LRCK Right-Channel BCK DOUT 1 2 3 22 23 24 MSB 1 LSB 2 3 22 23 24 MSB 1 LSB FORMAT 1: FMT[1:0] = 01 24-Bit, MSB-First, I2S LRCK Left-Channel Right-Channel BCK DOUT 1 2 3 22 23 24 1 LSB MSB 2 3 22 23 24 LSB MSB FORMAT 2: FMT[1:0] = 10 24-Bit, MSB-First, Right-Justified LRCK Left-Channel Right-Channel BCK DOUT 24 1 2 3 22 23 24 MSB LSB 1 2 3 22 23 24 MSB LSB FORMAT 3: FMT[1:0] = 11 20-Bit, MSB-First, Right-Justified LRCK Left-Channel Right-Channel BCK DOUT 20 1 2 MSB 3 18 19 20 LSB 1 2 MSB 3 18 19 20 LSB T0016-11 Figure 19. Audio Data Formats (LRCK and BCK Work as Inputs in Slave Mode and as Outputs in Master Mode) 13 PCM1803 www.ti.com SLES125 – NOVEMBER 2004 INTERFACE TIMING Figure 20 and Figure 21 illustrate the interface timing in slave mode and master mode, respectively. t(LRCP) 1.4 V LRCK t(BCKL) t(BCKH) t(LRSU) t(LRHD) 1.4 V BCK t(CKDO) t(BCKP) t(LRDO) 0.5 VDD DOUT T0017-02 SYMBOL PARAMETER MIN TYP MAX UNIT t(BCKP) BCK period 1/(64 fS) ns t(BCKH) BCK pulse duration, HIGH 1.5 × t(SCKI) ns t(BCKL) BCK pulse duration, LOW 1.5 × t(SCKI) ns t(LRSU) LRCK setup time to BCK rising edge 40 ns t(LRHD) LRCK hold time to BCK rising edge 20 ns t(LRCP) LRCK period 10 t(CKDO) Delay time, BCK falling edge to DOUT valid –10 40 ns t(LRDO) Delay time, LRCK edge to DOUT valid –10 40 ns tr Rising time of all signals 20 ns tf Falling time of all signals 20 ns µs NOTE: Timing measurement reference level is (VIH + VIL)/2. Rising and falling time is measured from 10% to 90% of IN/OUT signal swing. Load capacitance of DOUT is 20 pF. t(SCKI) means SCKI period time. Figure 20. Audio Data Interface Timing (Slave Mode: LRCK and BCK Work as Inputs) 14 PCM1803 www.ti.com SLES125 – NOVEMBER 2004 t(LRCP) 0.5 VDD LRCK t(BCKL) t(BCKH) t(CKLR) 0.5 VDD BCK t(CKDO) t(BCKP) t(LRDO) 0.5 VDD DOUT T0018-02 SYMBOL PARAMETER t(BCKP) BCK period t(BCKH) BCK pulse duration, HIGH t(BCKL) BCK pulse duration, LOW t(CKLR) Delay time, BCK falling edge to LRCK valid t(LRCP) LRCK period t(CKDO) Delay time, BCK falling edge to DOUT valid t(LRDO) Delay time, LRCK edge to DOUT valid tr tf MIN 150 TYP MAX 1000 ns 65 600 ns 65 600 ns –10 20 ns 65 µs –10 20 ns –10 20 ns Rising time of all signals 20 ns Falling time of all signals 20 ns 10 1/(64 fS) UNIT 1/fS NOTE: Timing measurement reference level is (VIH + VIL)/2. Rising and falling time is measured from 10% to 90% of IN/OUT signal swing. Load capacitance of all signals is 20 pF. Figure 21. Audio Data Interface Timing (Master Mode: LRCK and BCK Work as Outputs) SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM In slave mode, the PCM1803 operates under LRCK, synchronized with system clock SCKI. The PCM1803 does not need a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI. If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCK/frame (±5 BCKs for 48 BCK/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/fS and digital output is forced to zero data (BPZ code) until resynchronization between LRCK and SCKI occurs. In case of changes less than ±5 BCKs for 64 BCK/frame (±4 BCKs for 48 BCK/frame), resynchronization does not occur and the previously explained digital output control and discontinuity do not occur. Figure 22 illustrates the digital output response for loss of synchronization and resynchronization. During undefined data, the PCM1803 can generate some noise in the audio signal. Also, the transition of normal to undefined data and undefined or zero data to normal creates a discontinuity in the data of the digital output, which can generate some noise in the audio signal. It is recommended to set PDWN (pin 7) to LOW once to get stable analog performance when the sampling rate, interface mode, data format, or oversampling control is changed. 15 PCM1803 www.ti.com SLES125 – NOVEMBER 2004 Synchronization Lost State of Synchronization SYNCHRONOUS Resynchronization ASYNCHRONOUS SYNCHRONOUS 1/fS DOUT NORMAL DATA UNDEFINED DATA 32/fS ZERO DATA NORMAL DATA T0020-05 Figure 22. ADC Digital Output for Loss of Synchronization and Resynchronization POWER DOWN PDWN (pin 7) controls operation of the entire ADC. During power-down mode, supply current for the analog portion is shut down and the digital portion is reset; also, DOUT (pin 12) is disabled. It is acceptable to halt the system clock during power-down mode so that power dissipation is minimized. The minimum LOW pulse duration of PDWN pin is 100 ns. Table 4. Power-Down Control PWDN Power-Down Mode LOW Power-down mode HIGH Normal operation mode HPF BYPASS The built-in function for dc-component rejection can be bypassed by BYPAS (pin 8) control. In bypass mode, the dc component of the input analog signal, internal dc offset, etc., also are converted and included in the digital output data. Table 5. HPF Bypass Control BYPAS HPF (High-Pass Filter) Mode LOW Normal (no dc component in DOUT) mode HIGH Bypass (dc component in DOUT) mode OVERSAMPLING RATIO CONTROL OSR (pin 16) controls oversampling ratio of the delta-sigma modulator, ×64 or ×128. The ×128 mode is available for fS ≤ 48 kHz. Table 6. Oversampling Control OSR Oversampling Ratio LOW ×64 HIGH ×128 (fS ≤ 48 kHz) 16 PCM1803 www.ti.com SLES125 – NOVEMBER 2004 APPLICATION INFORMATION TYPICAL CIRCUIT CONNECTION DIAGRAM Figure 23 illustrates a typical circuit connection diagram where the cutoff frequency of the input HPF is about 160 kHz. C1 + R1 C2 + R2 L-Ch IN R-Ch IN 1 VINL MODE1 20 2 VINR MODE0 19 3 VREF1 FMT1 18 Mode [1:0] C7 C8 C5 C6 + + FMT0 17 OSR 16 Oversampling AGND SCKI 15 System Clock 7 PDWN VDD 14 8 BYPAS DGND 13 9 TEST DOUT 12 Data Out 10 LRCK BCK 11 Data Clock 4 VREF2 5 VCC 6 Power Down LCF Bypass +5 V + C4 Control Format [1:0] PCM1803 Control + C3 +3.3 V Audio Data Processor L/R Clock S0026-01 NOTES: A. C1, C2: A 1-µF electrolytic capacitor gives a 4-Hz (τ = 1 µF × 40 kΩ) cutoff frequency for the input HPF in normal operation, and requires a power-on settling time with a 40-ms time constant during the power-on initialization period. B. C3, C4: Bypass capacitors are 0.1-µF ceramic and 10-µF electrolytic, depending on layout and power supply. C. C5, C6: Recommended capacitors are 0.1-µF ceramic and 10-µF electrolytic. D. C7, C8, R1, R2: A 0.01-µF film-type capacitor and 100-Ω resistor give a 160-kHz (τ = 0.01 µF × 100 Ω) cutoff frequency for the antialiasing filter in normal operation. Figure 23. Typical Application Diagram BOARD DESIGN and LAYOUT CONSIDERATIONS VCC, VDD Pins The digital and analog power-supply lines to the PCM1803 should be bypassed to the corresponding ground pins with 0.1-µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the dynamic performance of the ADC. AGND, DGND Pins To maximize the dynamic performance of the PCM1803, the analog and digital grounds are not connected internally. These grounds should have low impedance to avoid digital noise feeding back into the analog ground. Therefore, they should be connected directly to each other under the part to reduce potential noise problems. 17 PCM1803 SLES125 – NOVEMBER 2004 www.ti.com APPLICATION INFORMATION (continued) VINL, VINR Pins The VINL and VINR pins need a simple external RC filter (fC = 160 kHz) as an antialiasing filter to remove out-of-band noise from the audio band. If the input signal includes noise with a frequency near the oversampling frequency (64 fS or 128 fS), the noise is folded into the baseband (audio band) signal through A-to-D conversion. The recommended R value is 100 Ω. Film-type capacitors of 0.01-µF should be located as close as possible to the VINL and VINR pins and should be terminated to GND as close as possible to the AGND pin to maximize the dynamic performance of ADC, by suppressing kickback noise from the PCM1803. VREF1 Pin A 0.1-µF ceramic capacitor and 10-µF electrolytic capacitor are recommended between VREF1 and AGND to ensure low source impedance of the ADC references. These capacitors should be located as close as possible to the VREF1 pin to reduce dynamic errors on the ADC reference. VREF2 Pin The differential voltage between VREF2 and AGND sets the analog input full-scale range. A 0.1-µF ceramic capacitor and 10-µF electrolytic capacitor are recommended between VREF2 and AGND. These capacitors should be located as close as possible to the VREF2 pin to reduce dynamic errors on the ADC reference. DOUT Pin The DOUT pin has enough load drive capability, but if the DOUT line is long, locating a buffer near the PCM1803 and minimizing load capacitance is recommended to minimize the digital-analog crosstalk and maximize the dynamic performance of the ADC. System Clock The quality of the system clock can influence the dynamic performance, because the PCM1803 operates based on a system clock. Therefore, it may be required to consider the system-clock duty, jitter, and the time difference between system-clock transition and BCK or LRCK transition in the slave mode. 18 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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