ANACHIP PA7540J-15

PA7540 PEEL Array™
Programmable Electrically Erasable Logic Array
Most Powerful 24-pin PLD Available
- 20 I/Os, 2 inputs/clocks, 40 registers/latches
- 40 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers and other widegate functions
High-Speed Commercial and Industrial Versions
- As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (fMAX)
- Industrial grade available for 4.5 to 5.5V VCC and
-40 to +85 °C temperatures
CMOS Electrically Erasable Technology
- Reprogrammable in 24-pin DIP, SOIC and
28-pin PLCC packages
- Optional JN package for 22V10 power/ground
compatibility
Flexible Logic Cell
- 2 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
Development and Programmer Support
- Anachip’s WinPLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party
programmers
General Description
The PA7540 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on ICT’s
CMOS EEPROM technology. PEEL™ Arrays free
designers from the limitations of ordinary PLDs by
providing the architectural flexibility and speed needed for
today’s programmable logic designs. The PA7540 is by far
the most powerful 24-pin PLD available today with 20 I/O
pins, 2 input/global-clocks and 40 registers/latches (20
buried logic cells and 20 I/O registers/latches). Its logic
array implements 84 sum-of-products logic functions. The
PA7540’s logic and I/O cells (LCCs, IOCs) are extremely
flexible offering two output functions per cell (a total of 40
for all 20 logic cells). Logic cells are configurable as D, T,
and JK registers with independent or global clocks, resets,
Figure 1. Pin Configuration
4
21
I/O
I/O
5
20
I/O
I/O
6
19
I/O
I/O
7
18
I/O
I/O
8
17
I/O
I/O
9
16
I/O
I/O
10
15
I/O
I/O
11
14
I/O
GND
12
13
I/C LK2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
23
I/O
G ND
8
22
NC
9
21
I/O
10
20
I/O
19
I/O
20
I/O
I/O
19
I/O
I/O
11
PA7540
L o g ic C o n tro l C e lls
I/C L K 2
I/O
C ells
(IO C )
20
B uried
logic
20
L o g ic
Arr ay
4 sum term s
4 product term s
for G lobal C ells
A
B
C
D
20 I/O P ins
Logic
C ontrol
C ells
(LC C )
20
Logic functions
to I/O cells
20
80 sum term s
(four per LC C )
20 Logic C ontrol Cells
2 output functions per cell
(40 total output functions possible)
0 8 -1 4 -0 02 A
12 13 14 15 16 17 18
I/O
21
10
I/O
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
22
I/CLK2
I/O
I/O
NC
23
8
GND
25
I/O
I/O
NC
7
I/O
GND
1 28 27 26
84 (42X2)
A rray Inputs
true and
com plem ent
VC C
I/O
I/O
I/O
I/O
2
I/O C e lls
I/O
I/O
NC
I/O
3
G lo b a l C e lls
I/O
24
I/O
PLCC -J
2
I/C L K 1
6
24
1 2 1 3 1 4 1 5 1 6 1 71 8
G lobal
C ells
I/O
6
11
2 Input/
G lobal C lock P ins
I/O
I/O
I/O
4
5
NC
25
I/CLK2
28 27 26
I/O
1
I/O
VCC
2
I/O
VCC
3
I/O
I/O
I/CLK1
4
5
VC C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/C LK2
SO IC
GND
I/O
I/O
DIP
24
23
22
21
20
19
18
17
16
15
14
13
I/O
22
I/O
1
2
3
4
5
6
7
8
9
10
11
12
I/C LK1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
3
I/O
VCC
I/O
NC
VC C
23
I/CLK1
24
2
I/O
I/O
1
I/O
Figure 2. Block Diagram
I/O
I/C LK1
presets, clock polarity, and other features, making the
PA7540 suitable for a variety of combinatorial,
synchronous and asynchronous logic applications. With pin
compatibility and super-set functionality to most 24-pin
PLDs, (22V10, EP610/630, GAL6002), the PA7540 can
implement designs that exceed the architectures of such
devices. The PA7540 supports speeds as fast as
10ns/15ns (tpdi/tpdx) and 71.46MHz (fMAX) at moderate
power consumption 80mA (55mA typical). Packaging
includes 24-pin DIP, SOIC and 28-pin PLCC (see Figure
1). Anachip and popular third-party development tool
manufacturers provide development and programming
support for the PA7540.
PLCC -JN
08-14-001B
1
04-02-051B
Inside the Logic Array
The heart of the PEEL™ Array architecture is based on a
logic array structure similar to that of a PLA (programmable
AND, programmable OR). The logic array implements all
logic functions and provides interconnection and control of
the cells. In the PA7540 PEEL™ Array, 42 inputs are
available into the array from the I/O cells and input/globalclock pins.
All inputs provide both true and complement signals, which
can be programmed to any product term in the array. The
PA7540 PEEL™ Arrays contains 84 product terms. All
product terms (with the exception of certain ones fed to the
global cells) can be programmably connected to any of the
sum-terms of the logic control cells (four sum-terms per
logic control cell). Product-terms and sum-terms are also
routed to the global cells for control purposes. Figure 3
shows a detailed view of the logic array structure.
From
IO C ells
(IO C) and
I/CLKs
needed and not left unutilized or duplicated. Secondly, the
sum-of-products functions provided to the logic cells can be
used for clocks, resets, presets and output enables instead of
just simple product-term control.
The PEEL™ logic array can also implement logic functions
with many product terms within a single-level delay. For
example a 16-bit comparator needs 32 shared product terms
to implement 16 exclusive-OR functions. The PEEL™ logic
array easily handles this in a single level delay. Other
PLDs/CPLDs either run out of product-terms or require
expanders or additional logic levels that often slow
performance and skew timing.
Logic Control Cell (LCC)
Logic Control Cells (LCC) are used to allocate and control the
logic functions created in the logic array. Each LCC has four
primary inputs and three outputs. The inputs to each LCC are
complete sum-of-product logic functions from the array, which
can be used to implement combinatorial and sequential logic
functions, and to control LCC registers and I/O cell output
enables.
From G lobal C ell
42 Array Inputs
S ys tem C lock
P res et
R egType R es et
O n /O ff
MUX
From
Logic
Control
Cells
(LCC)
To
G lobal
Cells
84 Product Term s
To
A rray
P
D ,T,J
MUX
Q
R EG
K
R
From
A rray
A
B
C
D
To
I/O
C ell
MUX
To
Logic C ontrol
Cells
(LCC)
PA 7540 Logic Array
08 -14 -0 04 A
Figure 4. Logic Control Cell Block Diagram
84 Sum Term s
08-14-003A
Figure 3 PA7540 Logic Array
True Product-Term Sharing
The PEEL™ logic array provides several advantages over
common PLD logic arrays. First, it allows for true productterm sharing, not simply product-term steering, as
commonly found in other CPLDs. Product term sharing
ensures that product-terms are used where they are
2
As shown in Figure 4, the LCC is made up of three signal
routing multiplexers and a versatile register with synchronous
or asynchronous D, T, or JK registers (clocked-SR registers,
which are a subset of JK, are also possible). See Figure 5.
EEPROM memory cells are used for programming the
desired configuration. Four sum-of-product logic functions
(SUM terms A, B, C and D) are fed into each LCC from the
logic array. Each SUM term can be selectively used for
multiple functions as listed below.
04-02-051B
can be registered, one output can be combinatorial and the
third, an output enable. The multi-function PEEL™ Array logic
cells are equivalent to two or three macrocells of other PLDs,
which have only one output per cell. They also allow registers
to be truly buried from I/O pins without limiting them to inputonly (see Figure 8 ).
Sum-A = D, T, J or Sum-A
Sum-B = Preset, K or Sum-B
Sum-C = Reset, Clock, Sum-C
Sum-D = Clock, Output Enable
D
P
D R e g is te r
Q = D after clocked
Q
Best for storage, simple coun ters,
shifters and state machines with
few hold (loop) conditions.
R
From Global Cell
I/O Cell Clock
T
P
Q
J
K
REG /
Latch
Q
Best for wide binary counters (saves
product terms) and state machines
with many hold (loop) conditio ns.
R
P
T R e g is te r
Q toggles when T = 1
Q holds when T = 0
Q
To
Array
J K R e g is te r
Q toggles when J/K = 1/1
Q holds when J/K = 0/0
Q =1
when J/K = 1/0
Q =0
when J/K = 0/1
R
Combines features of both D and T
registers.
From
Logic
Control
Cell
08-14-005A
Figure 5. LCC Register Types
SUM-A can serve as the D, T, or J input of the register or a
combinatorial path. SUM-B can serve as the K input, or the
preset to the register, or a combinatorial path. SUM-C can
be the clock, the reset to the register, or a combinatorial
path. SUM-D can be the clock to the register or the output
enable for the connected I/O cell. Note that the sums
controlling clocks, resets, presets and output enables are
complete sum-of-product functions, not just product terms
as with most other PLDs. This also means that any input or
I/O pin can be used as a clock or other control function.
MUX
Input
A,B,C
or
Q
MUX
MUX
D
1 0
7540 /O Cell (IOC)
08-14-006A
Figure 6. I/O Cell Block Diagram
D
Multiple Outputs Per Logic Cell
An important feature of the logic control cell is its capability
to have multiple output functions per cell, each operating
independently. As shown in Figure 4, two of the three
outputs can select the Q output from the register or the
Sum A, B or C combinatorial paths. Thus, one LCC output
3
Q
IO C R e g is te r
Q = D after rising edge of clo ck
holds until next rising ed ge
L
Several signals from the global cell are provided primarily
for synchronous (global) register control. The global cell
signals are routed to all LCCs. These signals include a
high-speed clock of positive or negative polarity, global
preset and reset, and a special register-type control that
selectively allows dynamic switching of register type. This
last feature is especially useful for saving product terms
when implementing loadable counters and state machines
by dynamically switching from D-type registers to load and
T-type registers to count (see Figure 10).
I/O Pin
Q
IO C L a tc h
Q = L when clock is high
holds value when clock is low
08-14-007A
Figure 7. IOC Register Configurations
I/O Cell (IOC)
All PEEL™ Arrays have I/O cells (IOC) as shown above in
Figure 6. Inputs to the IOCs can be fed from any of the LCCs
in the array. Each IOC consists of routing and control
multiplexers, an input register/transparent latch, a three-state
buffer and an output polarity control. The register/ latch can
be clocked from a variety of sources determined by the global
cell. It can also be bypassed for a non-registered input. The
combination of LCC and IOC allows for multiple buried
registers and logic paths. (See Figure 8).
04-02-051B
G roup A & B
Q
Input with optional
register/latch
D
CL K1
I/O
MUX
LCC Clocks
MUX
IO C Clocks
CLK 2
PCL K
Reg-Type
I/O with
independent
output enable
A
B
C
D
D Q
LCC Reg-Type
Preset
LCC Presets
LCC Resets
Reset
1
G lobal C ell: LC C & IO C
2
08-14-009A
OE
08-14 -008A
Figure 9. Global Cells
Figure 8. LCC & IOC With Two Outputs
Reg-T ype from G lobal Cell
Global Cells
The global cells, shown in Figure 9, are used to direct
global clock signals and/or control terms to the LCCs and
IOCs. The global cells allow a clock to be selected from the
CLK1 pin, CLK2 pin, or a product term from the logic array
(PCLK). They also provide polarity control for IOC clocks
enabling rising or falling clock edges for input
registers/latches. Note that each individual LCC clock has
its own polarity control. The global cell includes sum-ofproducts control terms for global reset and preset, and a
fast product term control for LCC register-type, used to
save product terms for loadable counters and state
machines (see Figure 10). The PA7540 provides two
global cells that divides the LCC and IOCs into two groups,
A and B. Half of the LCCs and IOCs use global cell A, half
use global cell B. This means, for instance, two high-speed
global clocks can be used among the LCCs.
R e g is te r T yp e C h a ng e F e a tu re
D
P
Q
R
T
P
R
G lobal Cell can dynamica lly change userse lected LCC registers fro m D to T or from D
to JK. This saves product terms for loadable
co unters or state machine s. Use as D register
to load, use as T or JK to count. Timing allows
dynamic operation.
E x a m p le :
Product terms for 10 bit lo adable binary counter
Q
D uses 57 product terms (47 count, 10 load)
T uses 30 product terms (10 count, 20 load)
D/T uses 20 product terms (10 count, 10 load)
08-14-010A
Figure 10. Register Type Change Feature
internal signals to be simulated and analyzed via a
waveform display.(See Figures 10a-c)
PEEL™ Array Development Support
Development support for PEEL™ Arrays is provided by
Anachip and manufacturers of popular development tools.
Anachip offers the powerful WinPLACE Development
Software (free to qualified PLD designers).
The PLACE software includes an architectural editor, logic
compiler, waveform simulator, documentation utility and a
programmer interface. The PLACE editor graphically
illustrates and controls the PEEL™ Array’s architecture,
making the overall design easy to understand, while
allowing the effectiveness of boolean logic equations, state
machine design and truth table entry. The PLACE compiler
performs logic transformation and reduction, making it
possible to specify equations in almost any fashion and fit
the most logic possible in every design. PLACE also
provides a multi-level logic simulator allowing external and
4
PEEL™ Array development is also supported by popular
development tools, such as ABEL via Anachip’s PEEL™
Array fitters. A special smart translator utility adds the
capability to directly convert JEDEC files for other devices
into equivalent JEDEC files for pin-compatible PEEL™
Arrays.
Programming
PEEL™ Arrays are EE-reprogrammable in all package
types, plastic-DIP, PLCC and SOIC. This makes them an
ideal development vehicle for the lab. EE reprogrammability is also useful for production, allowing
unexpected changes to be made quickly and without
04-02-051B
waste. Programming of PEEL™ Arrays is supported by
many popular third party programmers.
Design Security and Signature Word
The PEEL™ Arrays provide a special EEPROM security bit
that prevents unauthorized reading or copying of designs.
Once set, the programmed bits of the PEEL™ Arrays
cannot be accessed until the entire chip has been
electrically erased. Another programming feature,
signature word, allows a user-definable code to be
programmed into the PEEL™ Array. The code can be read
back even after the security bit has been set. The signature
word can be used to identify the pattern programmed in the
device or to record the design revision.
Figure 12 - WinPLACE LCC and IOC screen
Figure 11 - WinPLACE Architectural Editor for
PA7540
5
Figure 13 - WinPLACE waveform and
simulator screen
04-02-051B
Table 1. Absolute Maximum Ratings
Symbol
Parameter
Conditions
Ratings
Unit
VCC
Supply Voltage
Relative to Ground
-0.5 to + 7.0
V
1
VI, VO
Voltage Applied to Any Pin
Relative to Ground
-0.5 to VCC + 0.6
V
IO
Output Current
Per pin (IOL, IOH)
±25
mA
TST
Storage Temperature
TLT
Lead Temperature
-65 to + 150
°C
+300
°C
Soldering 10 seconds
Table 2. Operating Ranges
Symbol
Parameter
Conditions
Min
Max
Commercial
4.75
5.25
Industrial
4.5
5.5
Unit
VCC
Supply Voltage
TA
Ambient Temperature
TR
Clock Rise Time
See Note 2
20
ns
TF
Clock Fall Time
See Note 2
20
ns
TRVCC
VCC Rise Time
See Note 2
250
ms
Commercial
0
+70
Industrial
-40
+85
V
°C
Over the Operating Range
Table 3. D.C. Electrical Characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
VOH
Output HIGH Voltage - TTL
VCC = Min, IOH = -4.0mA
VOHC
Output HIGH Voltage CMOS
VCC = Min, IOH = -10µA
VOL
Output LOW Voltage - TTL
VCC = Min, IOL = 16mA
0.5
V
VOLC
Output LOW Voltage CMOS
VCC = Min, IOL = -10µA
0.15
V
2.4
V
VCC - 0.3
V
VIH
Input HIGH Level
2.0
VCC + 0.3
V
VIL
Input LOW Level
-0.3
0.8
V
IIL
Input Leakage Current
VCC = Max, GND ≤VIN ≤VCC
±10
µA
IOZ
Output Leakage Current
I/O = High-Z, GND ≤VO ≤VCC
±10
µA
ISC
Output Short Circuit
Current4
VCC = 5V, VO = 0.5V, TA= 25°C
-120
mA
VCC Current
VIN = 0V or VCC3,11
f = 25MHz
All outputs disabled4
ICC11
CIN7
COUT7
Input Capacitance5
Output Capacitance5
-30
-15
I-15
55 (typ.)18
80
mA
90
6
pF
12
pF
TA = 25°C, VCC = 5.0V @ f = 1 MHz
6
04-02-051B
Table 4. A.C Electrical Characteristics Combinatorial
Symbol
tPDI
tPDX
tIA
tAL
tLC
tLO
tOD, tOE
tOX
6,12
Parameter
Propagation delay Internal (tAL + tLC)
Propagation delay External (tIA + tAL +tLC + tLO)
Input or I/O pin to array input
Array input to LCC
LCC input to LCC output10
LCC output to output pin
Output Disable, Enable from LCC output7
Output Disable, Enable from input pin7
Over the Operating Range
-15/I-15
Min
Max
10
15
2
9
1
3
3
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
This device has been designed and tested for the recommended operating conditions. Proper operation outside of these
levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage
Figure 14. Combinatorial Timing - Waveforms and Block Diagram
7
04-02-051B
Table 5. A.C. Electrical Characteristics Sequential
-15/I-15
6,1
Symbol
Parameter
8
Min
14
tSCX
Internal set-up to system clock - LCC
(tAL + tSK + tLC - tCK)
Input16 (EXT.) set-up to system clock, - LCC (tIA + tSCI)
tCOI
System-clock to Array Int. - LCC/IOC/INC14 (tCK +tLC)
tCOX
System-clock to Output Ext. - LCC (tCOI + tLO)
tHX
Input hold time from system clock - LCC
tSCI
Max
Unit
ns
6
8
ns
8
ns
12
ns
0
ns
tSK
13
LCC Input set-up to async. clock - LCC
3
ns
tAK
Clock at LCC or IOC - LCC output
1
ns
tHK
LCC input hold time from system clock - LCC
4
ns
ns
14
tSI
Input set-up to system clock - IOC/INC (tSK - tCK)
0
tHI
Input hold time from system clock - IOC/INC (tSK - tCK)
4
tPK
Array input to IOC PCLK clock
ns
6
17
tSPI
Input set-up to PCLK clock - IOC/INC (tSK-tPK-tIA)
0
tHPI
Input hold from PCLK clock17 - IOC/INC (tPK+tIA-tSK)
5
tCK
System-clock delay to LCC/IOC/INC
tCW
System-clock low or high pulse width
fMAX1
ns
ns
ns
7
ns
Max. system-clock frequency Int/Int 1/(tSCI + tCOI)
71.4
MHz
fMAX2
Max. system-clock frequency Ext/Int 1/(tSCX + tCOI)
62.5
MHz
fMAX3
Max. system-clock frequency Int/Ext 1/(tSCI + tCOX)
55.5
MHz
fMAX4
Max. system-clock frequency Ext/Ext 1/(tSCX + tCOX)
50.0
MHz
7
9
ns
fTGL
Max. system-clock toggle frequency 1/(tCW + tCW)
71.4
MHz
tPR
LCC presents/reset to LCC output
1
ns
tST
Input to Global Cell present/reset (tIA + tAL + tPR)
12
ns
tAW
Asynch. preset/reset pulse width
tRT
Input to LCC Reg-Type (RT)
6
ns
tRTV
LCC Reg-Type to LCC output register change
1
ns
tRTC
Input to Global Cell register-type change (tRT + tRTV)
7
ns
tRW
Asynch. Reg-Type pulse width
tRESET
8
ns
10
Power-on reset time for registers in clear state
8
2
ns
5
µs
04-02-051B
Figure 15. Sequential Timing – Waveforms and Block Diagram
Notes
1. Minimum DC input is -0.5V, however inputs may under-shoot to -2.0V
for periods less than 20ns.
2.Test points for Clock and VCC in tR,tF,tCL,tCH, and tRESET are referenced at
10% and 90% levels.
3. I/O pins are 0V or VCC.
4. Test one output at a time for a duration of less than 1 sec.
5. Capacitances are tested on a sample basis.
6. Test conditions assume: signal transition times of 5ns or less from the
10% and 90% points, timing reference levels of 1.5V (unless
otherwise specified).
7. tOE is measured from input transition to VREF ±0.1V (See test loads at
end of Section 6 for VREF value). tOD is measured from input transition
to VOH -0.1V or VOL +0.1V.
8. DIP: “System-clock” refers to pin 1/13 high speed clocks. PLCC: “System-clock” refers to pin 2/16 high speed clocks.
9. For T or JK registers in toggle (divide by 2) operation only.
10. For combinatorial and async-clock to LCC output delay.
11. ICC for a typical application: This parameter is tested with the device
programmed as a 10-bit D-type counter.
9
12. Test loads are specified in Section 5 of the Data Book.
13. “Async. Clock” refers to the clock from the Sum term (OR gate).
14. The “LCC” term indicates that the timing parameter is applied to the
LCC register. The “LCC/IOC” term indicates that the timing
parameter is applied to both the LCC and IOC registers.
16. The term “input” without any reference to another term refers to an
(external) input pin.
17. The parameter tSPI indicates that the PCLK signal to the IOC register
is always slower than the data from the pin or input by the absolute
value of (tSK -tPK -tIA). This means that no set-up time for the data
from the pin or input is required, i.e. the external data and clock can
be sent to the device simultaneously. Additionally, the data from the
pin must remain stable for tHPI time, i.e. to wait for the PCLK signal to
arrive at the IOC register.
18. Typical (typ) ICC is measured at TA = 25° C, freq = 25MHZ, VCC =
5V
04-02-051B
Table 6. Ordering Information
Part Number
PA7540P-15
PA7540J-15
PA7540JN-15
PA7540S-15
PA7540PI-15
PA7540JI-15
PA7540JNI-15
PA7540SI-15
Speed
Temperature
10/15ns
C
10/15ns
I
Package
P24
J28
JN28
S24
P24
J28
JN28
S24
Figure 16. Part Number
Device
Suffix
P A7540J-15
P ackag e
S peed
P = 300m il DIP
J = Plastic (J) Leaded Chip Carrier (PLCC)
JN = PLCC Alternate Pin Out
S = SOIC 300 m il Gullwing
-15 = 10ns/15ns tpd/tpdx
Tem perature R ange
(Blank) = Com m ercial 0 to 70° C
I = Industrial -40 to +85° C
08-14--016A
Anachip USA, Inc.
Email:
Sales_usa@anachip.com
780 Montague Expressway, #201
San Jose, CA 95131
TEL (408) 321-9600
FAX (408) 321-9696
Website:
http://www.anachip.com
©2002 Anachip Corp.
Anachip reserves the right to make changes in specifications at any time and without notice. The information furnished by
Anachip in this publication is believed to be accurate and reliable. However, there is no responsibility assumed by Anachip
for its use nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted
under any patents or patent rights of Anachip. Anachip’s products are not authorized for use as critical components in life
support devices or systems.
©
Marks bearing or ™ are registered trademarks and trademarks of Anachip Corp.
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