ANACHIP PEEL16CV8T-25

Features
PEEL™ 16CV8 -25
CMOS Programmable Electrically Erasable Logic Device
Compatible with Popular 16V8 Devices
- 16V8 socket and function compatible
- Programs with standard 16V8 JEDEC file
- 20-pin DIP, SOIC, TSSOP, and PLCC
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Application Versatility
- Replaces random logic
- Super sets standard 20-pin PLDs (PALs)
Multiple Speed, Power Options
- Speeds range 25ns
- Power as low as 37mA @ 25mHZ
Development / Programmer Support
- Third party software and programmers
- Anachip WinPLACE Development Software
- Automatic programmer translation and JEDEC file translation
software available for the most popular PAL devices
General Description
The PEELTM 16CV8 is a Programmable Electrically Erasable Logic
(PEEL) device providing an attractive alternative to ordinary PLDs. The
PEELTM 16CV8 offers the performance, flexibility, ease of design and
production practicality needed by logic designers today.
The PEELTM 16CV8 architecture allows it to replace over standard 20pin PLDs (PAL, GAL, EPLD etc.). See Figure 2. Anachip’s PEELTM
16CV8 can be programmed with existing 16CV8 JEDEC file. Some programmers also allow the PEELTM 16CV8 to be programmed directly
from PLD 16L8, 16R4, 16R6 and 16R8 JEDEC files. Additional development and programming support for the PEELTM16CV8 is provided by
popular third-party programmers and development software. Anachip
also offers free WinPLACE development software.
The PEELTM 16CV8 is available in 20-pin DIP, PLCC, SOIC and TSSOP
packages (see Figure 1) with 25ns speed and power consumption as low
as 37mA. EE-Reprogrammability provides the convenience of instant
reprogramming for development and reusable production inven- tory
minimizing the impact of programming changes or errors. EEReprogrammability also improves factory testability, thus assuring the
highest quality possible.
Figure 1 - Pin Configuration
Figure 2 - Block Diagram
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under
any patent accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
1/11
Functional Description
The PEELTM 16CV8 implements logic functions as sum-of- products
expressions in a programmable-AND/fixed-OR logic array. User-defined
functions are created by programming the connections of input signals
into the array. User-configurable output structures in the form of macrocells further increase logic flexibility.
64 product terms:
-56 product terms (arranged in 8 groups of 7) form sum-of-product
functions for macrocell combinatorial or registered logic
-8 product terms (arranged 1 per macrocell) add an additional
product term for macrocell sum-of-products functions or I/O pin
output enable control
At each input-line/product-term intersection there is an EEPROM memory cell which determines whether or not there is a logical connection at
that intersection. Each product term is essentially a 32-input AND gate. A
product term which is connected to both the true and complement of an
input signal will always be FALSE and thus will not affect the OR
function that it drives. When all the connections on a product term are
opened, that term will always be TRUE.
Architecture Overview
The PEELTM 16CV8 features ten dedicated input pins and eight I/O pins,
which allow a total of up to 16 inputs and 8 outputs for creating logic
functions. At the core of the device is a programmable electrically-erasable AND array which drives a fixed OR array. With this structure the
PEELTM 16CV8 can implement up to 8 sum-of-products logic expressions.
Associated with each of the eight OR functions is a macrocell which can
be independently programmed to one of up to four different basic configurations. The programmable macrocells allow each I/O to create
sequential or combinatorial logic functions of active-high or active-low
polarity, while providing two possible feedback paths into the array.
Three different device modes, Simple, Complex, and Registered, support various user configurations. In Simple mode a macrocell can be
configured for combinatorial function with the output buffer permanently
enabled, or the output buffer can be disabled and the I/O pin used as a
dedicated input. In Complex mode a macrocell is configured for combinatorial function with the output buffer enable controlled by a product
term. In Registered mode, a macrocell can be configured for registered
operation with the register clock and output buffer enable controlled
directly from pins, or can be configured for combinatorial function with the
output buffer enable controlled by a product term. In most cases the
device mode is set automatically by the development software, based on
the features specified in the design.
When programming the PEELTM 16CV8, the device programmer first
performs a bulk erase to remove the previous pattern. The erase cycle
opens every logical connection in the array. The device is configured to
perform the user-defined function by programming selected connections
in the AND array. (Note that PEELTM device programmers automatically
program all of the connections on unused product terms so that they will
have no effect on the output function.
Table 1 : PEELTM 16CV8 Device Compatibility
PLD Architecture
PEELTM 16CV8
Compatibility
Device Mode
10H8
10L8
10P8
12H6
12L6
12P6
14H4
14L4
14P4
16H2
16HD8
16L2
16LD8
16P2
16H8
16L8
16P8
16R4
16R6
16R8
16RP4
The three device modes support designs created explicitly for the
PEELTM 16CV8, as well as designs created originally for popular PLD
devices such as the 16R4, 16R8, and 16L8. Table 1 shows the device
mode used to emulate the various PLDs. Design conversion into the
16CV8 is accommodated by JEDEC-to-JEDEC translators available
from Anachip, as well as several programmers which can read the original PLD JEDEC file and automatically program the 16CV8 to perform the
same function.
AND/OR Logic Array
The programmable AND array of the PEELTM 16CV8 is formed by input
lines intersecting product terms. The input lines and product terms are
used as follows:
32 input lines:
-16 input lines carry the true and complement of the signals applied
to the 8 dedicated input pins
-16 additional lines carry the true and complement of 8 macrocell
feedback signals or inputs from I/O pins or the clock/ OE pins
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Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Complex
Complex
Complex
Registered
Registered
Registered
Registered
Rev. 1.0 Dec 16, 2004
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Simple Mode
Table 1 : PEEL TM 16CV8 Device Compatibility
PLD Architecture
Compatibility
In Simple mode, all eight product terms feed the OR array which can
generate a purely combinatorial function for the output pin. The programmable output polarity selector allows active-high or active-low logic,
PEELTM 16CV8
Device Mode
16RP6
Registered
14RP8
Registered
eliminating the need for external inverters. For output functions, the
buffer can be permanently enabled. Feedback into the array is available
on all macrocell I/O pins, except for pins 15 and 16. Figure 6 shows the
logic array of the PEELTM 16CV8 configured in Simple mode.
Programmable Macrocell
The macrocell provides complete control over the architecture of each
output. The ability to configure each output independently permits users
to tailor the configuration of the PEELTM 16CV8 to the precise requirements of their designs.
Simple mode also provides the option of configuring an I/O pin as a dedicated input. In this case, the output buffer is permanently disabled, and
the I/O pin feedback is used to bring the input signal from the pin into the
logic array. This option is available for all I/O pins except pins 15 and 16.
Figure 3 shows the possible Simple mode macrocell configurations.
Macrocell Architecture
Each macrocell consists of an OR function, a D-type flip-flop, an output
polarity selector, and a programmable feedback path. Four EEPROM
architecture bits MS0, MS1, OP, and RC control the configuration of
each macrocell. Bits MS0 and MS1 are global, and select between Simple, Complex, and Registered mode for the whole device. Bits OP and
RC are local for each macrocell; bit OP controls the output polarity and bit
RC selects between registered and combinatorial operation and also
specifies the feedback path. Table 2 shows the architecture bit settings
for each possible configuration.
1 Simple Mode
Active Low Output
2
VCC
3
Equivalent circuits for the possible macrocell configurations are illustrated in Figures 3, 4, and 5. When creating a PEELTM device design, the
desired macrocell configuration generally is specified explicitly in the
design file. When the design is assembled or compiled, the macrocell
configuration bits are defined in the last lines of the JEDEC programming file.
Simple Mode
Active High Output
VCC
Simple Mode
I/O Pin Input
Figure 3 - Macrocell Configurations for Simple mode of the PEELTM
16CV8 (see Figure 6 for Logic Array)
Table 2 : PEEL TM 16CV8 Device Mode/Macrocell Configuration Bits
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Complex Mode
In Complex mode, seven product terms feed the OR array which can
generate a purely combinatorial function for the output pin. The programmable output polarity selector provides active-high or active-low
logic, eliminating the need for external inverters. The output buffer is
controlled by the eighth product term, allowing the macrocell to be configured for input, output, or bidirectional functions. Feedback into the
array for input or bidirectional functions is available on all pins except 12
and 19. Figure 4 shows the possible complex mode macrocell configurations.
1
Registered Mode
Active Low Registered Output
2
Complex Mode
Active Low Output
Active High Registered Output
OE PIN
OE PIN
D
Q
D
Q
Q
Q
CLK PIN
3
Registered Mode
Active Low Combinatorial Output
PRODUCT TERM
1
2 Registered Mode
CLK PIN
4
Registered Mode
Active High Combinatorial Output
PRODUCT TERM
Complex Mode
Active High Output
PRODUCT TERM
Figure 5 - Macrocell Configurations for the Registered Mode of the
PEELTM 16CV8 (see Figure 8 for logic Array)
PRODUCT TERM
Design Security
The PEELTM 16CV8 provides a special EEPROM security bit that prevents unauthorized reading or copying of designs programmed into the
device. The security bit is set by the PLD programmer, either at the conclusion of the programming cycle or as a separate step, after the device
has been programmed. Once the security bit has been set it is impossible to verify (read) or program the PEELTM until the entire device has first
been erased with the bulk-erase function.
Figure 4 - Macrocell Configurations for the Complex Mode of the
PEELTM 16CV8 (see Figure 7 for Logic Array)
Registered Mode
Registered mode provides eight product terms to the OR array for registered functions. The programmable output polarity selector provides
active-high or active-low logic, eliminating the need for external inverters. (Note, however, that if register is selected, the PEELTM 16CV8 reggisters power-up reset and so before the first clock arrives the output at
the pin will be low if the user has selected active-high logic and high if the
user has selected active-low logic. If combinatorial is selected, the output
will be a function of the logic.) For registered functions, the output buffer
enable is controlled directly from the /OE control pin. Feedback into the
array comes from the macrocell register. In Registered mode, input pins
1 and 11 are permanently allocated as CLK and /OE, respec- tively. Figure
8 shows the logic array of the PEELTM 16CV8 configured in Registered
mode.
Signature Word
The signature word feature allows a 64-bit code to be programmed into
the PEELTM 16CV8. The code cannot be read back after the security bit
has been set. The signature word can be used to identify the pattern
programmed into the device or to record the design revision, etc.
Registered mode also provides the option of configuring a macrocell for
combinatorial operation, with seven product terms feeding the OR function.
Again the programmable output polarity selector provides active-high or
active-low logic. The output buffer enable is controlled by the eighth
product term, allowing the macrocell to be configured for input, output, or
bidirectional functions. Feedback into the array for input or bidirectional
functions is available on all I/O pins. Macrocell Configurations for the
Registered Mode of the PEELTM 16CV8
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1
I
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
I/O
12
I/O
MACRO
CELL
2
I
MACRO
CELL
I
3
MACRO
CELL
I
4
MACRO
CELL
I
5
MACRO
CELL
I
6
MACRO
CELL
I
7
MACRO
CELL
I
8
MACRO
CELL
I9
11
Figure 6 - PEEL TM 16CV8 Logic Array - Simple Mode (see Figure 3 for macrocell details)
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CLK
1
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
OE
MACRO
CELL
I
2
MACRO
CELL
I
3
MACRO
CELL
I
4
MACRO
CELL
I
5
MACRO
CELL
I
6
MACRO
CELL
I
7
MACRO
CELL
I
8
MACRO
CELL
I
9
Figure 8 - PEEL TM 16CV8 Logic Array - Registered Mode (see Figure 5 for macrocell details)
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This device has been designed and tested for the specified operating
ranges. Improper operation outside of these levels is not guaranteed.
Exposure to absolute maximum ratings may cause permanent damage.
Absolute Maximum Ratings
Symbol
VCC
VO
IO
TST
TLT
Parameter
Supply Voltage
Voltage Applied to Any Pin2
Output Current
Storage Temperature
Lead Temperature
Conditions
Relative to Ground
Relative to Ground1
Per Pin (IOL, IOH)
Soldering 10 Seconds
Rating
Unit
-0.5 to +6.0
-0.5 to VCC +0.6
+25
-65 to +150
+300
V
V
mA
o
C
o
C
Min
Max
Unit
4.75
0
5.25
+70
20
20
250
V
C
ns
ns
ms
Operating Range
Symbol
Parameter
VCC
TA
TR
TF
TRVCC
Supply Voltage
Ambient Temperature
Clock Rise Time
Clock Fall Time
VCC Rise Time
Conditions
Commercial
Commercial
See Note 3.
See Note 3.
See Note 3.
o
D.C. Electrical Characteristics Over the operating range (Unless otherwise specified)
Symbol
Parameter
VOH
VOHC
VOL
VOLC
VIH
VIL
IIL
Output HIGH Voltage – TTL
Output HIGH Voltage – CMOS
Output LOW Voltage – TTL
Output LOW Voltage – CMOS
Input HIGH level
Input LOW Voltage
Input, I/O Leakage Current LOW
IIH
Input, I/O Leakage Current HIGH
ICC
10
CIN7
COUT7
VCC Current, f=1MHz
Input Capacitance
Output Capacitance
Conditions
Min
VCC=Min, IOH=-4.0mA
VCC=Min, IOH=-10µA
VCC=Min, IOL=16mA
VCC=Min, IOL=10µA
2.0
-0.3
VCC=Max, VIN=GND,
I/O=High Z
VCC=Max, VIN=GND,
I/O=High Z
VIN=0V or VCC,
F=25MHz
All Outputs disabled4
TA=25oC, VCC=5.0V
@f=1MHz
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Max
Unit
0.5
0.15
VCC+0.3
0.8
V
V
V
V
V
V
-10
µA
40
µA
37
mA
6
12
pF
pF
2.4
VCC-0.3
0(Typical)
-25
Rev. 1.0 Dec 16, 2004
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A. C. Electrical Characteristics
Symbol
tPD
tOE
tOD
tCO1
tCO2
tCF
tSC
tHC
tCL, tCH
tCP
fMAX1
fMAX2
fMAX3
tAW
tAP
tAR
tRESET
Over the Operating Range 8, 11
Parameter
Min
Input5 to non-registered output
Input5 to output enable6
Input5 to output disable6
Clock to Output
Clock to comb. Output delay
Via internal registered feedback
Clock to Feedback
Input5 or feedback setup to clock
Input5 hold after clock
Clock low time, clock high time8
Min clock period Ext (tSC + tCO1)
Internal feedback (1/tSC +tCF)11
External Feedback (1/tCP)11
No Feedback (1/tCL +tCH)11
Asynchronous Reset Pulse Width
5
Input to Asynchronous Reset
Asynchronous Reset recovery time
Power-on reset time for registers in clear
state
Max
Unit
25
25
25
15
ns
ns
ns
ns
35
ns
10
25
25
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
5
µs
20
0
15
35
28.5
28.5
33.3
25
Switching Waveforms
Inputs, I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs
Notes:
8. Test conditions assume: signal transition times of 3ns or less from the 10% and 90%
points, timing reference levels of 1.5V (Unless otherwise specified).
9. Test one output at a time for a duration of less than 1 second.
10. ICC for a typical application: This parameter is tested with the device programmed as an
8-bit Counter.
11. Parameters are not 100% tested. Specifications are based on initial characterization and
are tested after any design process modification that might affect operational fre- quency.
1. Minimum DC input is -0.5V, however, inputs may undershoot to -2.0V for periods less than
20 ns.
2. VI and VO are not specified for program/verify operation.
3. Test Points for Clock and VCC in tR and tF are referenced at the 10% and 90% levels.
4. I/O pins are 0V and VCC.
5. “Input” refers to an input pin signal.
6. tOE is measured from input transition to VREF±0.1V, TOD is measured from input transi- tion
to VOH-0.1V or VOL+0.1V; VREF=VL.
7. Capacitances are tested on a sample basis.
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Ordering Information
Part Number
Speed
Temperature
Package
PEELTM 16CV8P-25 (L)
25ns
C
P20
PEELTM 16CV8J-25 (L)
25ns
C
J20
PEELTM 16CV8S-25 (L)
25ns
C
S20
PEELTM 16CV8T-25 (L)
25ns
C
T20
Part Number
Device
Suffix
TM
PEEL 16CV8P-25X
Lead Free
Blank : Normal
L : Lead Free Package
Package
P = Plastic 300mil DIP
J = Plastic (J) Leaded Chip Carrier (PLCC)
S = SOIC
T = TSSOP
Speed
-25 = 25ns tpd
Temperature Range
(Blank) = Commercial temperature 0 to 70oC
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Anachip Corp.
Head Office
,
2F, No. 24-2, Industry E. Rd. IV, Science-Based
Industrial Park, Hsinchu, 300, Taiwan
Tel: +886-3-5678234
Fax: +886-3-5678368
Anachip USA
780 Montague Expressway, #201
San Jose, CA 95131
Tel: (408) 321-9600
Fax: (408) 321-9696
Email: sales_usa@anachip.com
Website: http://www.anachip.com
©2004 Anachip Corp.
Anachip reserves the right to make changes in specifications at any time and without notice. The information furnished by
Anachip in this publication is believed to be accurate and reliable. However, there is no responsibility assumed by Anachip for
its use nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any
patents or patent rights of Anachip. Anachip’s products are not authorized for use as critical components in life support devices
or systems.
Marks bearing © or ™ are registered trademarks and trademarks of Anachip Corp.
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