ASM34012C DATA SHEET 6F-3 NO.7, LANE 75, TA-AN ROAD, SEC.1, TAIPEI, TAIWAN, R.O.C. 台北市大安路一段75巷7號6F-3 TEL:886-2-27818277 FAX:886-2-27815779 HTTP://WWW.APLUSINC.COM.TW ASM34012C ASM34012C – VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR 1.0 General Description The ASM34012C is very low cost voice synthesizer with 4-bit microprocessor. It has various features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS technology and halt function can minimize power dissipation. Its architecture is similar to RISC, with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle, except for program branches and data table read instructions (which need two instruction cycles). 1.1 Feature Single power supply can operate from 2.4V through 5V Internal Program ROM: 4K x 10-bit 1 sets of 20-bit DPR can access up to 1024K x 10 bits data memory space Data Registers: • 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh) • Unbanked special function registers (SFR) range: 20h-3Fh I/O Ports: • PRA: 4-bit I/O Port A (2Bh) • PRB: 4-bit Output Port B (2Dh) • PRC: 4-bit Input Port C (2Fh) On-chip clock generator: Resistive Clock Drive(RM) Timer: 1 • Timer0: a 9-bit auto-reload timer/counter Stack: 2-level subroutine nesting HALT and Release from HALT function to reduce power consumption Watch Dog Timer (WDT) Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles Number of instruction: 22 1 Rev 1.2 ASM34012C FIGURE 1.1 : Block Diagram of ASM34012C Data Bus[3:0] ROM Latch PCLATCH(8) PCL(4) Stack(12) PC[11:0] (ADDR[19:12]) =00000000b (2-Level) ADDR[19:0] 0 ROM_ADDR[19:0] Instruction Bus [9:0] 1 DPR3,2,1 Instruction Latch Program (Data) ROM DPR[19:0] Instruction Decoder Control Signal DLATCH(10) ROM_Data[9:0] Data Bus[3:0] Instruction Bus [9:0] Accumlator(4) SRAM ALU(4) Immediate(4) (96 x 4) Instruction Bus [9:0] PCH(8) PRA(4) PRB(4) PRC(4) Timer0(9) 00h-1Fh 40h-7Fh Register(4) enter test mode One-Channel ( Voice synthesizer ) Reset Chip Reset Chip Clock Generator PRASL(4) VDD/GND Power on Reset RESET pin COUT OSC Test select PRA0 P1,P2,P3,P4 weak or strong pull-low for PRA, PRB, PRC COUT 2 Rev 1.2 ASM34012C FIGURE 1.2 : External ROM Map of ASM34012C PC[11:0] 12bit x 2 STACK 20-bit Data Pointer Reset Vector 00000h 00080h Reserved for Testing 00080h-003FFh 00400h Program and data ROM 00000h-00FFFh 00FFFh(4K) Data ROM 00000h-FFFFFh FFFFFh(1024Kx10-bits) 3 Rev 1.2 ASM34012C 1.2 Pin-Out ASM34012C Pin-Out VDD3 PRC1 I I PRC0/RESET I STI Std./O.D. STI Std./O.D. PRA3-1 I/O STI Std./O.D. PRA0/RESET I/O STI Std./O.D. OSC VDD1 COUT GND1 GND2 TEST VDD2 PRB0-3 PRC2-3 I I O I I O I O I GND3 I Std./O.D. STI Std./O.D. - Third Power supply during operation Input port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Input port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Mask option selected as an external RESET pin with weak pull-low capability I/O port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Output type with standard or Open-Drain output I/O port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Output type with standard or Open-Drain output Mask option selected as an external RESET pin with weak pull-low capability RM mode Oscillator input First Power supply during operation Current Output of Audio First Circuit Ground Potential Second Circuit Ground Potential Enter Test Mode. ( TEST = High ) Second Power supply during operation Output type with standard or Open-Drain output Input port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Third Circuit Ground Potential 1.3 Application circuit 4 Rev 1.2 ASM34012C 1.4 Bonding Diagram ASM34012C CHIP SIZE: X= 3090 + 100 (um), Y= 5540 + 100 (um) 1 2 3 4 5 6 7 8 9 10 11 12 ASM34012C Pad Location PAD # PAD Name 1 2 3 4 5 6 7 8 9 10 11 VDD3 PRC1 PRC0 PRA3 PRA2 PRA1 PRA0/RESET OSC VDD1 ACOUT GND1 X -1445.96 -1325.24 -1202.92 -1080.6 -958.28 -835.96 -713.64 -591.32 -414.36 -162.24 38.72 13 14 15 16 17 18 19 20 21 Chip Size: X= 3090 + 100 (um), Y= 5540 + 100 (um) PAD # PAD Name X Y Y -2656.48 -2656.48 -2656.48 -2656.48 -2656.48 -2656.48 -2656.48 -2656.48 -2656.48 -2656.48 -2650.96 5 12 13 14 15 16 17 18 19 20 21 GND2 TEST VDD2 PRB0 PRB1 PRB2 PRB3 PRC2 PRC3 GND3 118.72 319.68 575.32 714.48 836.8 959.12 1081.44 1203.76 1326.08 1449.36 Rev 1.2 -2650.96 -2656.48 -2656.48 -2656.48 -2656.48 -2656.48 -2656.48 -2656.48 -2656.48 -2656.48 ASM34012C 1.5 DC Characteristics for ASM34012C SYMBOL PARAMETER OPERATING VOLTAGE VDD Isb SUPPLY CURREN T Iop VDD MIN. TYP. MAX. UNIT 2.4 STANDBY OPERATING INPUT CURRENT /Internal pull low Iih OUTPUT HIGH CURRENT OUTPUT LOW CURRENT Ioh Iol 3 3 5 3 5 3 5 2 7 3 9 5 -5.2 3 5 3 5 -3 -8 7 20 5 V 1 1 uA CONDITION depending on Freq. 4MHz, RM in HALT Mode 4MHz, RM IO Floating 4MHz, RM in HALT Mode (IO Ports with weak pull-high pull-low) mA uA 4MHz, RM (IO ports) mA dF/F FREQUENCY STABILITY -10 10 % dF/F Fosc VARIATION -20 20 % Fosc(3v)Fosc(2.4v) Fosc (3v) VDD=3V, Rosc=790k, 4MHz FIGURE 1.3 : Frequency Range for Rosc in RM mode Resistor(k ohm) 3v Freq.(MHz) 1200 1000 820 470 2.61 3.25 3.79 6.68 Rosc & Freq. Freq. MHz 8 6.68 6 4 3.79 3.25 2 2.61 0 0 200 400 600 800 1000 1200 1400 Rosc k ohm 6 Rev 1.2