APLUS ASM5206C-1

A
PLUS MAKE YOUR PRODUCTION A-PLUS
ASM5206C
DATA SHEET
APLUS
INTEGRATED CIRCUITS INC.
Address:
3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei,
Taiwan 115, R.O.C.
(115)台北市南港區成功路㆒段 32 號 3 樓之 10.
Sales E-mail: Mr. Jason
sales@aplusinc.com.tw
TEL: 886-2-2782-9266
Technology E-mail: Mr. George
service@aplusinc.com.tw
FAX: 886-2-2782-9255
WEBSITE : http: //www.aplusinc.com.tw
ASM5206C DATA SHEET
ASM5206C – VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR
1.0 General Description
The ASM5206C is very low cost voice synthesizer with 4-bit microprocessor. It has various
features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog
timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS
technology and halt function can minimize power dissipation. Its architecture is similar to RISC,
with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle,
except for program branches and data table read instructions (which need two instruction
cycles).
1.1 Feature
Single power supply can operate from 2.4V through 5V
Internal Program ROM: 4K x 10-bit
1 sets of 18-bit DPR can access up to 160K x 10 bits data memory space
Data Registers:
• 64 x 4-bit data RAM (00-1Fh plus 40h-5Fh)
• Unbanked special function registers (SFR) range: 20h-3Fh
I/O Ports:
• PRA: 4-bit I/O Port A (2Bh)
• PRB: 2-bit Output Port B (2Dh)
On-chip clock generator:
Resistive Clock Drive(RM)
Timer: 1
• Timer0: a 9-bit auto-reload timer/counter
Stack: 2-level subroutine nesting
HALT and Release from HALT function to reduce power consumption
Watch Dog Timer (WDT)
Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles
Number of instruction: 22
The Voice function can be implemented by microprocessor instruction
•
One 8-bit COUT output for ASMxxxxx
This product is empowered by HQPCM Technology by Aplus licensed from BD&C.
1
Rev 1.0
2002/09/22
ASM5206C
FIGURE 1.1 : Block Diagram of ASM5206C
Data Bus[3:0]
ROM Latch
PCLATCH(8)
PCL(4)
Stack(12)
PC[11:0]
(ADDR[17:12])
=00000b
(2-Level)
ADDR[17:0]
Instruction Bus [9:0]
1
DPR3,2,1
Instruction
Latch
0 ROM_ADDR[17:0]
Program
(Data)
ROM
DPR[17:0]
Instruction
Decoder
Control Signal
DLATCH(10)
ROM_Data[9:0]
Data Bus[3:0]
Instruction Bus [9:0]
Accumlator(4)
SRAM
ALU(4)
Immediate(4)
PRA(4)
PRB(2)
Timer0(9)
(64 x 4)
Instruction Bus [9:0]
PCH(8)
00h-1Fh
40h-5Fh
Register(4)
enter test mode
One-Channel
( Voice synthesizer )
Reset Chip
Reset Chip
Clock Generator
PRASL(4)
VDD/GND
Power on Reset
RESET pin
COUT
OSC
Test select
PRA0
P1,P2,P3,P4
weak or strong
pull-low for PRA,
PRB, PRC
COUT
2
Rev 1.0
2002/09/22
ASM5206C
FIGURE 1.2 : External ROM Map of ASM5206C
PC[11:0]
12bit x 2 STACK
17-bit Data Pointer
Reset Vector
00000h
00080h
Reserved for Testing
00080h-003FFh
00400h
Program and data ROM
00000h-00FFFh
00FFFh(4K)
Data ROM
00000h-17FFFh
17FFFh(160Kx10-bits)
3
Rev 1.0
2002/09/22
ASM5206C
1.2 Pin-Out
ASM5206C Pin-Out
VDD
PRA3-1
I
I/O
PRA0/RESET
I/O
OSC
COUT
GND
TEST
PRB0-1
I
O
I
O
O
Power supply during operation
STI
I/O port with programmable strong pull-low or weak pull-low or
Std./O.D. fix-input-floating capability
Output type with standard or Open-Drain output
STI
I/O port with programmable strong pull-low or weak pull-low or
Std./O.D. fix-input-floating capability
Output type with standard or Open-Drain output
Mask option selected as an external RESET pin with weak pull-low capability
RM mode Oscillator input
Current Output of Audio
Circuit Ground Potential
Enter Test Mode. ( TEST = High )
Std./O.D. Output type with standard or Open-Drain output
1.3 Application circuit
4
Rev 1.0
2002/09/22
ASM5206C
1.4 Bonding Diagram
160K x 10 bit ROM
Y= 2700+80(um)
ASM5206C
1
11
CHIP SIZE: X= 1550+80(um) , Y= 2700+80(um)
10
2
3
4
5
6
7
8
9
X= 1550+80(um)
Substrate must be connected to GND.
ASM5206C Pad Location
PAD # PAD Name
1
RA3
2
RA2
3
RA1
4
RA0
5
OSC
6
GND
CHIP SIZE: X= 1550+80(um) , Y= 2700+80(um)
X
Y
PAD # PAD Name
X
Y
-664.92 -944.32
7
TEST_PAD
105.44
-1269
-664.92 -1072.44
8
COUT
303.96
-1269
-662.64
-1269
9
VDD
683.04
-1269
-468.24
-1269
10
RB0
664.92
-1068
-281.04
-1269
11
RB1
664.92
-949.6
-111.72
-1269
5
Rev 1.0
2002/09/22
ASM5206C
1.5 DC Characteristics for ASM5206C
SYMBOL
VDD
PARAMETER
OPERATING VOLTAGE
Isb
SUPPLY
CURRENT
Iop
VDD
STANDBY
OPERATING
INPUT CURRENT
/Internal pull low
Iih
Ioh
OUTPUT HIGH CURRENT
Iol
OUTPUT LOW CURRENT
DA CURRENT OUT
(FULL SCALE)
FREQUENCY
STABILITY
Cout
dF/F
dF/F
Fosc VARIATION
MIN.
2.4
TYP.
3
3
5
3
5
3
5
2
7
3
9
5
-5.2
3
5
3
5
3
5
-3
-8
7
20
4
5.2
MAX.
5.5
1
1
UNIT
V
CONDITION
depending on Freq.
4MHz, RM
in HALT Mode
4MHz, RM
IO Floating
4MHz, RM
in HALT Mode
(IO Ports with weak
pull-high pull-low)
uA
mA
uA
mA
-10
10
%
-20
20
%
4MHz, RM
(IO ports)
Fosc(3v- 2.4v)
Fosc (3v)
VDD=3V,
Rosc=820k, 4MHz
FIGURE 1.3 : Frequency Range for Rosc in RM mode
Resistor(k ohm)
3v Freq.(MHz)
1000
3.66
820
4
560
6.2
470
7.16
R o sc & Fre q .
Freq. MHz
8
7 .1 6
6 .2
6
4
4
3 .6 6
2
0
0
200
400
600
800
1000
1200
R o sc k o h m
6
Rev 1.0
2002/09/22