APLUS AV8732E

A
PLUS MAKE YOUR PRODUCTION A-PLUS
AVXX32E-B SERIES
DATA SHEET
APLUS
INTEGRATED CIRCUITS INC.
Address:
3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei,
Taiwan 115, R.O.C.
(115)台北市南港區成功路㆒段 32 號 3 樓之 10.
Sales E-mail:
sales@aplusinc.com.tw
TEL: 886-2-2782-9266
Technology E-mail:
service@aplusinc.com.tw
FAX: 886-2-2782-9255
WEBSITE : http: //www.aplusinc.com.tw
AVXX32E-B SERIES
21, 32, 43, 65 and 87 Seconds Complicate Pure Speech
Features
y Operating voltage: 2.4V~5.0V
y One single-key can implement play-all, play-next
and random function. Maximum play count is 32.
y 4-column inputs and 3-row outputs can
implement 4x4-matrix function.
y Each input can implement looping function.
y Single-key and 4-column inputs can be last-key
priority for stand-alone input or first-key priority.
y Each input trigger can select trigger mode: (For
OKY, TG0, TG1, TG2, TG3) Edge/Level,
Hold/Unhold, Retrigger/Irretrigger.
y Each input trigger can select its own debounce
time:
Fast debounce: < 200us;
Slow debounce: ~16ms (S.R.=6.0kHz)
y Support bouncing trigger solution for retrigger
application. (Second trigger force to retrigger
and slow debounce.)
y Maximum table entries are 460*8.
y Word count is only limited by ROM capacity.
y 4 output ports for Status or Led application:
Ϋʳ OP_A Status:
Busy_high ,DC_low, Stop_high,DC_high
LED: +Fast,+Slow, Dyn(7/10), Off
Ϋʳ OP_B Status:
Busy_high, DC_low, Stop_high, DC_high
LED: -Fast, -Slow, Dyn(9/10), On
Ϋʳ OP_C Status: Busy_high, DC_low,
Busy_low, DC_high
LED: +Fast, +Slow, On, Off
OP_D Status0: Busy_high, DC_low
Status1: Busy_low, DC_high
y Each output can specify its initial state (High or
Low)
y Outputs can be set as constant current
regardless of the supply voltage varied.
y Two PWM playing ports. Drive speaker or
buzzer directly (For tone only).
y One DAC playing port, together with external
bipolar to drive speaker. Ramp up/down is
automatic.
y For DAC, AVXX32E-B series supports 8
levels of current control to offer flexible choises
of corresponding BJT.
y Four-level volume control is provided for DAC or
PWM output.
y Eight-pitch control is provided.
y Voice length: 21, 32, 43, 65 and 87 seconds.
(ROM capacity : 131072*5, 196608*5, 262144*5,
393216*5 and 524288*5 bits)
y Voice algorithm: 5-bits LOG_PCM
y External resister or built-in resister for system
frequency by bonding option on the same pad.
y Sixteen default sampling frequencies are
supported. The default frequencies can be
changed by an external applying resistor.
y Support single key play on/off. (For OKY, TG0,
TG1)
y Programmable pull-high, pull-low or floating
input. (For OKY, TG0, TG1)
Ϋʳ
General Description
The AVXX32E-B is a series of single-chip
synthesizing CMOS VLSI which synthesizes voice
by LOG_PCM algorithm. Table programming and shared
multiple I/O pins make the applications flexible. Powerful
functions and pure speech architecture make the
AVXX32E-B series able to best fit most
speech applications and a best cost/performance ratio
as a result.
The programming of the AVXX32E-B
series is first to define words. Each word contains
voice data (or mute length), output method, pitch (if
pitch control enabled), and volume (if volume control
enabled). Assemble the words into sentences first,
and then the programmer can assign the sentences
to the keys corresponding to the user inputs.
The I/O pins of the AVXX32E-B series are
multiplexed. This means the users have flexible I/O
options for their applications in a minimum number of
pin counts, that is, lower cost. The users can use
maximum 4*4 matrix plus one single-key inputs, but
less outputs; or 4 maximum outputs, but less inputs.
The AVXX32E-B series support DAC or
PWM audio output, the users can select both if
necessary.
The frequency stability in the AVXX32E-B
series is outstanding. The frequency variation by
voltage change is relatively small compared to the
competitor. Furthermore, volume option offers users
flexible selection for their applications. In addition, the
AVXX32E-B series support current control for
DAC output. Thus users can choose suitable current
output for their BJT component.
The programming and the approval can be done in
the EV chip of the AVXX32E-B series. It
makes the programming and verification easy.
Please contact APLUS sales for the EV chip if
required.
10-1
Ver. 1.0
AVXX32E-B SERIES
Pin Description
Pin Name
VDD
TEST
OSC
OKY_RW3
TG0,TG1
TG2_OPD
TG3_OPC
RW1_OPB
RW2_OPA
PWM1
I/O
Power
In
In
In
Out
In
In
Out
In
Out
Out
Out
Out
Out
Out
Out
Out
PWM2
Out
Out
DAC
VSS
Pad Assign
Out
OKY
ROW3
TG2
OP_D
TG3
OP_C
ROW1
OP_B
ROW2
OP_A
PWM1
OP_A
OP_C
PWM2
OP_B
OP_D
DAC
OP_A
OP_B
OP_C
OP_D
Power
Description
Positive power supply
Test enable pad, high-active, pull-low
With resister connected to VDD for system clock
generating or connected to VSS using internal resister
Trigger input, active-high
Row output for matrix function.
Column input or stand-alone input; active-high
Column input or stand-alone input; active-high
Status output
Column input or stand-alone input; active-high
Status output
Row output for matrix function
Status output
Row output for matrix function
Status output
Voltage output to drive speaker or buzzer
Status output
Voltage output to drive speaker or buzzer
Status output
Current output for speaker application
Status output
Negative power supply
Absolute Maximum Rating
Symbol
VDD~VSS
VIN (for input)
VOUT (for all outputs)
T (operating)
T (storage)
Rating
-0.5 ~ +0.5
VSS-0.3 < VIN < VDD+0.3
VSS < VOUT < VDD
-10 ~ +60
-55 ~ +125
10-2
Unit
V
V
V
к
к
Ver. 1.0
AVXX32E-B SERIES
DC Characteristics
Symbol
VDD
Isb
Iop
Iih
Iil
Iol
Ioh
Parameter
Operating Voltage
Standby
Supply
Current
Operating
d F/F
Frequency Stability
d F/F
Frequency
Variation
difference lot
Min Typ. Max
2.4 3.0 5.0
Ϋ
Ϋ
1
Ϋ
Ϋ 400
Ϋ
Ϋ -20
Ϋ
Ϋ
20
Ϋ
Ϋ
10
Ϋ
Ϋ
-5
Input Current
Output Current
by
Unit
V
ӴA
ӴA
ӴA
ӴA
mA
mA
Ϋ
Ϋ
r5
%
Ϋ
Ϋ
r10
%
Condition
VDD=3.0V, I/O open
VDD=3.0V, No loading
VDD=3.0V, VIP=0V
VDD=3.0V, VIP=3.0V
VDD=3.0V, VOP=0.8V
VDD=3.0V, VOP=2.5V
(fOSC (4.5V)-fOSC(4.0))/
fOSC (4.5V)
VDD=4.5V
fOSC =384kHz
Function Diagram
Edge/Level mode (If sentence = word1+word2)
y Edge mode
Trigger length > Voice length
7*
$XGLR
ZRUG ZRUG
GHERXQFHWLPH
Trigger length < Voice length
7*
ZRUG ZRUG
GHERXQFHWLPH
y Level mode
Trigger length > Voice length (if sentence=word1+word2)
7*
$XGLR
ZRUG ZRUG ZRUG ZRUG
GHERXQFHWLPH
10-3
Ver. 1.0
AVXX32E-B SERIES
Trigger length < Voice length (if sentence = word1+word2)
7*
$XGLR
ZRUG ZRUG
GHERXQFHWLPH
Hold/Unhold mode (If sentence = word1+word2)
y Hold mode
7*
ZRUG
$XGLR
ZRUG
GHERXQFHWLPH
y Unhold mode
7*
$XGLR
ZRUG ZRUG
GHERXQFHWLPH
Retrigger/Irretrigger mode (If sentence = word1+word2)
y Retrigger mode (Edge Unhold mode)
7*
$XGLR
ZRUG
ZRUG
ZRUG ZRUG
GHERXQFHWLPH
y Irretrigger mode (Edge, Unhold mode)
7*
$XGLR
ZRUG ZRUG
GHERXQFHWLPH
10-4
Ver. 1.0
AVXX32E-B SERIES
Last key priority
y If TG1, TG2 are retrigger mode
7*
7*
$XGLR
7*
V
7*
V
7*
V
7*
V
Looping function
If sentence is set to looping mode (sentence1_sentence2)
y Unhold mode
7*
$XGLR
VHQWHQFH VHQWHQFH VHQWHQFH VHQWHQFH
y Hold mode
7*
VHQWHQFH
$XGLR
VHQWHQFH VHQWHQFH
Force to retrigger and slow debounce option
(Trigger mode set to Fast debounce and Irretrigger mode)
VW7*
)56%
$XGLR
'RQ
WFDUH
:
:
: :
7KLVZRUGPXVWEHODUJHUWKDQJOLWFKSHULRG
$PXWHZRUGFDQEHXVHGEHUKDSV
QG7*
)56%
$XGLR
:
: : :
6ORZGHERXQFH
5HWULJJHUPRGH
6ORZGHERXQFH
5HWULJJHUPRGH
)DVWGHERXQFH
,UUHWULJJHUPRGH
)DVWGHERXQFH
,UUHWULJJHUPRGH
Busy=0, FRSB set to high;
Busy=1, depending on FRSB setting.
If FRSB=0, force to slow debounce and retrigger mode;
If FRSB=1, no change (fast debounce and irretrigger mode).
10-5
Ver. 1.0
AVXX32E-B SERIES
Stand-alone trigger inputs are enabled at the same time
OKY
COL0
COL1
COL2
COL3
Audio
This voice is enabled by COL3
Trigger input priority is COL3 > COL2 > COL1 > COL0 > OKY
Application circuit
y External resister, Driver speaker by PWM, driver LED
VDD
Rosc
OSC
OKY
OP_A
PWM1
PWM2
VSS
ROSC=200k: for frequency option 8
y Internal resister, driver speaker by PWM, driver LED
If OSC bonds to VSS, this chip uses internal resister automatically.
VDD
OKY
OP_A
OSC
PWM1
PWM2
VSS
10-6
Ver. 1.0
AVXX32E-B SERIES
y Power on play
Set the pull resisters of OKY, TG0 or TG1 to pull-high will cause the triggers to play immediately after
power on.
VDD
OSC
OP_A
PWM1
PWM2
VSS
y Matrix input
526&
9''
26&
2.<
7*
7* 7*
23B$
7*
&2/
-$
-$
-$
-$
-$
7*
&2/
7*
&2/
23B%
23B&
7*
&2/
7* 7* 7*
52:
3:0
3:0
52:
52:
966
y Driver speaker by DAC and driver Motor application
ROSC
VDD
OSC
OP_A
OKY
OP_B
+
-
Motor
OP_C
C1
DAC
Cx
Rx
VSS
10-7
Ver. 1.0
AVXX32E-B SERIES
y Stand-alone trigger input
ROSC
VDD
OSC
OP_A
OKY
OP_B
OP_C
COL0
COL1
COL2
PWM1
PWM2
COL3
VSS
Output Definition
OPA
OPB
OPC
OPD
Option
0
1
2
3
Status
BH
DL
SH
DH
Standby state
L
L
L
H
LED
+Fast
+Slow
Dy07
OFF
Standby state
H
H
H
H
Status
BH
DL
SH
DH
Standby state
L
L
L
H
LED
-Fast
-Slow
Dy09
ON
Standby state
H
H
H
H
Status
BH
DL
BL
DH
Standby state
L
L
H
H
LED
+Fast
+Slow
ON
OFF
Standby state
H
H
H
H
Status1
BH
DL
Standby state
L
L
Satatus2
BH
DL
Standby state
H
H
10-8
Ver. 1.0
AVXX32E-B SERIES
Bonding Diagram
Y
VSS
PWM2
PWM1
VDD
DAC
TG0
OSC
TG1
RW2_OPA
OKY_RW3
TG3_OPC
RW1_OPB
TEST
TG2_OPD
X
Note: The IC substrate should be connect to VSS
(1) AV2132E
PIN Name
OKY_RW3
RW2_OPA
RW1_OPB
TG3_OPC
TG2_OPD
TEST
OSC
TG1
DAC
TG0
VSS
PWM2
PWM1
VDD
X(mm)
250.75
451.50
660.25
861.00
1069.75
1270.25
94.00
1313.25
94.00
1313.25
410.75
631.00
1049.50
1331.00
Y(mm)
94.00
94.25
94.25
94.25
94.25
94.25
271.25
297.00
472.25
501.00
1419.50
1440.00
1440.00
1440.00
DIE SIZE = 1510 * 1655 Pm^2 (X*Y)
(2) AV3232E
PIN Name
OKY_RW3
RW2_OPA
RW1_OPB
TG3_OPC
TG2_OPD
TEST
OSC
TG1
DAC
TG0
VSS
PWM2
PWM1
VDD
X(mm)
250.75
451.50
660.25
861.00
1069.75
1270.25
94.00
1313.25
94.00
1313.25
410.75
631.00
1049.50
1331.00
Y(mm)
94.00
94.25
94.25
94.25
94.25
94.25
271.25
297.00
472.25
501.00
1649.50
1670.00
1670.00
1670.00
DIE SIZE = 1510 * 1885 Pm^2 (X*Y)
10-9
Ver. 1.0
AVXX32E-B SERIES
(3) AV4332E
PIN Name
OKY_RW3
RW2_OPA
RW1_OPB
TG3_OPC
TG2_OPD
TEST
OSC
TG1
DAC
TG0
VSS
PWM2
PWM1
VDD
X(mm)
250.75
451.50
660.25
861.00
1069.75
1270.25
94.00
1313.25
94.00
1313.25
410.75
631.00
1049.50
1331.00
Y(mm)
94.00
94.25
94.25
94.25
94.25
94.25
271.25
297.00
472.25
501.00
1870.50
1890.25
1890.25
1890.25
DIE SIZE = 1510 * 2115 Pm^2 (X*Y)
X(mm)
259.25
460.00
668.75
869.50
1078.25
1278.75
102.50
1321.75
102.50
1321.75
419.25
639.50
1058.00
1271.25
Y(mm)
94.00
94.25
94.25
94.25
94.25
94.25
271.25
297.00
472.25
501.00
2322.50
2342.25
2342.25
2364.25
DIE SIZE = 1427.25 * 2457.50 Pm^2 (X*Y)
X(mm)
266.00
466.75
675.50
876.25
1085.00
1285.50
109.25
1328.50
109.25
1328.50
426.00
646.25
1064.75
1271.25
Y(mm)
94.00
94.25
94.25
94.25
94.25
94.25
271.25
297.00
472.25
501.00
2801.25
2821.00
2821.00
2815.00
DIE SIZE = 1427.25 * 2908.25 Pm^2 (X*Y)
(4) AV6532E
PIN Name
OKY_RW3
RW2_OPA
RW1_OPB
TG3_OPC
TG2_OPD
TEST
OSC
TG1
DAC
TG0
VSS
PWM2
PWM1
VDD
(5) AV8732E
PIN Name
OKY_RW3
RW2_OPA
RW1_OPB
TG3_OPC
TG2_OPD
TEST
OSC
TG1
DAC
TG0
VSS
PWM2
PWM1
VDD
10-10
Ver. 1.0