SGLS141 – DECEMBER 2002
D Qualification in Accordance With
D
D
D
D
D
D
D
D
D
D
AEC-Q100†
Qualified for Automotive Applications
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval†
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Supply Current of 220 nA (Typ)
Precision Supply Voltage Supervision
Range: 1.8 V, 2.5 V, 3.0 V, 3.3 V
Power-On Reset Generator With Selectable
Delay Time of 10 ms or 200 ms
Push/Pull RESET Output (TPS3836),
RESET Output (TPS3837), or
Open-Drain RESET Output (TPS3838)
Manual Reset
5-Pin SOT-23 Package
Temperature Range –40°C to 125°C
D Applications Include
– Applications Using Automotive
Low-Power DSPs, Microcontrollers, or
Microprocessors
– Battery-Powered Equipment
– Intelligent Instruments
– Wireless Communication Systems
– Automotive Systems
TPS3836, TPS3838
DBV PACKAGE
(TOP VIEW)
CT
1
GND
2
MR
3
5
VDD
4
RESET
TPS3837
DBV PACKAGE
(TOP VIEW)
† Contact factory for details. Q100 qualification data available on
request.
description
CT
1
GND
2
MR
3
5
VDD
4
RESET
The TPS3836, TPS3837, TPS3838 families of
supervisory circuits provide circuit initialization
and timing supervision, primarily for DSP and
processor-based systems.
During power on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the
supervisory circuit monitors VDD and keeps RESET output active as long as VDD remains below the threshold
voltage VIT. An internal timer delays the return of the output to the inactive state (high) to ensure proper system
reset. The delay time starts after VDD has risen above the threshold voltage VIT.
When CT is connected to GND a fixed delay time of typical 10 ms is asserted. When connected to VDD the delay
time is typically 200 ms.
When the supply voltage drops below the threshold voltage VIT, the output becomes active (low) again.
All the devices of this family have a fixed-sense threshold voltage VIT set by an internal voltage divider.
The TPS3836 has an active-low push-pull RESET output. The TPS3837 has active-high push-pull RESET, and
TPS3838 integrates an active-low open-drain RESET output.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
! ! "#$%&'()"%# "* +,&&-#) (* %$ .,/0"+()"%# 1()-2
&%1,+)* +%#$%&' )% *.-+"$"+()"%#* .-& )3- )-&'* %$ -4(* #*)&,'-#)*
*)(#1(&1 5(&&(#)62 &%1,+)"%# .&%+-**"#7 1%-* #%) #-+-**(&"06 "#+0,1)-*)"#7 %$ (00 .(&('-)-&*2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SGLS141 – DECEMBER 2002
description (continued)
TPS3836K33
VDD
MSP430
VCC
CT
Xin
RESET
RST
MR
T
Xout
Quartz
32 kHz
VSS
GND
Lithium
Battery
3.6 V
TYPICAL OPERATING CIRCUIT
The product spectrum is designed for supply voltages of 1.8 V, 2.5 V, 3 V, and 3.3 V. The circuits are available
in a 5-pin SOT-23 package. The TPS3836-Q-Q1, TPS3837-Q-Q1, TPS3838-Q-Q1 families are characterized
for operation over a temperature range of –40°C to 125°C, and qualified in accordance with AEC-Q100 stress
test qualification for integrated circuits.
PACKAGE INFORMATION
TA
–40°C
125°C
40 C to 125
C
DEVICE NAME
THRESHOLD VOLTAGE
SYMBOL
TPS3836E18QDBVRQ1†
TPS3836J25QDBVRQ1†
1.71 V
PDNQ
2.25 V
PDSQ
TPS3836H30QDBVRQ1†
TPS3836L30QDBVRQ1†
2.79 V
PHRQ
2.64 V
PCAQ
TPS3836K33QDBVRQ1†
TPS3837E18QDBVRQ1†
2.93 V
PDTQ
1.71 V
PDOQ
TPS3837J25QDBVRQ1†
TPS3837L30QDBVRQ1†
2.25 V
PDRQ
2.64 V
PCBQ
TPS3837K33QDBVRQ1†
TPS3838E18QDBVRQ1†
2.93 V
PDUQ
1.71 V
PDQQ
TPS3838J25QDBVRQ1†
TPS3838L30QDBVRQ1†
2.25 V
PDPQ
2.64 V
PCCQ
TPS3838K33QDBVRQ1†
2.93 V
PDVQ
† The DBVR passive indicates tape and reel of 3000 parts.
ORDERING INFORMATION
TPS383 6 E 18 Q DBV R Q1
Q100 Designator
Reel
Package
Q-Temperature Designator
Nominal Supply Voltage
Typical Reset Threshold Voltage
Functionality
Family
2
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• DALLAS, TEXAS 75265
SGLS141 – DECEMBER 2002
FUNCTION TABLE TPS3836, TPS3837, TPS3838
VDD > VIT
RESET†
RESET‡
MR
L
0
L
H
L
1
L
H
H
0
L
H
H
L
H
1
† TPS3836 and TPS3838
‡ TPS3837
functional block diagram
VDD
CT
R3
MR
C1
R1
+
S1
Reset Logic
and Timer
–
Reset (TPS3837-Push-Pull)
Reset (TPS3836-Push-Pull
TPS3838-Open-Drain)
R2
C2
S2
Band-Gap
Reference
S3
C3
Refresh
Timer
GND
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SGLS141 – DECEMBER 2002
timing diagram
A
B
C
D
E
F
G
VDD
VIT
< 1.1 V
t
MR
t
RESET
t
Undefined
Output
4
td
POST OFFICE BOX 655303
td
• DALLAS, TEXAS 75265
td
Undefined
Output
SGLS141 – DECEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Maximum low output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Maximum high output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 mA
Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND. For reliable operation, the device must not be operated at 7 V for more than t=1000 h
continuously
DISSIPATION RATING TABLE
PACKAGE
TA <25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
DBV
437 mW
3.5 mW/ºC
280 mW
227 mW
87 mW
recommended operating conditions at specified temperature range
MIN
Supply voltage, VDD
Input voltage, VI
MAX
UNIT
1.6
6
V
0
VDD + 0.3
V
0.7 × VDD
High-level input voltage, VIH
V
0.3 × VDD
Low-level input voltage, VIL
Input transition rise and fall rate at MR, ∆t/∆V
Operating free-air temperature range, TA
–40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
100
ns/V
125
°C
5
SGLS141 – DECEMBER 2002
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
VOH
VOL
Vhys
IIH
RESET
(TPS3836)
VDD = 3.3 V,
VDD = 6 V,
RESET
(TPS3837)
VDD = 1.8 V,
VDD = 3.3 V,
RESET
(TPS3836/8)
VDD = 1.8 V,
VDD = 3.3 V,
RESET
(TPS3837)
VDD = 3.3 V,
VDD = 6 V,
TPS3836/8
VDD ≥ 1.1 V,
IOL = 3 mA
IOL = 50 µA
TPS3837
VDD ≥ 1.1 V,
IOH = –50 µA
High le el output
High-level
o tp t voltage
oltage
Low level output voltage
Low-level
Power-up
Po
er p reset voltage
oltage
(see Note 2)
VIT
TEST CONDITION
Negative-going
N
ti
i input
i
t threshold
th h ld
voltage (see Note 3)
IIL
Low-level
Low
level input
in ut current
IOH
High-level output current
IDD
Supply
Su
ly current
Input capacitance at MR, CT
MAX
0.8 ×
VDD
V
IOL = 2 mA
IOL = 2 mA
04
0.4
0.8 ×
VDD
V
1.64
1.71
1.76
2.16
2.25
2.30
TPS383xH30
2.70
2.79
2.85
TPS383xL30
2.54
2.64
2.71
TPS383xK33
2.82
2.93
3.10
1.7 V < VIT < 2.5 V
30
2.5 V < VIT < 3.5 V
40
3.5 V < VIT < 5 V
50
MR
(see Note 4)
MR = 0.7 × VDD,
CT
CT = VDD = 6 V
MR
(see Note 4)
MR = 0 V,
VDD = 6 V
CT
CT = 0 V,
TPS3838
VDD = VIT + 0.2 V,
VDD > VIT,
VDD = 6 V
VOH = VDD
VDD = 6 V
–40
–60
–25
VDD < 3 V
VDD > 3 V
VI = 0 V to VDD
V
0.2
TPS383xJ25
VDD > VIT,
VDD < VIT
UNIT
IOL = –2 mA
IOL = 1 mA
Internal pullup resistor at MR
CI
TYP
TPS383xE18
Hysteresis at VDD in
input
ut
High-level
High
level in
input
ut current
IOH = –2 mA
IOH = –3 mA
IOH = –1 mA
MIN
–130
–200
–25
V
mV
–100
µA
25
nA
–340
µA
25
nA
25
nA
220
500
250
550
10
25
nA
µA
30
kΩ
5
pF
NOTES: 2. The lowest voltage at which RESET output becomes active. tr, VDD ≥ 15 µs/V
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near the supply terminal.
4. If manual reset is unused, MR should be connected to VDD to minimize current consumption.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SGLS141 – DECEMBER 2002
timing requirements at RL = 1 MΩ, CL = 50 pF, TA = 25_C
PARAMETER
tw
Pulse width
TEST CONDITIONS
MIN
TYP
MAX
UNIT
at VDD
VIH = VIT + 0.2 V,
VIL = VIT – 0.2 V
6
µs
at MR
VDD ≥ VIT + 0.2 V,
VIH = 0.7 × VDD
VIL = 0.3 × VDD,
1
µs
switching characteristics at RL = 1 MΩ, CL = 50 pF, TA = 25_C
PARAMETER
TEST CONDITIONS
MIN
VDD ≥ VIT + 0.2 V,
MR = 0.7 × VDD,
CT = GND,
See timing diagram
td
tPHL
tPLH
Delay time
VDD ≥ VIT + 0.2 V,
MR = 0.7 × VDD,
CT = VDD ,
See timing diagram
Propagation
Pro
agation (delay) time, high
high-to-low-level
to low level output
out ut
Propagation
Pro
agation (delay) time, low
low-to-high-level
to high level output
out ut
VDD to RESET delay
(TPS3836 TPS3838)
(TPS3836,
VDD to RESET delay
(TPS3837)
5
TYP
MAX
10
UNIT
15
ms
100
200
300
VIL = VIT – 0.2 V,
VIH = VIT + 0.2 V
10
µs
VIL = 1.6 V
VIL = VIT – 0.2 V,
VIH = VIT + 0.2 V
50
VIL = 1.6 V
50
0.1
µs
0.1
µs
tPHL
Propagation (delay) time, high-to-low-level output
MR to RESET delay
(TPS3836, TPS3838)
VDD ≥ VIT + 0.2 V,
VIL = 0.3 × VDD,
tPLH
Propagation (delay) time, low-to-high-level output
MR to RESET delay
(TPS3837)
VIL = 0.7 × VDD
10
µs
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
IDD
IMR
Supply current
vs Supply voltage
1
Manual reset current
vs Manual reset voltage
2
VOL
VOH
Low-level output voltage
vs Low-level output current
3
High-level output voltage
vs High-level output current
4
Normalized reset threshold voltage
vs Free-air temperature
5
Minimum pulse duration at VDD
vs VDD Threshold overdrive
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SGLS141 – DECEMBER 2002
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
MANUAL RESET CURRENT
vs
MANUAL RESET VOLTAGE
10
100
MR = Open
CT = GND
VDD = 6 V
CT = GND
IMR – Manual Reset Current – µA
TA = 85°C
IDD – Supply Current – µA
8
TA = 25°C
6
TA = 0°C
4
TA = –40°C
2
0
0
TA = –40°C
–100
TA = 0°C
–200
TA = 25°C
–300
TA = 85°C
–400
–500
0
2
4
6
–2
0
VDD – Supply Voltage – V
Figure 1
6
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
2.0
2.0
VDD = 2 V
MR = OPEN
CT = GND
VOH – High-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
4
Figure 2
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1.5
TA = 25°C
1.0
TA = 85°C
TA = 0°C
0.5
TA = –40°C
0.0
VDD = 2 V
MR = OPEN
CT = GND
1.5
TA = 85°C
TA = 25°C
1.0
TA = 0°C
0.5
TA = –40°C
0.0
0
1
2
3
4
5
6
7
IOL – Low-Level Output Current – mA
Figure 3
8
2
VMR – Manual Reset Voltage – V
POST OFFICE BOX 655303
0
1
2
3
4
IOH – High-Level Output Current – mA
Figure 4
• DALLAS, TEXAS 75265
5
SGLS141 – DECEMBER 2002
TYPICAL CHARACTERISTICS
NORMALIZED RESET THRESHOLD
VOLTAGE
vs
FREE-AIR TEMPERATURE
Normalized Reset Threshold Voltage – V
1.001
1
0.999
0.998
0.997
CT = GND,
MR = Open
0.996
0.995
–40
–15
10
35
60
TA – Free-Air Temperature – °C
85
Figure 5
MINIMUM PULSE DURATION AT VDD
vs
VDD THRESHOLD OVERDRIVE
22
MR = Open
CT = GND
TA = 25°C
Minimum Pulse Duration at VDD – µs
20
18
16
14
12
10
8
6
4
2
0
0
0.2
0.4 0.6
0.8
1
1.2 1.4
1.6 1.8
2
VDD – Threshold Overdrive – V
Figure 6
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9
SGLS141 – DECEMBER 2002
MECHANICAL DATA
DBV (R-PDSO-G5)
PLASTIC SMALL-OUTLINE
0,95
5X
5
0,50
0,20 M
0,30
4
1,70
1,50
1
0,15 NOM
3,00
2,60
3
Gage Plane
3,00
2,80
0,25
0°–8°
0,55
0,35
Seating Plane
1,45
0,95
0,05 MIN
0,10
4073253-4/G 01/02
NOTES: A.
B.
C.
D.
10
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-178
POST OFFICE BOX 655303
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
TPS3836E18QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
None
Call TI
Level-1-220C-UNLIM
TPS3836H30QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
None
Call TI
Level-1-220C-UNLIM
TPS3836J25QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
None
Call TI
Level-1-220C-UNLIM
TPS3836K33QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
None
Call TI
Level-1-220C-UNLIM
TPS3836L30QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
None
Call TI
Level-1-220C-UNLIM
TPS3837E18QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
None
Call TI
Level-1-220C-UNLIM
TPS3837J25QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
None
Call TI
Level-1-220C-UNLIM
TPS3837K33QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
None
Call TI
Level-1-220C-UNLIM
TPS3837L30QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
None
Call TI
Level-1-220C-UNLIM
TPS3838E18QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
None
Call TI
Level-1-220C-UNLIM
TPS3838J25QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
None
Call TI
Level-1-220C-UNLIM
TPS3838K33QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
None
Call TI
Level-1-220C-UNLIM
TPS3838L30QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
None
Call TI
Level-1-220C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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