ADS7803 ® Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● LOW POWER: 10mW plus Power Down The ADS7803 is a monolithic CMOS 12-bit analogto-digital converter with internal sample/hold and fourchannel multiplexer. It is designed and tested for full dynamic performance with input signals to 50kHz. An autocalibration cycle guarantees a total unadjusted error within ±3/4LSB over the specified temperature range, eliminating the need for offset or gain adjustment. The 5V single-supply requirements and standard CS, RD, and WR control signals make the part easy to use in microprocessor applications. Conversion results are available in two bytes through an 8-bit three-state output bus. ● SIGNAL-TO-(NOISE + DISTORTION) RATIO OVER TEMPERATURE: 69dB min with fIN = 1kHz 66dB min with fIN = 50kHz ● FAST CONVERSION TIME: 8.5µs Including Acquisition (117kHz Sampling Rate) ● DC PERFORMANCE OVER TEMPERATURE: ±3/4 LSB max Total Error ±1/4 LSB max Channel Mismatch ● FOUR-CHANNEL INPUT MULTIPLEXER ● SINGLE SUPPLY: +5V ● PIN COMPATIBLE WITH ADC7802 A0 A1 AIN0 AIN1 AIN2 AIN3 Address Latch and Decoder Analog Multiplexer The ADS7803 is available in a 28-pin plastic DIP and 28-lead PLCC, fully specified for operation over the industrial –40°C to +85°C temperature range. Calibration Microcontroller and Memory Capacitor Array Sampling ADC VREF+ Clock Control Logic Three-State Input/Output CS RD WR SFR BUSY 8-Bit Data Bus VREF– International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © PDS-1126A 1991 Burr-Brown Corporation Printed in U.S.A. August, 1993 SPECIFICATIONS ELECTRICAL VA = VD = VREF+ = 5V ±5%; VREF– = AGND = DGND = 0V; CLK = 2MHz external, TA = –40°C to +85°C, after calibration at any temperature, unless otherwise specified. ADS7803BP/ADS7803BN PARAMETER CONDITIONS MIN TYP RESOLUTION ANALOG INPUT Voltage Input Range Input Capacitance On State Bias Current Off State Bias Current On Resistance Multiplexer Off Resistance Multiplexer Channel Separation REFERENCE INPUT For Specified Performance: VREF+ VREF– For Derated Performance(1): VREF+ VREF– Input Reference Current THROUGHPUT TIMING Conversion Time With External Clock (Including Multiplexer Settling Time and Acquisition Time) With Internal Clock Using Recommended Clock Components Multiplexer Settling Time to 0.01% Multiplexer Access Time DC ACCURACY Total Error, All Channels(2) Differential Nonlinearity No Missing Codes Gain Error Gain Error Drift Offset Error Offset Error Drift Channel-to-Channel Mismatch Power Supply Sensitivity AC ACCURACY Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Signal-to-Noise Ratio Spurious Free Dynamic Range SAMPLING DYNAMICS Full Power Bandwidth Aperture Delay Offset Error DIGITAL INPUTS All Pins Other Than CLK: VIL VIH Input Current CLK Input: VIL VIH IIL IIH IIH VREF+ = 5V, VREF– = 0V 0 MAX UNITS 12 Bits 5 V pF nA nA nA kΩ MΩ dB 50 100 TA = +25°C TA = –40°C to +85°C 10 100 2 10 92 500Hz VREF+ ≤ VA 5 0 4.5 0 VREF+ = 5V, VREF– = 0V 10 CLK = 2MHz CLK = 1MHz CLK = 500kHz TA = +25°C TA = –40°C to +85°C 20 µs µs µs µs µs ns ns ±3/4 ±1/2 LSB LSB ±1/4 LSB ppm/°C LSB ppm/°C LSB LSB 8.5 17 34 10 10 460 All Channels Between Calibration Cycles All Channels Between Calibration Cycles ±1/2 ±1/4 Guaranteed ±1/8 ±0.2 ±1/8 ±0.2 VA = VD = 4.75V to 5.25V ±1/8 fIN = 1kHz fIN = 50kHz fIN = 50kHz fIN = 50kHz fIN = 1kHz fIN = 50kHz VA 1 100 69 66 –3dB SFR D2 LOW SRF D2 HIGH SFR D2 LOW SFR D2 HIGH, Internal Clock or Sampling Command Synchronous to External Clock SFR D2 HIGH, Sampling Command Asynchronous to External Clock ±1/4 ±1/4 71 69 –75 70 90 82 dB dB dB dB dB dB 4 2500 5 ±1/8 ±1/2 MHz ns ns LSB LSB ±1/4 ±1 ±4 LSB 0.8 2.4 TA = +25°C, VIN = 0 to VD TA = –40°C to +85°C, VIN = 0 to VD 1 10 0.8 3.5 Power Down Mode (D3 in SFR HIGH) V V V V µA 10 1.5 100 V V µA µA V V µA mA nA NOTES: (1) For (VREF+) – (VREF–) as low as 4.5V, the total error will typically not exceed ±1LSB. (2) After calibration cycle, without external adjustment. Includes gain (full scale) error, offset error, integral nonlinearity, differential nonlinearity, and drift. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADS7803 2 SPECIFICATIONS (CONT) ELECTRICAL VA = VD = VREF+ = 5V ±5%; VREF– = AGND = DGND = 0V; CLK = 2MHz external, TA = –40°C to +85°C, after calibration at any temperature, unless otherwise specified. ADS7803BP/ADS7803BN PARAMETER CONDITIONS DIGITAL OUTPUTS VOL VOH Leakage Current Output Capacitance MIN ISINK = 1.6mA ISOURCE = 200µA High-Z State, VOUT = 0V to VD High-Z State POWER SUPPLIES Supply Voltage for Specified Performance: VA VD Supply Current: IA ID Power Dissipation Power Down Mode TYP MAX UNITS 0.4 V V µA pF 4 ±1 15 4 4.75 4.75 VA ≥ VD 5 5 1 1 10 50 Logic Input Pins HIGH or LOW WR = RD = CS = BUSY = HIGH See Table III TEMPERATURE RANGE Specification Storage –40 –65 5.25 5.25 2.5 2 V V mA mA mW µW +85 +150 °C °C PIN CONFIGURATIONS 2 27 AGND AIN1 3 26 CAL (SHC) AIN2 4 25 A1 AIN3 5 AIN3 5 24 A0 VREF+ 6 VREF+ 6 23 CLK VREF– 7 VREF– 7 22 BUSY DGND 8 DGND 8 21 HBE VD 9 VD 9 20 WR D7 10 D7 10 19 CS D6 11 D6 11 18 RD D5 12 17 D0 D4 13 16 D1 D3 14 15 D2 CAL (SHC) AIN0 AGND 28 VA VA 1 SFR SFR AIN0 Top View AIN1 DIP AIN2 Top View 4 3 2 1 28 27 26 LCC 25 A1 24 A0 23 CLK 22 BUSY 21 HBE 20 WR 12 13 14 15 16 17 18 D5 D4 D3 D2 D1 D0 RD 19 CS ABSOLUTE MAXIMUM RATINGS VA to Analog Ground .......................................................................... 6.5V VD to Digital Ground ........................................................................... 6.5V Pin VA to Pin VD ............................................................................... ±0.3V Analog Ground to Digital Ground ........................................................ ±1V Control Inputs to Digital Ground ................................ –0.3V to VD + 0.3V Analog Input Voltage to Analog Ground .................... –0.3V to VD + 0.3V Maximum Junction Temperature ..................................................... 150°C Internal Power Dissipation ............................................................. 875mW Lead Temperature (soldering, 10s) ............................................... +300°C Thermal Resistance, θJA: Plastic DIP .......................................... 75°C/W PLCC .................................................. 75°C/W PACKAGE INFORMATION MODEL ADC7803BN ADS7803BP PACKAGE PACKAGE DRAWING NUMBER(1) 28-Pin LCC 28-Pin Plastic DIP 251 215 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION MODEL ADS7803BN ADS7803BP MINIMUM SIGNAL-TO(NOISE + DISTORTION) RATIO, dB MAXIMUM TOTAL ERROR, LSB SPECIFICATION TEMPERATURE RANGE 69 69 ±3/4 ±3/4 –40°C to +85°C –40°C to +85°C 1-24 25-99 100+ ® 3 ADS7803 TYPICAL PERFORMANCE CURVES At VA = VD = VREF+ = 5V, VREF– = AGND = 0V, TA = +25°C, dynamic performance based on 2048 point FFTs, unless otherwise noted. FREQUENCY SPECTRUM (1kHz fIN) FREQUENCY SPECTRUM (48kHz fIN) 0 0 S/(N + D) = 71.4dB fSAMPLING = 100kHz –20 –40 Magnitude (dB) –40 Magnitude (dB) S/(N + D) = 69.2dB fSAMPLING = 100kHz –20 –60 –80 –100 –60 –80 –100 –120 –120 10 0 20 30 40 50 0 10 20 Frequency (kHz) CHANNEL SEPARATION vs FREQUENCY Conversion Yielding Expected Code (%) Channel Separation (dB) 80 Channel AIN3 Channel AIN1 Channel AIN0 40 20 0 1 10 50 100 100 75 50 25 0 0 1k Frequency of 5Vp-p Signal on Channel AIN2 (kHz) 0.25 0.5 0.75 1 Analog Input Voltage – Expected Code Center (LSBs) SIGNAL/(NOISE + DISTORTION) vs INPUT FREQUENCY POWER SUPPLY REJECTION vs FREQUENCY 10 Full-Scale Error vs Change in Supply Voltage (mV/V) 72 Signal/(Noise + Distortion) (dB) 40 CODE TRANSITION NOISE 100 60 30 Frequency (kHz) 70 68 66 VA 1 VD 0.1 1 0.5 2 3 5 10 20 3 50 0.1 Input Frequency (kHz) 10 Frequency (kHz) ® ADS7803 1 4 100 1000 TYPICAL PERFORMANCE CURVES (CONT) At VA = VD = VREF+ = 5V, VREF– = AGND = 0V, TA = +25°C, dynamic performance based on 2048 point FFTs , unless otherwise noted. INTERNAL CLOCK FREQUENCY vs RCLOCK INTERNAL CLOCK FREQUENCY vs TEMPERATURE 10 1.1 Clock Frequency (MHz) Clock Frequency (MHz) 1.15 RCLOCK = 70kΩ 1.05 1 0.95 0.9 –50 1 0.1 –25 0 25 50 75 100 10 100 Ambient Temperature (°C) 1k RCLOCK (kΩ) THEORY OF OPERATION OPERATION ADS7803 uses the advantages of advanced CMOS technology (logic density, stable capacitors, precision analog switches, and low power consumption) to provide a precise 12-bit analog-to-digital converter with on-chip sampling and four-channel analog-input multiplexer. BASIC OPERATION Figure 1 shows the simple circuit required to operate ADS7803 in the Transparent Mode, converting a single input channel. A convert command on pin 20 (WR) starts a conversion. Pin 22 (BUSY) will output a LOW during the conversion process (including sample acquisition and conversion), and rises only after the conversion is completed. The two bytes of output data can then be read using pin 18 (RD) and pin 21 (HBE). The input stage consists of an analog multiplexer with an address latch to select from four input channels. The converter stage consists of an advanced successive approximation architecture using charge redistribution on a capacitor network to digitize the input signal. A temperature-stabilized differential auto-zeroing circuit is used to minimize offset errors in the comparator. Linearity errors in the binary weighted main capacitor network are corrected using a capacitor trim network and correction factors stored in on-chip memory. The correction terms are calculated by an on-chip microcontroller during a calibration cycle, initiated either by power-up or by applying an external calibration signal at any time. During conversion, the correct trim capacitors are switched into the main capacitor array as needed to correct the conversion accuracy. With all of the capacitors in both the main array and the trim array on the same chip, excellent stability is achieved, both over temperature and over time. +5V NC 0 –5V Input 1 SFR VA 28 2 AIN0 AGND 27 3 AIN1 CAL 4 AIN2 A1 25 5 AIN3 A0 24 10nF + 10µF 26 NC 100kΩ +5V + 10nF 10µF For flexibility, timing circuits include both an internal clock generator and an input for an external clock to synchronize with external systems. Standard control signals and threestate input/output registers simplify interfacing ADS7803 to most micro-controllers, microprocessors or digital storage systems. The on-chip sampling provides excellent dynamic performance for input signals to 50kHz, and has a full-power –3dB bandwidth of 4MHz. Full control over sample-to-hold timing is available for applications where this is critical. 6 VREF+ CLK 23 7 VREF– BUSY 22 8 DGND HBE 21 BUSY High Byte Enable Command Convert Command 9 VD WR 20 BUSY Data Bit 7 10 D7 CS 19 LOW Data Bit 6 11 D6 RD 18 LOW Data Bit 5 12 D5 D0 17 LOW Data Bit 4 13 D4 D1 16 Data Bit 0 Data Bit 8 (LSB) Data Bit 1 Data Bit 9 Data Bit 11 Data Bit 3 (MSB) 14 D3 D2 15 Data Bit 2 Data Bit 10 HBE Input HBE Input HIGH LOW Read Command HBE Input HBE Input LOW HIGH FIGURE 1. Basic Operation. Finally, this performance is matched with the low-power advantages of CMOS structures to allow a typical power consumption of 10mW, with a 50µW power down option. ® 5 ADS7803 STARTING A CONVERSION A conversion is initiated on the rising edge of the WR input, with valid signals on A0, A1 and CS. The selected input channel is sampled for five clock cycles. The successive approximation conversion takes place during clock cycles 6 through 17. CALIBRATION A calibration cycle is initiated automatically upon power-up (or after a power failure). Calibration can also be initiated by the user at any time by the rising edge of a minimum 100nswide LOW pulse on the CAL pin (pin 26), or by setting D1 HIGH in the Special Function Register (see SFR section). A calibration command will initiate a calibration cycle, regardless of whether a conversion is in process. During a calibration cycle, convert commands are ignored. Figures 2 and 3 show the full conversion sequence and the timing to initiate a conversion. A conversion can also be initiated by a rising edge on pin 26, if a HIGH has been written to D2 of the Special Function Register, as discussed below. Calibration takes 168 clock cycles, and a normal conversion (17 clock cycles) is added automatically. Thus, at the end of a calibration cycle, there is valid conversion data in the output registers. For maximum accuracy, the supplies and reference need to be stable during the calibration procedure. To ensure that supply voltages have settled and are stable, an internal timer provides a waiting period of 42,425 clock cycles between power-up/power-failure and the start of the calibration cycle. PIN ASSIGNMENTS PIN # NAME 1 SFR DESCRIPTION 2 to 5 AIN0 to AIN3 6 VREF+ Positive voltage reference input. Normally +5V. Must be ≤VA. 7 VREF– Negative voltage reference input. Normally 0V. 8 DGND 9 VD 10 to 17 D0 to D7 10 D7 11 12 13 14 15 16 17 D6 D5 D4 D3 D2 D1 D0 Data Bus Input/Output Pins. Normally used to read output data. See section on SFR (Special Function Register) for other uses. When SFR is LOW, these function as follows: Data Bit 7 if HBE is LOW; if HBE is HIGH, acts as converter status pin and is HIGH during conversion or calibration, goes LOW after the conversion is completed. (Acts as an inverted BUSY). Data Bit 6 if HBE is LOW; LOW if HBE is HIGH. Data Bit 5 if HBE is LOW; LOW if HBE is HIGH. Data Bit 4 if HBE is LOW; LOW if HBE is HIGH. Data Bit 3 if HBE is LOW; Data Bit 11 (MSB) if HBE is HIGH. Data Bit 2 if HBE is LOW; Data Bit 10 if HBE is HIGH. Data Bit 1 if HBE is LOW; Data Bit 9 if HBE is HIGH. Data Bit 0 (LSB) if HBE is LOW; Data Bit 8 if HBE is HIGH. 18 RD Read Input. Active LOW; used to read the data outputs in combination with CS and HBE. 19 CS Chip Select Input. Active LOW. 20 WR Write Input. Active LOW; used to start a new conversion and to select an analog channel via address inputs A0 and A1 in combination with CS. The minimum WR pulse LOW width is 100ns. Special Function Register. When connected to a microprocessor address pin, allows access to special functions through D0 to D7. See the sections discussing the Special Function Register. If not used, connect to DGND. This pin has an internal pull-down. Analog inputs. Channel 0 to channel 3. Digital ground. DGND = 0V. Logic supply voltage. VD = +5V. Must be ≤VA and applied after VA. 21 HBE 22 BUSY High Byte Enable. Used to select high or low data output byte in combination with CS and RD, or to select SFR. 23 CLK Clock Input. For internal or external clock operation. For external clock operation, connect pin 23 to a 74HC-compatible clock source. For internal clock operation, connect pin 23 per the clock operation description. 24 to 25 A0 to A1 Address Inputs. Used to select one of four analog input channels in combination with CS and WR. The address inputs are latched on the rising edge of WR or CS. BUSY is LOW during conversion or calibration. BUSY goes HIGH after the conversion is completed. A1 LOW LOW HIGH HIGH 26 CAL (SHC) 27 AGND 28 VA A0 Selected Channel LOW HIGH LOW HIGH AIN0 AIN1 AIN2 AIN3 Calibration Input. A calibration cycle is initiated when CAL is LOW. The minimum pulse width of CAL is 100ns. If not used, connect to VD. In this case calibration is only initiated at power on, or with SFR. If D2 of the SFR is programmed HIGH, pin 26 will be used as an input to control the sample-to-hold timing. A rising edge on pin 26 will switch from sample-mode to hold-mode and initiate a conversion. This pin has an internal pull-up. Analog Ground. AGND = 0V. Analog Supply. VA = +5V. Must be ≥VD and VREF+. ® ADS7803 6 the most right bit in the 16-bit word). Two read operations are required to transfer the High byte and Low byte, and the bytes are presented according to the input level on the High Byte Enable pin (HBE). READING DATA Data from the ADS7803 is read in two 8-bit bytes, with the Low byte containing the 8 LSBs of data, and the High byte containing the 4 MSBs of data. The outputs are coded in straight binary (with 0V = 000 hex, 5V = FFF hex), and the data is presented in a right-justified format (with the LSB as 1 2 3 4 The bytes can be read in either order, depending on the status of the HBE input. If HBE changes while CS and RD are 5 6 7 16 17 18 CLK WR Multiplexer Settling, Offset Auto Zeroing and Sampling Acquisition Successive Approximation Conversion BUSY FIGURE 2. Converter Timing. CS t1 t2 t3 WR or CAL t4 BUSY t5 t6 SFR VIH VIL A0, A1 FIGURE 3. Write Cycle Timing (for initiating conversion or calibration). BUSY t7 CS t8 t9 t10 t8 t10 t12 t11 t12 RD SFR t11 HBE t13 D0 - D7 Hi-Z State t14 t13 Hi-Z Low Byte Data t14 High Byte Data FIGURE 4. Read Cycle Timing. ® 7 ADS7803 TIMING CONSIDERATIONS Table I and Figures 3 through 9 show the digital timing of ADS7803 under the various operating modes. All of the critical parameters are guaranteed over the full –40°C to +85°C operating range for ease of system design. LOW, the output data will change to correspond to the HBE input. Figure 4 shows the timing for reading first the Low byte and then the High byte. ADS7803 provides two modes for reading the conversion results. At power-up, the converter is set in the Transparent Mode. SPECIAL FUNCTION REGISTER (SFR) An internal register is available, either to determine additional data concerning the ADS7803, or to write additional instructions to the converter. TRANSPARENT MODE This is the default mode for ADS7803. In this mode, the conversion decisions from the successive approximation register are latched into the output register as they are made. Thus, the High byte (the 4 MSBs) can be read after the end of the ninth clock cycle (five clock cycles for the mux settling, sample acquisition and auto-zeroing of the comparator, followed by the four clock cycles for the 4MSB decisions.) The complete 12-bit data is available after BUSY has gone HIGH, or the internal status flag goes LOW (D7 when HBE is HIGH). Table II shows the data in the Special Function Register that will be transferred to the output bus by driving HBE HIGH (with SFR HIGH) and initiating a read cycle (driving RD and CS LOW with WR HIGH.) The Power Fail flag in the SFR is set when the power supply falls below about 3V. The flag also means that a new calibration has been started, and any data written to the SFR has been lost. Thus, the ADS7803 will again be in the Transparent Mode. Writing a LOW to D5 in the SFR resets the Power Fail flag. The Cal Error flag in the SFR is set when an overflow occurs during calibration, which may happen in very noisy systems. It is reset by starting a calibration, and remains low after a calibration without an overflow is completed. LATCHED OUTPUT MODE This mode is activated by writing a HIGH to D0 in the Special Function Register with CS and WR LOW and SFR and HBE HIGH. (See the discussion of the Special Function Register below.) Table III shows how instructions can be transferred to the Special Function Register by driving HBE HIGH (with SFR HIGH) and initiating a write cycle (driving WR and CS LOW with RD HIGH.) Note that writing to the SFR also initiates a new conversion. In this mode, the data from a conversion is latched into the output buffers only after a conversion is complete, and remains there until the next conversion is completed. The conversion result is valid during the next conversion. This allows the data to be read even after a new conversion is started, for faster system throughput. PARAMETER(1) SYMBOL MIN TYP MAX UNITS t1 CS to WR Setup Time(2) 0 0 0 ns t2 WR or CAL Pulse Width 100 t3 CS to WR Hold Time(2) 0 0 0 ns t4 WR to BUSY Propagation Delay 20 50 150 t5 A0, A1, HBE, SFR Valid to WR Setup Time 0 ns t6 A0, A1, HBE, SFR Valid to WR Hold Time 20 ns t7 BUSY to CS Setup Time 0 t8 CS to RD Setup Time(2) 0 t9 RD Pulse Width t10 CS to RD Hold Time(2) 0 ns ns ns 0 0 ns 0 0 ns 100 ns t11 HBE, SFR to RD Setup Time 50 t12 HBE, SFR to RD Hold Time 0 ns t13 RD to Valid Data (Bus Access Time)(3) 80 150 ns t14 RD to Hi-Z Delay (Bus Release Time)(3) 90 180 ns t15 RD to Hi-Z Delay For SFR(3) 20 t16 Data Valid to WR Setup Time 100 ns t17 Data Valid to WR Hold Time 20 ns t18 Acquisition Time. Pin 26 LOW with D2 in SFR HIGH 2.5 t19 Sample-to-Hold Aperture Delay. (D2 in SFR HIGH) t20 Delay from rising edge on pin 26 to start of conversion. (D2 in SFR HIGH) ns 60 ns µs 5 ns 1.5 CLK cycles NOTES: (1) All input control signals are specified with tRISE = tFALL = 20ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. Data is timed from VIH, VIL, VOH or VOL. (2) The internal RD pulse is performed by a NOR wiring of CS and RD. The internal WR pulse is performed by a NOR wiring of CS and WR. (3) Figures 8 and 9 show the measurement circuits and pulse diagrams for testing transitions to and from Hi-Z states. TABLE I. Timing Specifications (CLK = 2MHz external, TA = –40°C to +85°C). ® ADS7803 8 PIN FUNCTION DESCRIPTION D0 Mode Status If LOW, Transparent Mode enabled for data latches. If HIGH, latched Output Mode enabled. D1 CAL Flag D2 Pin 26 Status D3 Power Down Status D4 D5 CS t1 If HIGH, calibration cycle in progress. If LOW, pin 26 used as input to initiate calibration cycle. If HIGH, pin 26 used as input to control sample-to-hold timing. t3 t5 t6 HBE If HIGH, in Power Down Mode. SFR Reserved for factory use. POWER FAIL Flag t2 WR VIH If HIGH, a power supply failure has occurred. (Supply fell below 3V.) D6 CAL ERROR Flag If HIGH, an overflow occurred during calibration. D7 BUSY Flag If HIGH, conversion or calibration in progress. D0 - D7 Valid Data VIL t16 t17 FIGURE 5. Writing to the SFR. NOTE: These data are transferred to the bus when a read cycle is initiated with SFR and HBE HIGH. Reading the SFR with SFR HIGH and HBE LOW is reserved for factory use at this time, and will yield unpredictable data. TABLE II. Reading the Special Function Register. CS t10 t11 t12 t11 t12 RD POWER DOWN MODE Writing a HIGH to D3 in the SFR puts the ADS7803 in the Power Down Mode. Power consumption is reduced to 50µW and D3 remains HIGH. The internal clock and analog circuitry are turned off, although the output registers and SFR can still be accessed normally. To exit Power Down Mode, either write a LOW to D3 in the SFR, or initiate a calibration by sending a LOW to the CAL pin or writing a HIGH to D1. Note that if the power supply falls below 3V and then recovers, a calibration is automatically initiated, and the SFR will be reset. D3 will be LOW, and the ADS7803 will not be in the Power Down Mode. HBE SFR VIH t13 t14 SFR Data D0 - D7 FIGURE 6. Reading the FSR. SAMPLE/HOLD CONTROL MODE With D2 in the SFR HIGH, a rising edge input on pin 26 will switch the ADS7803 from sample-mode to hold-mode with a 5ns aperture delay. This also initiates a conversion, which will start within 1.5 CLK cycles. During Power Down Mode, a pulse on CS and WR will initiate a single conversion, then the ADS7803 will revert to power down. Also, writing to D1 and D3 in the SFR will initiate a calibration, do a single conversion and revert to the Power Down Mode, in 185 clock cycles. Accurate conversion results will be available in the output registers. This mode allows full control over the sample-to-hold timing, which is especially useful where external events trigger sampling timing. The activation delay from power down to normal operation is included in the sampling time. No extra time is required, either when coming out of the Power Down Mode or when making a single conversion in the Power Down Mode. OPERATION t8 In the Sample/Hold Control Mode, pin 26 must be held LOW a minimum of 2.5µs between conversions to allow accurate acquisition of input signals. Also, offset error will increase in this mode, since auto-zeroing of the comparator is not synchronized to the sampling. Minimum offset is achieved by synchronizing the sampling signal to CLK, whether internal or external. Ideally, the sampling signal CS/WR SFR/HBE D0 D1 D2 D3 D5 Enables Transparent Mode for Data Latches LOW HIGH LOW X X X X D4/D6/D7 LOW Enables Latched Output Mode for Data Latches LOW HIGH HIGH(1) X X X X LOW Initiates Calibration Cycle LOW HIGH X HIGH X X X LOW Activates Sample/Hold Control Mode LOW HIGH X X HIGH(1) X X LOW Activates Power Down Mode(2) LOW HIGH X X X HIGH(1) X LOW Resets Power Fail Flag LOW HIGH X X X X LOW LOW NOTES: (1) Writing a LOW here reactivates the standard mode of operation. (2) In Power Down Mode, a pulse on CS and WR will initiate a single conversion, then the ADS7803 will revert to power down. (3) X means it can be either HIGH or LOW without affecting this action. Writing HIGH to D4 or D6, or writing with SFR HIGH and HBE LOW, may result in unpredictable behavior. These modes are reserved for factory use at this time. TABLE III. Writing to the Special Function Register. ® 9 ADS7803 rising edge should be delayed 20ns from the falling edge of CLK. This will keep offset error to about 1LSB. noise at the analog input, since it could be injected into the capacitor array. In the Sample/Hold Control Mode, a LOW pulse on WR (with CS LOW) will not initiate a conversion, but the rising edge will latch the multiplexer channel according to the inputs on A0 and A1. When changing channels, this must be done at least 2.5µs before pin 26 goes HIGH (to start a conversion.) In many applications, a simple passive low-pass filter as shown in Figure 10a can be used to improve signal quality. In this case, the source impedance needs to be less than 5kΩ to keep the induced offset errors below 1/2LSB, and to meet the acquisition time of five clock cycles. The values in Figure 10a meet these requirements, and will maintain the full power bandwidth of the system. For higher source impedances, a buffer like the one in Figure 10b should be used. CONTROL LINES Table IV shows the functions of the various control lines on the ADS7803. The use of standard CS, RD and WR control signals simplifies use with most microprocessors. At the same time, flexibility is assured by availability of status information and control functions, both through the SFR and directly on pins. INPUT PROTECTION The input signal range must not exceed ±VREF or VA by more than 0.3V. The analog inputs are internally clamped to VA. To prevent damage to the ADS7803, the current that can flow into the inputs must be limited to 20mA. One approach is to use an external resistor in series with the input filter resistor. For example, a 1kΩ input resistor allows an overvoltage to 20V without damage. INSTALLATION INPUT IMPEDANCE ADS7803 has a very high input impedance (input bias current over temperature is 100nA max), and a low 50pF input capacitance. To ensure a conversion accurate to 12 bits, the analog source must be able to charge the 50pF and settle within the first five clock cycles after a conversion is initiated. During this time, the input is also very sensitive to REFERENCE INPUTS A 10µF tantalum capacitor is recommended between VREF+ and VREF– to insure low source impedance. These capacitors should be located as close as possible to the ADS7803 CS RD WR SFR HBE CAL BUSY X X X X X 0↑1 X OPERATION Initiates calibration cycle. (See SFR section for alternate use as Sample/ Hold Control Mode input.) X X X X X X 0 Conversion or calibration in process. Inhibits new conversion from starting. 1 X X X X 1 X None. Outputs in Hi-Z State. 0 1 0↑1 0 X 1 1 Initiates conversion. 0 0 1 0 0 1 X Low byte conversion results output on data bus. 0 0 1 0 1 1 X High byte conversion results output on data bus. 0 1 0 1 1 1 1 Write to SFR and rising edge on WR initiates conversion. 0 0 1 1 1 1 X Contents of SFR output on data bus. 0 1 0 1 0 1 X Reserved for factory use. 0 0 1 1 0 1 X Reserved for factory use. (Unpredictable data on data bus.) TABLE IV. Control Line Functions. 1 2 11 12 CLK t18 SHC (Pin 26) t20 BUSY t19 Sample Hold Convert FIGURE 7. Timing for Initiating Conversion in Sample/Hold Control Mode (D2 in SFR HIGH). ® ADS7803 10 Sample 5V ADS7803 Output 3kΩ ADS7803 Output Test Point 3kΩ Test Point CL CL (a) Load Circuit (a) Load Circuit Output Enable VD tFALL tFALL Output Enable 90% 50% 10% Gnd VD 90% VOH 10% VOL Gnd t15 t14 t15 t14 (b) From HIGH to Hi-Z, CL = 10pF (b) From LOW to Hi-Z, CL = 10pF tRISE VD Gnd 10% Gnd VD Output Enable 90% 50% Output Enable 90% 50% 10% tRISE VD 90% 50% 10% Gnd t13 t13 VOH VD 2.4V 0.8V Gnd VOL (c) From Hi-Z to HIGH, CL = 100pF (c) From Hi-Z to LOW, CL = 100pF FIGURE 8. Measuring Active LOW to/from Hi-Z State. FIGURE 9. Measuring Active HIGH to/from Hi-Z State. to reduce dynamic errors, since the reference provides packets of current as the successive approximation steps are carried out. power supply rejection, even for higher frequencies, linear regulated power supplies are recommended. Care should be taken to insure that VD does not come up before VA, or permanent damage to the part may occur. VREF+ must not exceed VA. Although the accuracy is specified with VREF+ = 5V and VREF– = 0V, the converter can function with VREF+ as low as 4.5V and VREF– as high as 1V. As long as there is at least a 4.5V difference between VREF+ and VREF–, the absolute value of errors does not change significantly, so that accuracy will typically be within ±1LSB 50Ω Analog Input To ADS7803 5nF VREF– (Normally 0V) The power supply to the reference source needs to be considered during system design to prevent VREF+ from exceeding (or overshooting) VA, particularly at power-on. Also, after power-on, if the reference is not stable within 42,425 clock cycles, an additional calibration cycle may be needed. (a) Passive Low Pass Filter Analog Input OPA627 R To ADS7803 C POWER SUPPLIES The digital and analog power supply lines to the ADS7803 should be bypassed with 10µF tantalum capacitors as close to the part as possible. Although ADS7803 has excellent VREF– (Normally 0V) (b) Active Low Pass Filter FIGURE 10. Input Signal Conditioning. ® 11 ADS7803 HIGH, with rise and fall times that do not exceed 200ns. The duty cycle of the external clock can vary as long as the LOW time and HIGH time are each at least 200ns wide. Synchronizing the conversion clock to an external system clock is recommended in microprocessor applications to prevent beat-frequency problems. +5V 5V REF 10µF + 10nF 10µF 10nF + 1 SFR VA 28 2 AIN0 AGND 27 3 AIN1 CAL 26 4 AIN2 A1 25 5 AIN3 A0 24 6 VREF+ CLK 23 7 VREF– BUSY 22 8 DGND HBE 21 9 VD WR 20 10 D7 CS 19 11 D6 RD 18 12 D5 D0 17 13 D4 D1 16 14 D3 D2 15 10nF + 10µF Note that the electrical specification tables are based on using an external 2MHz clock. Typically, the specified accuracy is maintained for clock frequencies between 0.5 and 2.4MHz. INTERNAL CLOCK OPERATION Figure 12b shows how to use the internal clock generating circuitry. The clock frequency depends only on the value of the resistor, as shown in “Internal Clock Frequency vs RCLOCK” in the Typical Performance Curves section. The clock generator can operate between 100kHz and 2MHz. With R = 100kΩ, the clock frequency will nominally be 800kHz. The internal clock oscillators may vary by up to 20% from device to device, and will vary with temperature, as shown in the typical performance curves. Therefore, use of an external clock source is preferred in applications where control of the conversion timing is critical, or where multiple converters need to be synchronized. 10Ω FIGURE 11. Power Supply and Reference Decoupling. Figure 11 shows a good supply approach, powering both VA and VD from a clean linear supply, with the 10Ω resistor between VA and VD insuring that VD comes up after VA. This is also a good method to further isolate the ADS7803 from digital supplies in a system with significant switching currents that could degrade the accuracy of conversions. APPLICATIONS BIPOLAR INPUT RANGES Figure 13 shows a circuit to accurately and simply convert a bipolar ±5V input signal into a unipolar 0 to 5V signal for conversion by the ADS7803, using a precision, low-cost complete difference amplifier, INA105. GROUNDING To maximize accuracy of the ADS7803, the analog and digital grounds are not connected internally. These points should have very low impedance to avoid digital noise feeding back into the analog ground. The VREF– pin is used as the reference point for input signals, so it should be connected directly to AGND to reduce potential noise problems. INA105 25kΩ ±5V Input EXTERNAL CLOCK OPERATION The circuitry required to drive the ADS7803 clock from an external source is shown in Figure 12a. The external clock must provide a 0.8V max for LOW and a 3.5V min for 74HC-Compatible Clock Source CLK 1 +5V 0 to 5V to ADS7803 25kΩ +5V (VREF+) FIGURE 13. ±5V Input Range. ±5V (VREF+) R1 10kΩ See Typical Performance Curves for R Values vs Frequency ±10V Input (b) Internal Clock Operation R2 5kΩ OPA627 R3 10kΩ FIGURE 14. ±10V Input Range. FIGURE 12. Internal Clock Operation. ® ADS7803 5 3 To ADS7803 Pin 23 To ADS7803 Pin 23 2 6 25kΩ (a) External Clock Operation R 25kΩ 12 0 to 5V to ADS7803 Figure 14 shows a circuit to convert a bipolar ±10V input signal into a unipolar 0 to 5V signal for conversion by the ADS7803. The precision of this circuit will depend on the matching and tracking of the three resistors used. A1 - A23 (A0 - A19) Address Decoder Logic AS ADC_CS HBE SFR BUSY DACK CS R/W RD WR ADS7803 DO 0 - DO 7 DO 0 D0 - D7 DO 1 A1 A0 FIGURE 15. Interface to Motorola Microprocessors. MOVEP.W $000 (ADC-ADDRESS), D0 This circuit can also be used to adjust gain and offset errors due to the components preceding the ADS7803, to match the performance of the self-calibration provided by the converter. This puts the 12-bit conversion result in the D0 register, as shown in Figure 15. The address decoder must pull down ADC_CS AT ADC-ADDRESS to access the Low byte and ADC-ADDRESS +2 to access the High byte. INTERFACING TO MOTOROLA MICROPROCESSORS Figure 15 show a typical interface to Motorola microprocessors, while Figure 16 shows how the result can be placed in register D0. INTERFACING TO INTEL MICROPROCESSORS Figure 17 shows a typical interface to Intel. A conversion is initiated by write instruction to address ADC_CS. Data pins DO0 and DO1 select the analog input channel. The BUSY signal can be used to generate a microprocessor interrupt (INT) when the conversion is completed. Conversion is initiated by a write instruction decoded by the address decoder logic, with the lower two bits of the address bus selecting an ADC input channel, as follows: A read instruction from the ADC_CS address fetches the Low byte, and a read instruction from the ADC_CS address +2 fetches the High byte. MOVE.W D0, ADC-ADDRESS The result of the conversion is read from the data bus by a read instruction to ADC-ADDRESS as follows: 24 23 A1 INT MC68000 (MC68008) To trim this circuit for full 12-bit precision, R2 and R3 need to be adjustable over appropriate ranges. To trim, first have the ADS7803 converting continually and apply +9.9927V (+10V – 1.5LSB) at the input. Adjust R3 until the ADS7803 output toggles between the codes FFE hex and FFF hex. This makes R3 extremely close to R1. Then, apply –9.9976V (–10V + 0.5LSB) at the input, and adjust R2 until the ADS7803 output toggles between 000 hex and 001 hex. At each trim point, the current through the third resistor will be almost zero, so that one trim iteration will be enough in most cases. More iterations may be required if the op amp selected has large offset voltage or bias currents, or if the +5V reference is not precise. 31 Address Bus 16 15 B U S Y 0 0 0 M S B 8 7 D D D B B B 11 10 9 D B 8 D B 7 L S B 0 D B 6 D B 5 D B 4 D B 3 D B 2 D B 0 D B 1 FIGURE 16. Conversion Results in Motorola Register D0. Intel Microprocessor Based Systems (IO/M) 8085 8086/88 80186/188 80286 8031 8051 Address Bus A1 A2 INT Address Decoder Logic ADC_CS HBE SFR BUSY CS R/D RD WR WR ADS7803 Data Bus DO 0 DO 1 D0 - D7 A1 A0 FIGURE 17. Interface to Intel Microprocessors. ® 13 ADS7803