ADS7808 ® ADS 7808 7808 ADS 12-Bit 10µs Serial CMOS Sampling ANALOG-to-DIGITAL CONVERTER FEATURES DESCRIPTION ● 100kHz SAMPLING RATE The ADS7808 is a complete 12-bit sampling analogto-digital using state-of-the-art CMOS structures. It contains a 12-bit capacitor-based SAR A/D with S/H, reference, clock, and a serial data interface. Data can be output using the internal clock, or can be synchronized to an external data clock. The ADS7808 also provides an output synchronization pulse for ease of use with standard DSP processors. The ADS7808 is specified at a 100kHz sampling rate, and guaranteed over the full temperature range. Lasertrimmed scaling resistors provide various input ranges including ±10V and 0V to 5V, while an innovative design operates from a single +5V supply, with power dissipation under 100mW. The 20-pin ADS7808 is available in a plastic 0.3" DIP and in an SOIC, both fully specified for operation over the industrial –40°C to +85°C range. ● ● ● ● ● ● 72dB SINAD WITH 45kHz INPUT ±1/2 LSB INL AND DNL SIX SPECIFIED INPUT RANGES SERIAL OUTPUT SINGLE +5V SUPPLY OPERATION PIN-COMPATIBLE WITH 16-BIT ADS7809 ● USES INTERNAL OR EXTERNAL REFERENCE ● 100mW MAX POWER DISSIPATION ● 20-PIN 0.3" PLASTIC DIP AND SOIC ● SIMPLE DSP INTERFACE CS R/C Power Down Successive Approximation Register and Control Logic Clock 20kΩ CDAC R1IN 10kΩ BUSY R2IN Serial 20kΩ 5kΩ Data Comparator R3IN Data Clock Out Serial Data CAP Buffer Internal +2.5V Ref 4kΩ REF International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1992 Burr-Brown Corporation PDS-1155B 1 Printed in U.S.A. January 1997 ADS7808 SPECIFICATIONS ELECTRICAL At TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors as shown in Figure 4, unless otherwise specified. ADS7808P, U PARAMETER CONDITIONS MIN TYP RESOLUTION ADS7808PB, UB MAX MIN TYP 12 ANALOG INPUT Voltage Ranges Impedance Capacitance MAX UNITS ✻ Bits ±10V, 0V to 5V, etc. (See Table I) See Table I 35 ✻ THROUGHPUT SPEED Conversion Time Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes Transition Noise(2) Full Scale Error(3,4) Full Scale Error Drift Full Scale Error(3,4) Full Scale Error Drift Bipolar Zero Error(3) Bipolar Zero Error Drift Unipolar Zero Error(3) Unipolar Zero Error Drift Recovery to Rated Accuracy after Power Down Power Supply Sensitivity (VDIG = VANA = VD) AC ACCURACY Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) Signal-to-Noise Full-Power Bandwidth(6) SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response Overvoltage Recovery(7) REFERENCE Internal Reference Voltage Internal Reference Source Current (Must use external buffer) External Reference Voltage Range for Specified Linearity External Reference Current Drain DIGITAL INPUTS Logic Levels VIL VIH IIL IIH 5.7 Acquire and Convert ✻ 8 10 ±0.9 ±0.9 ±7 ±2 ±2 ±2 1 FS Step No Load ±0.5 ±5 ±0.5 80 70 70 ±0.45 ±0.45 LSB(1) LSB 90 –90 73 73 250 ±0.25 ±0.25 ✻ ±10 ✻ ±2 ±5 ±3 ±3 ✻ ✻ ✻ ✻ ✻ ±0.5 +4.75V < VD < +5.25V 45kHz 45kHz 45kHz 45kHz µs µs kHz ✻ ✻ Guaranteed 0.1 fIN = fIN = fIN = fIN = ✻ ✻ ✻ 100 Ext. 2.5000V Ref Ext. 2.5000V Ref Bipolar Ranges Bipolar Ranges 0V to 10V Range 0V to 4V Range 0V to 5V Range Unipolar Ranges 1µF Capacitor to CAP pF ✻ ✻ –80 72 72 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ 40 Sufficient to meet AC specs 2 150 ✻ ✻ LSB % ppm/°C % ppm/°C mV ppm/°C mV mV mV ppm/°C ms LSB dB(5) dB dB dB kHz ns ns µs ns 2.48 2.5 1 2.52 ✻ ✻ ✻ ✻ V µA 2.3 2.5 2.7 ✻ ✻ ✻ V ✻ µA ✻ ✻ ✻ ✻ V V µA µA Ext. 2.5000V Ref 100 –0.3 +2.0 VIL = 0V VIH = 5V +0.8 VD +0.3V ±10 ±10 ✻ ✻ The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADS7808 2 SPECIFICATIONS (CONT) ELECTRICAL At TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 4, unless otherwise specified. ADS7808P/U PARAMETER CONDITIONS DIGITAL OUTPUTS Data Format Data Coding Pipeline Delay Data Clock Internal (Output Only When Transmitting Data) External (Can Run Continually) VOL VOH Leakage Current Output Capacitance POWER SUPPLIES Specified Performance VDIG VANA IDIG IANA Power Dissipation: PWRD LOW PWRD HIGH MIN TYP ADS7808PB/UB MAX MIN TYP MAX UNITS Serial 12 bits Binary Two's Complement or Straight Binary Conversion results only available after completed conversion. Selectable for internal or external data clock 2.3 ✻ EXT/INT LOW EXT/INT HIGH 0.1 ISINK = 1.6mA ISOURCE = 500µA High-Z State, VOUT = 0V to VDIG High-Z State ✻ 10 +0.4 +4.75 +5 0.3 16 +5 +5.25 MHz ✻ ±5 ✻ V V µA 15 15 pF * V mA mA * V ✻ * * * +5.25 ✻ VDIG = VANA = 5V, fS = 100kHz * * 100 50 TEMPERATURE RANGE Specified Performance Derated Performance Storage Thermal Resistance (θJA) Plastic DIP SOIC ✻ ✻ +4 Must be ≤ VANA +4.75 MHz mW µW * –40 –55 –65 +85 +125 +150 * * * °C °C °C * * * 75 75 °C/W °CW * * NOTES: (1) LSB means Least Significant Bit. For the ±10V input range, one LSB is 4.88mV. (2) Typical rms noise at worst case transitions and temperatures. (3) As measured with fixed resistors in Figure 4. Adjustable to zero with external potentiometer. (4) For bipolar input ranges, full scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. For unipolar input ranges, full scale error is the deviation of the last code transition divided by the transition voltage. It also includes the effect of offset error. (5) All specifications in dB are referred to a full-scale ±10V input. (6) Full-Power Bandwidth defined as Full-Scale input frequency at which Signalto (Noise + Distortion) degrades to 60dB. (7) Recovers to specified performance after 2 x FS input overvoltage. ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Analog Inputs: R1IN .......................................................................... ±25V R2IN .......................................................................... ±25V R3IN .......................................................................... ±25V CAP ..................................... VANA+0.3V to AGND2 –0.3V REF ....................................... Indefinite Short to AGND2, Momentary Short to VANA Ground Voltage Differences: DGND, AGND2 ................................. ±0.3V VANA ...................................................................................................... 7V VDIG to VANA ....................................................................................... +0.3 VDIG ....................................................................................................... 7V Digital Inputs ............................................................. –0.3V to VDIG +0.3V Maximum Junction Temperature .................................................. +165°C Internal Power Dissipation ............................................................ 700mW Lead Temperature (soldering, 10s) .............................................. +300°C Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that this integrated circuit be handled and stored using appropriate ESD protection methods. PACKAGE INFORMATION ADS7808P ADS7808PB ADS7808U ADS7808UB ADS7808P ADS7808PB ADS7808U ADS7808UB PACKAGE DRAWING NUMBER(1) 20-Pin Plastic DIP 20-Pin Plastic DIP 20-Pin SOIC 20-Pin SOIC 222 222 221 221 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ORDERING INFORMATION PRODUCT PACKAGE PRODUCT MAXIMUM LINEARITY ERROR (LSB) MINIMUM SIGNAL-TO(NOISE + DISTORTION) RATIO(dB) ±0.9 ±0.45 ±0.9 ±0.45 70 72 70 72 SPECIFICATION TEMPERATURE RANGE (°C) –40°C –40°C –40°C –40°C to to to to +85°C +85°C +85°C +85°C PACKAGE 20-Pin Plastic DIP 20-Pin Plastic DIP 20-Pin SOIC 20-Pin SOIC ® 3 ADS7808 PIN ASSIGNMENTS PIN # NAME 1 R1IN 2 AGND1 3 R2IN DESCRIPTION Analog Input. See Table I and Figure 4 for input range connections. Analog Ground. Used internally as ground reference point. Minimal current flow. Analog Input. See Table I and Figure 4 for input range connections. 4 R3IN Analog Input. See Table I and Figure 4 for input range connections. 5 CAP Reference Buffer Capacitor. 2.2µF Tantalum to ground. 6 REF Reference Input/Output. Outputs internal 2.5V reference. Can also be driven by external system reference. In both cases, bypass to ground with a 2.2µF Tantalum capacitor. 7 AGND2 Analog Ground. 8 SB/BTC Select Straight Binary or Binary Two’s Complement data output format. If HIGH, data will be output in a Straight Binary format. If LOW, data will be output in a Binary Two’s complement format. 9 EXT/INT Select External or Internal Clock for transmitting data. If HIGH, data will be output synchronized to the clock input on DATACLK. If LOW, a convert command will initiate the transmission of the data from the previous conversion, along with 12 clock pulses output on DATACLK. 10 DGND Digital Ground. 11 SYNC Synch Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a falling edge on CS with R/C HIGH will output a pulse on SYNC synchronized to the external DATACLK. 12 DATACLK 13 DATA Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the level of SB/BTC. In the external clock mode, after 12-bits of data, the ADS7808 will output the level input on TAG as long as CS is LOW and R/C is HIGH (see Figure 3.) If EXT/INT is LOW, data will be valid on both the rising and falling edges of DATACLK, and between conversions DATA will stay at the level of the TAG input when the conversion was started. 14 TAG Tag Input for use in external clock mode. If EXT/INT is HIGH, digital data input on TAG will be output on DATA with a delay of 12 DATACLK pulses as long as CS is LOW and R/C is HIGH. See Figure 3. 15 R/C Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion. When EXT/INT is LOW, this also initiates the transmission of the data results from the previous conversion. If EXT/INT is HIGH, a rising edge on R/C with CS LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the transmission of data from the previous conversion. Either an input or an output depending on the EXT/INT level. Output data will be synchronized to this clock. If EXT/INT is LOW, DATACLK will transmit 12 pulses after each conversion, and then remain LOW between conversions. 16 CS 17 BUSY Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the output shift register. CS or R/C must be HIGH when BUSY rises, or another conversion will start without time for signal acquisition. Chip Select. Internally OR’ed with R/C. 18 PWRD Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the previous conversion are maintained in the output shift register. 19 VANA Analog Supply Input. Nominally +5V. Connect directly to pin 20, and decouple to ground with 0.1µF ceramic and 10µF Tantalum capacitors. 20 VDIG Digital Supply Input. Nominally +5V. Connect directly to pin 19. Must be ≤ VANA. PIN CONFIGURATION R1IN 1 20 VDIG AGND1 2 19 VANA R2IN 3 18 PWRD R3IN 4 17 BUSY CAP 5 REF 6 15 R/C AGND2 7 14 TAG SB/BTC 8 13 DATA EXT/INT 9 12 DATACLK ADS7808 DGND 10 16 CS CONNECT R1IN VIA 200Ω TO ±10V ±5V ±3.33 0V to 10V 0V to 5V 0V to 4V VIN AGND VIN AGND AGND VIN CONNECT R2IN VIA 100Ω CONNECT R3IN TO TO AGND VIN VIN VIN AGND AGND CAP CAP CAP AGND VIN VIN IMPEDANCE 22.9kΩ 13.3kΩ 10.7kΩ 13.3kΩ 10.0kΩ 10.7kΩ TABLE I. Input Range Connections. See Figure 4 for complete information. 11 SYNC ® ADS7808 ANALOG INPUT RANGE 4 SYMBOL DESCRIPTION MIN t1 Convert Pulse Width 40 t1 TYP MAX UNITS 4500 ns t2 BUSY Delay 65 ns t3 BUSY LOW 8 µs t4 BUSY Delay after End of Conversion 220 ns t5 Aperture Delay 40 ns t6 Conversion Time 5.7 8 2 µs 10 µs CS, R/C t3 BUSY t2 t4 t5 MODE Acquire Convert Acquire t6 t7 µs t7 Acquisition Time t6 + t7 Throughput Time 9 t8 R/C LOW to DATACLK Delay 450 t9 DATACLK Period 440 ns t10 Data Valid to DATACLK HIGH Delay 20 75 ns t11 Data Valid after DATACLK LOW Delay 100 125 ns FIGURE 1. Basic Conversion Timing. ns t12 External DATACLK Period 100 ns t13 External DATACLK HIGH 20 ns t14 External DATACLK LOW 30 t15 DATACLK HIGH Setup Time 20 t16 R/C to CS Setup Time 10 t17 SYNC Delay After DATACLK HIGH 15 35 ns t18 Data Valid Delay 25 55 ns ns t12 + 5 ns ns t19 CS to Rising Edge Delay 25 ns t20 Data Available after CS LOW 4.5 µs TABLE II. Conversion and Data Timing TA = –40°C to +85°C. t8 R/C t9 1 DATACLK 2 3 11 12 Bit 9 Valid Bit 1 Valid LSB Valid t11 t10 SDATA MSB Valid Bit 10 Valid t2 t3 BUSY FIGURE 2. Serial Data Timing Using Internal Clock. (CS, EXT/INT and TAG Tied LOW.) ® 5 ADS7808 SPECIFIC FUNCTION CS R/C Initiate Conversion and Output Data Using Internal Clock 1>0 0 BUSY EXT/INT DATACLK PWRD 1 0 Output 0 SB/BTC x OPERATION Initiates conversion “n”. Data from conversion “n–1” clocked out on DATA synchronized to 12 clock pulses output on DATACLK. 0 1>0 1 0 Output 0 x Initiates conversion “n”. Data from conversion “n–1” clocked out on DATA synchronized to 12 clock pulses output on DATACLK. 1>0 0 1 1 Input 0 x Initiates conversion “n”. 0 1>0 1 1 Input 0 x Initiates conversion “n”. 1>0 1 1 1 Input x x Outputs a pulse on SYNC followed by data from conversion “n” clocked out synchronized to external DATACLK. 1>0 1 0 1 Input 0 x Outputs a pulse on SYNC followed by data from conversion “n–1” clocked out synchronized to external DATACLK.(1) Conversion “n” in process. 0 0>1 0 1 Input 0 x Outputs a pulse on SYNC followed by data from conversion “n–1” clocked out synchronized to external DATACLK .(1) Conversion “n” in process. Incorrect Conversions 0 0 0>1 x x 0 x CS or R/C must be HIGH or a new conversion will be initiated without time for acquisition. Power Down x x x x x 0 x Analog circuitry powered. Conversion can proceed. x x x x x 1 x Analog circuitry disabled. Data from previous conversion maintained in output registers. x x x x x x 0 Serial data is output in Binary Two’s Complement format. x x x x x x 1 Serial data is output in Straight Binary format. Initiate Conversion and Output Data Using External Clock Selecting Output Format NOTE: (1) See Figure 3b for constraints on previous data valid during conversion. Table III. Control Truth Table. DIGITAL OUTPUT BINARY TWO’S COMPLEMENT (SB/BTC LOW) DESCRIPTION HEX BINARY CODE CODE 3.99902V 0111 1111 1111 7FF 1111 1111 1111 FFF 2V 0000 0000 0000 000 1000 0000 0000 800 1.99902V 1111 1111 1111 FFF 0111 1111 1111 7FF 0V 1000 0000 0000 800 0000 0000 0000 000 ANALOG INPUT Full-Scale Range Least Significant Bit (LSB) +Full Scale (FS – 1LSB) Midscale One LSB Below Midscale –Full Scale ±10 ±5 ±3.33V 0V to 5V 0V to 10V 4.88mV 2.44mV 1.63mV 1.22mV 9.99512V 4.99756V 3.33171V 0V 0V 0V –4.88mV –2.44mV –1.63mV –10V –5V –3.333333V 2.44mV 4.99878V 9.99756V 2.5V 5V 2.49878V 4.99756V 0V 0V Table IV. Output Codes and Ideal Input Voltages. ® ADS7808 6 STRAIGHT BINARY (SB/BTC HIGH) HEX BINARY CODE CODE 0V to 4V 0.98mV FIGURE 3a. Conversion and Read Timing with External Clock. (EXT/INT Tied HIGH). Read After Conversion. 7 ® ADS7808 TAG DATA SYNC BUSY R/C CS EXTERNAL DATACLK t16 t2 t1 0 t13 t16 t12 t14 t17 t15 1 t12 Tag 0 t18 2 Tag 1 Bit 11 (MSB) 3 Tag 2 Bit 10 4 Tag 11 Bit 1 13 Tag 12 Bit 0 (LSB) 14 Tag 13 Tag 0 Tag 1 Tag 14 t19 Tag 15 Tag 15 Tag 14 Tag 13 Tag 1 Tag 1 t15 t17 Tag 0 t12 t18 t20 Bit 11 (MSB) Tag 12 Bit 0 (LSB) Tag 0 t19 t1 t14 t12 TAG DATA SYNC BUSY R/C CS EXTERNAL DATACLK t16 t2 t13 FIGURE 3b. Conversion and Read Timing with External Clock. (EXT/INT Tied HIGH.) Read During Conversion (Previous Conversion Results). ® ADS7808 8 Input Range With Trim (Adjust offset first at 0V, then adjust gain) Without Trim 200Ω 200Ω R1IN R1IN AGND1 AGND1 100Ω 100Ω VIN R2IN 33.2kΩ R3IN 0V – 10V R2IN VIN 33.2kΩ R3IN +5V 2.2µF CAP + CAP 50kΩ 2.2µF 576kΩ REF 2.2µF + +5V REF 50kΩ + + 2.2µF AGND2 AGND2 200Ω 200Ω R1IN R1IN AGND1 AGND1 100Ω 100Ω R2IN 33.2kΩ 0V – 5V R3IN VIN R2IN 33.2kΩ R3IN VIN +5V CAP + CAP +5V 2.2µF 2.2µF 576kΩ + 50kΩ REF 2.2µF REF 50kΩ + 2.2µF AGND2 AGND2 200Ω 200Ω VIN VIN R1IN R1IN AGND1 AGND1 100Ω 100Ω 0V – 4V R2IN R2IN R3IN R3IN 33.2kΩ 2.2µF + +5V CAP + 33.2kΩ +5V 2.2µF + 576kΩ REF 50kΩ + 2.2µF REF 50kΩ 2.2µF CAP + AGND2 AGND2 FIGURE 4a. Offset/Gain Circuits for Unipolar Input Ranges. ® 9 ADS7808 Input Range With Trim (Adjust offset first at 0V, then adjust gain) Without Trim 200Ω 200Ω VIN VIN R1IN R1IN AGND1 AGND1 100Ω 100Ω R2IN ±10V R2IN +5V 33.2kΩ R3IN 33.2kΩ R3IN 50kΩ +5V CAP + 2.2µF 576kΩ 2.2µF REF 2.2µF CAP + REF 50kΩ + 2.2µF + AGND2 AGND2 200Ω 200Ω R1IN R1IN AGND1 AGND1 100Ω 100Ω R2IN VIN 33.2kΩ ±5V 33.2kΩ R3IN 2.2µF +5V CAP + R3IN + CAP +5V 50kΩ 2.2µF REF 2.2µF R2IN VIN 576kΩ REF 50kΩ + + 2.2µF AGND2 AGND2 200Ω 200Ω VIN VIN R1IN 100Ω R1IN AGND1 100Ω AGND1 R2IN R2IN ±3.33V R3IN 33.2kΩ R3IN 33.2kΩ 2.2µF +5V CAP + CAP +5V 50kΩ + 576kΩ REF 2.2µF + + 2.2µF AGND2 FIGURE 4b. Offset/Gain Circuits for Bipolar Input Ranges. ® ADS7808 REF 50kΩ 10 2.2µF AGND2