® ADS ADS7820 782 0 ADS 782 0 12-Bit 10µs Sampling CMOS ANALOG-to-DIGITAL CONVERTER FEATURES DESCRIPTION ● 100kHz min SAMPLING RATE ● 0 to +5V INPUT RANGE The ADS7820 is a complete 12-bit sampling A/D using state-of-the-art CMOS structures. It contains a complete 12-bit, capacitor-based SAR A/D with S/H, reference, clock, interface for microprocessor use, and three-state output drivers. ● 72dB min SINAD WITH 45kHz INPUT ● ±1/2 LSB max INL AND DNL ● SINGLE +5V SUPPLY OPERATION ● PIN-COMPATIBLE WITH 16-BIT ADS7821 The ADS7820 is specified at a 100kHz sampling rate, and guaranteed over the full temperature range. Lasertrimmed scaling resistors provide a 0 to +5V input range, with power dissipation under 100mW. The 28-pin ADS7820 is available in a plastic 0.3" DIP and in an SOIC, both fully specified for operation over the industrial –40°C to +85°C range. ● USES INTERNAL OR EXTERNAL REFERENCE ● COMPLETE WITH S/H, REF, CLOCK, ETC. ● FULL PARALLEL DATA OUTPUT ● 100mW max POWER DISSIPATION ● 28-PIN 0.3" PLASTIC DIP AND SOIC Clock Successive Approximation Register and Control Logic R/C CS BYTE BUSY CDAC 5kΩ 0 to +5V Input 6.66kΩ 20kΩ Comparator Output Latches and Three State Drivers Three State Parallel Data Bus CAP Buffer Internal +2.5V Ref 4kΩ REF International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1996 Burr-Brown Corporation 1 PDS-1322 Printed in U.S.A. June, 1996 ADS7820 SPECIFICATIONS ELECTRICAL TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference, unless otherwise specified. ADS7820P/U PARAMETER CONDITIONS MIN TYP RESOLUTION ADS7820PB/UB MAX MIN TYP 12 ANALOG INPUT Voltage Ranges Impedance Capacitance DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes Transition Noise(2) Full Scale Error(3,4) Full Scale Error Drift Full Scale Error(3,4) Full Scale Error Drift Offset Error Offset Error Drift Power Supply Sensitivity (VDIG = VANA = VD) AC ACCURACY Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) Signal-to-Noise Full-Power Bandwidth(6) SAMPLING DYNAMICS Aperture Delay Transient Response Overvoltage Recovery(7) REFERENCE Internal Reference Voltage Internal Reference Source Current (Must use external buffer.) External Reference Voltage Range for Specified Linearity External Reference Current Drain 5.7 Acquire and Convert ±7 ±2 ±2 +4.75V < VD < +5.25V 45kHz 45kHz 45kHz 45kHz ±0.5 ±5 ±0.5 ✱ ✱ µs µs kHz ±0.5 ±0.5 LSB(1) LSB Bits LSB % ppm/°C % ppm/°C mV ppm/°C LSB ±0.25 ±0.25 ✱ ±8 ±4 ✱ ±0.75 ±0.5 ✱ 80 ✱ –80 70 70 72 72 ✱ 250 ✱ 40 FS Step ✱ 2 ✱ 150 dB(5) dB dB dB kHz ns µs ns 2.48 2.5 1 2.52 ✱ ✱ ✱ ✱ V µA 2.3 2.5 2.7 ✱ ✱ ✱ V ✱ µA ✱ ✱ ✱ ✱ V V µA µA ✱ ✱ V V µA 15 ✱ pF 83 83 ✱ ✱ ns ns Ext. 2.5000V Ref 100 –0.3 +2.0 Output Capacitance V kΩ pF ✱ ✱ Guaranteed 0.1 fIN = fIN = fIN = fIN = Bits ✱ ±1.0 ±1.0 DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Data Coding VOL VOH Leakage Current ✱ 8 10 100 Ext. 2.5000V Ref Ext. 2.5000V Ref UNITS ✱ ✱ ✱ ✱ 0 to +5 10 35 THROUGHPUT SPEED Conversion Time Complete Cycle Throughput Rate MAX ISINK = 1.6mA ISOURCE = 500µA High-Z State, VOUT = 0V to VDIG High-Z State +4 DIGITAL TIMING Bus Access Time Bus Relinquish Time +0.8 VD +0.3V ±10 ±10 ✱ ✱ Parallel 12 bits Straight Binary +0.4 ✱ ±5 The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADS7820 2 SPECIFICATIONS (CONT) ELECTRICAL TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference, unless otherwise specified. ADS7820P/U PARAMETER POWER SUPPLIES Specified Performance VDIG VANA +IDIG +IANA ADS7820PB/UB CONDITIONS MIN TYP MAX Must be ≤ VANA +4.75 +4.75 +5 +5 0.3 16 +5.25 +5.25 Power Dissipation f S = 100kHz MIN ✱ ✱ TYP ✱ ✱ ✱ ✱ 100 TEMPERATURE RANGE Specified Performance Derated Performance Storage Thermal Resistance (θJA) Plastic DIP SOIC –40 –55 –65 +85 +125 +150 75 75 ✱ ✱ ✱ ✱ ✱ MAX UNITS ✱ ✱ V V mA mA ✱ mW ✱ ✱ ✱ °C °C °C °C/W °C/W NOTES: (1) LSB means Least Significant Bit. For the 12-bit, 0 to +5V input ADS7820, one LSB is 1.22mV. (2) Typical rms noise at worst case transitions and temperatures. (3) Adjustable to zero with external potentiometer as shown in Figure 4b. (4) Full scale error is the worst case of Full Scale untrimmed deviation from ideal last code transition divided by the transition voltage and includes the effect of offset error. (5) All specifications in dB are referred to a full-scale input. (6) FullPower Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB, or 10 bits of accuracy. (7) Recovers to specified performance after 2 x FS input overvoltage. ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY Analog Inputs: VIN .................................................... –0.7V to +VANA +0.3V REF .................................... +VANA +0.3V to AGND2 –0.3V CAP ........................................... Indefinite Short to AGND2 Momentary Short to VANA Ground Voltage Differences: DGND, AGND1, AGND2 ................... ±0.3V VANA ....................................................................................................... 7V VDIG to VANA ..................................................................................... +0.3V VDIG ....................................................................................................... 7V Digital Inputs ............................................................ –0.3V to +VDIG +0.3V Maximum Junction Temperature ................................................... +165°C Internal Power Dissipation ............................................................. 825mW Lead Temperature (soldering, 10s) ................................................ +300°C Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PACKAGE INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) ADS7820P ADS7820PB ADS7820U ADS7820UB Plastic DIP Plastic DIP SOIC SOIC 246 246 217 217 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION PRODUCT ADS7820P ADS7820PB ADS7820U ADS7820UB MAXIMUM LINEARITY ERROR (LSB) MINIMUM SIGNAL-TO(NOISE + DISTORTION) RATIO (dB) ±1.0 ±0.5 ±1.0 ±0.5 70 72 70 72 SPECIFICATION TEMPERATURE RANGE PACKAGE –40°C –40°C –40°C –40°C Plastic DIP Plastic DIP SOIC SOIC to to to to +85°C +85°C +85°C +85°C ® 3 ADS7820 PIN CONFIGURATION VIN 1 28 VDIG AGND1 2 27 VANA REF 3 26 BUSY CAP 4 25 CS AGND2 5 24 R/C D11 (MSB) 6 23 BYTE D10 7 22 DZ ADS7820 D9 8 21 DZ D8 9 20 DZ D7 10 19 DZ D6 11 18 D0 (LSB) D5 12 17 D1 D4 13 16 D2 DGND 14 15 D3 PIN ASSIGNMENTS PIN # NAME DESCRIPTION 1 VIN 2 AGND1 Analog Input. Full-scale input range is 0 to +5V. 3 REF Reference Input/Output. Outputs internal reference of +2.5V nominal. Can also be driven by external system reference. In both cases, connect to ground with a 2.2µF Tantalum capacitor. 4 CAP Reference Buffer Capacitor. 2.2µF Tantalum to ground. 5 AGND2 6 D11 (MSB) 7 D10 Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW. 8 D9 Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW. 9 D8 Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW. 10 D7 Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW. 11 D6 Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW. 12 D5 Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW. 13 D4 Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW. 14 DGND 15 D3 Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW. 16 D2 Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW. 17 D1 Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW. 18 D0 (LSB) 19 DZ Data Zero. LOW when CS LOW and R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW. 20 DZ Data Zero. LOW when CS LOW and R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW. 21 DZ Data Zero. LOW when CS LOW and R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW. 22 DZ Data Zero. LOW when CS LOW and R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW. 23 BYTE Byte Select. With BYTE LOW, data will be output as indicated above, causing pin 6 (D11) to output the MSB, and pin 18 (D0) to output the LSB. Pins 19 to 22 will output LOWs. With BYTE HIGH, the top and bottom 8 bits of data will be switched, so that pin 6 outputs data bit 3, pin 9 outputs data bit 0 (LSB), pin 10 to 13 output LOWs, pin 15 outputs data bit 11 (MSB) and pin 22 outputs data bit 4. 24 R/C Read/Convert input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion. With CS LOW, a rising edge on R/C enables the output data bits. 25 CS Chip Select. Internally OR’d with R/C. With R/C LOW, a falling edge on CS will initiate a conversion. With R/C HIGH, a falling edge on CS will enable the output data bits. 26 BUSY 27 VANA Analog Supply Input. Nominally +5V. Connect directly to pin 28. Decouple to ground with 0.1µF ceramic and 10µF Tantalum capacitors. 28 VDIG Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be ≤ VANA. Analog Ground. Used internally as ground reference point. Analog Ground. Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW. Digital Ground. Data Bit 0. Lease Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW. Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the output register. With CS LOW and R/C HIGH, output data will be valid when BUSY rises, so that the rising edge can be used to latch the data. CS or R/C must be high when BUSY rises, or another conversion will start, without time for signal acquisition. ® ADS7820 4 TYPICAL PERFORMANCE CURVES At TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference, unless otherwise specified. CONVERSION TIME vs TEMPERATURE 6.2 2.515 6.1 Conversion Time (µs) Internal Reference (V) INTERNAL REFERENCE VOLTAGE vs TEMPERATURE 2.52 2.51 2.505 2.5 2.495 2.49 2.485 6 5.9 5.8 5.7 5.6 5.5 2.48 5.4 –40 –15 10 35 60 85 –40 ADS7820 AT +25°C 12-Bit LSBs 60 85 Min/Max DNL Errors –0.073 at 00512 0.087 at 02047 12-Bit LSBs 1024 35 ADS7820 AT +25°C 0.2 +0.1 0 –0.1 –0.2 512 10 Temperature (°C) Min/Max INL Errors –0.051 at 03962 0.086 at 02048 0 –15 Temperature (°C) 1536 2048 2560 3072 3584 4096 0.2 +0.1 0 –0.1 –0.2 0 Decimal Code 512 1024 1536 2048 2560 3072 3584 4096 Decimal Code ® 5 ADS7820 BASIC OPERATION CS and R/C are internally OR’d and level triggered. There is not a requirement which input goes LOW first when initiating a conversion. If, however, it is critical that CS or R/C initiates conversion ‘n’, be sure the less critical input is LOW at least 10ns prior to the initiating input. Figure 1 shows a basic circuit to operate the ADS7820 with a full parallel data output. Taking R/C (pin 24) LOW for a minimum of 40ns (5.4µs max) will initiate a conversion. BUSY (pin 26) will go LOW and stay LOW until the conversion is completed and the output registers are updated. Data will be output in Straight Binary with the MSB on pin 6. BUSY going HIGH can be used to latch the data. All convert commands will be ignored while BUSY is LOW. To reduce the number of control pins, CS can be tied LOW using R/C to control the read and convert modes. However, the output will become active whenever R/C goes HIGH. Refer to the Reading Data section. The ADS7820 will begin tracking the input signal at the end of the conversion. Allowing 10µs between convert commands assures accurate acquisition of a new signal. CS R/C BUSY OPERATION 1 X X None. Databus is in Hi-Z state. ↓ 0 1 Initiates conversion “n”. Databus remains in Hi-Z state. STARTING A CONVERSION 0 ↓ 1 Initiates conversion “n”. Databus enters Hi-Z state. The combination of CS (pin 25) and R/C (pin 24) LOW for a minimum of 40ns immediately puts the sample/hold of the ADS7820 in the hold state and starts conversion ‘n’. BUSY (pin 26) will go LOW and stay LOW until conversion ‘n’ is completed and the internal output register has been updated. All new convert commands during BUSY LOW will be ignored. CS and/or R/C must go HIGH before BUSY goes HIGH or a new conversion will be initiated without sufficient time to acquire a new signal. 0 1 ↑ Conversion “n” completed. Valid data from conversion “n” on the databus. ↓ 1 1 Enables databus with valid data from conversion “n”. ↓ 1 0 Enables databus with valid data from conversion “n-1”(1). Conversion n in process. 0 ↑ 0 Enables databus with valid data from conversion “n-1”(1). Conversion “n” in process. 0 0 ↑ New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C must be HIGH when BUSY goes HIGH. X X 0 New convert commands ignored. Conversion “n” in process. The ADS7820 will begin tracking the input signal at the end of the conversion. Allowing 10µs between convert commands assures accurate acquisition of a new signal. Refer to Table I for a summary of CS, R/C, and BUSY states and Figures 3 through 5 for timing diagrams. 0 to +5V + NOTE: (1) See Figures 2 and 3 for constraints on data valid from conversion “n-1”. Table I. Control Line Functions for “Read” and “Convert”. 1 28 2 27 2.2µF 3 26 4 25 5 24 B11 (MSB) 6 23 B10 7 2.2µF + + 0.1µF + +5V 10µF Convert Pulse 22 LOW ADS7820 B9 8 21 LOW B8 9 20 LOW B7 10 19 LOW B6 11 18 B0 (LSB) B5 12 17 B1 B4 13 16 B2 14 15 B3 FIGURE 1. Basic Operation (Byte Low). ® ADS7820 6 40ns min 5.4µs max READING DATA PARALLEL OUTPUT (During a Conversion) After conversion ‘n’ has been initiated, valid data from conversion ‘n-1’ can be read and will be valid up to 16µs after the start of conversion ‘n’. Do not attempt to read data from 16µs after the start of conversion ‘n’ until BUSY (pin 26) goes HIGH; this may result in reading invalid data. Refer to Table III and Figures 3 and 5 for timing specifications. The ADS7820 outputs full or byte-reading parallel data in Straight Binary data output format. The parallel output will be active when R/C (pin 24) is HIGH and CS (pin 25) is LOW. Any other combination of CS and R/C will tri-state the parallel output. Valid conversion data can be read in a full parallel, 12-bit word or two 8-bit bytes on pins 6-13 and pins 15-22. BYTE (pin 23) can be toggled to read both bytes within one conversion cycle. Refer to Table II for ideal output codes and Figure 2 for bit locations relative to the state of BYTE. Note! For the best possible performance, data should not be read during a conversion. The switching noise of the asynchronous data transfer can cause digital feedthrough degrading the converter’s performance. The number of control lines can be reduced by tieing CS LOW while using R/C to initiate conversions and activate the output mode of the converter. See Figure 3. DIGITAL OUTPUT STRAIGHT BINARY DESCRIPTION ANALOG INPUT Full Scale Range 0 to +5V Least Significant Bit (LSB) 1.22mV Full Scale Midscale One LSB below Midscale Zero Scale 4.99878V BINARY CODE HEX CODE SYMBOL DESCRIPTION 1111 1111 1111 FFF t1 Convert Pulse Width 5400 ns Data Valid Delay after R/C LOW 8 µs 65 8 ns µs MIN TYP MAX UNITS 40 2.5V 1000 0000 0000 800 t2 2.49878V 0111 1111 1111 7FF t3 t4 BUSY Delay from R/C LOW BUSY LOW 0V 0000 0000 0000 0 t5 BUSY Delay after End of Conversion 220 ns t6 Aperture Delay 40 ns t7 Conversion Time 7.6 t8 Acquisition Time Table II. Ideal Input Voltages and Output Codes. PARALLEL OUTPUT (After a Conversion) After conversion ‘n’ is completed and the output registers have been updated, BUSY (pin 26) will go HIGH. Valid data from conversion ‘n’ will be available on D11-D0 (pin 6-13 and 15-18 when BYTE is LOW). BUSY going HIGH can be used to latch the data. Refer to Table III and Figures 3 and 5 for timing specifications. 8 µs 2 µs t9 Bus Relinquish Time 10 35 t10 BUSY Delay after Data Valid 50 200 ns t11 Previous Data Valid after R/C LOW 7.4 µs 83 ns µs t7 + t6 Throughput Time t12 R/C to CS Setup Time 10 ns t13 Time Between Conversions 10 µs t14 Bus Access Time and BYTE Delay 10 9 10 83 ns TABLE III. Conversion Timing. BYTE LOW BYTE HIGH +5V Bit 11 (MSB) 6 Bit 10 7 23 Bit 3 6 22 LOW Bit 2 7 ADS7820 23 22 Bit 4 ADS7820 Bit 9 8 21 LOW Bit 1 8 21 Bit 5 Bit 8 9 20 LOW Bit 0 (LSB) 9 20 Bit 6 Bit 7 10 19 LOW LOW 10 19 Bit 7 Bit 6 11 18 Bit 0 (LSB) LOW 11 18 Bit 8 Bit 5 12 17 Bit 1 LOW 12 17 Bit 9 Bit 4 13 16 Bit 2 LOW 13 16 Bit 10 14 15 Bit 3 14 15 Bit 11 FIGURE 2. Bit Locations Relative to State of BYTE (pin 23). ® 7 ADS7820 t1 R/C t13 t2 t4 BUSY t3 t6 t5 Convert Acquire MODE Acquire t7 Previous Data Valid DATA BUS t8 Previous Data Valid Hi-Z t9 Convert Data Valid Not Valid Hi-Z t10 t11 FIGURE 3. Conversion Timing with Outputs Enabled after Conversion (CS Tied LOW.) t12 t12 t12 t12 R/C t1 CS t3 t4 BUSY t6 MODE Convert Acquire Acquire t7 Hi-Z State DATA BUS Data Valid t9 t14 FIGURE 4. Using CS to Control Conversion and Read Timing. t12 t12 R/C CS BYTE Pins 6 - 13 Hi-Z High Byte t14 Pins 15 - 22 Hi-Z t14 Low Byte FIGURE 5. Using CS and BYTE to Control Data Bus. ® ADS7820 Low Byte 8 High Byte Hi-Z t9 Hi-Z Hi-Z State Data Valid INPUT RANGE REF The ADS7820 offers a standard 0V to 5V input range. Figure 6 shows the required circuit connections for the ADS7820 with and without the gain adjustment hardware. Adjustments for offset and gain are described in the calibration section of this data sheet. REF (pin 3) is an input for an external reference or the output for the internal 2.5V reference. A 2.2µF capacitor should be connected as close to the REF pin as possible. The capacitor and the output resistance of REF create a low pass filter to bandlimit noise on the reference. Using a smaller value capacitor will introduce more noise to the reference degrading the SNR and SINAD. The REF pin should not be used to drive external AC or DC loads. CALIBRATION The range for the external reference is 2.3V to 2.7V and determines the actual LSB size. Increasing the reference voltage will increase the full scale range and the LSB size of the converter which can improve the SNR. The ADS7820 can be trimmed in hardware or software. There is no external, offset adjustment. If offset adjustment is required, an op amp featuring an offset trim pin should be used to drive the ADS7820. The offset should be trimmed before the gain since the offset directly affects the gain. To achieve optimum performance, several iterations may be required. CAP CAP (pin 4) is the output of the internal reference buffer. A 2.2µF capacitor should be placed as close to the CAP pin as possible to provide optimum switching currents for the CDAC throughout the conversion cycle and compensation for the output of the internal buffer. Using a capacitor any smaller than 1µF can cause the output buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 2.2µF will have little affect on improving performance. GAIN ADJUSTMENT To calibrate the gain of the ADS7820, a 576kΩ resistor must be tied between the REF pin and a 5V potentiometer (see Figure 6b). The calibration range is ±15mV for the gain. REFERENCE The ADS7820 can operate with its internal 2.5V reference or an external reference. By applying an external reference to pin 3, the internal reference can be bypassed. The reference voltage at REF is buffered internally with the output on CAP (pin 4). The output of the buffer is capable of driving up to 2mA of current to a DC load. DC loads requiring more than 2mA of current from the CAP pin will begin to degrade the linearity of the ADS7820. Using an external buffer will allow the internal reference to be used for larger DC loads and AC loads. Do not attempt to directly drive an AC load with the output voltage on CAP. This will cause performance degradation of the converter. The internal reference has an 8 ppm/°C drift (typical) and accounts for approximately 20% of the full scale error (FSE = ±0.5% for low grade, ±0.25% for high grade). a) WITHOUT EXTERNAL GAIN ADJUSTMENT 1 0 to +5V 2 2.2µF + b) WITH EXTERNAL GAIN ADJUSTMENT 2 AGND1 2.2µF +5V 3 1 0 to +5V VIN + 3 REF VIN AGND1 REF 576kΩ 4 2.2µF 4 50kΩ CAP Gain + 2.2µF 5 5 AGND2 CAP + AGND2 FIGURE 6. Circuit Diagram With and Without External Gain Adjustment. ® 9 ADS7820 LAYOUT SIGNAL CONDITIONING The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of charge injection which can cause the driving op amp to oscillate. The FET switch on the ADS7820, compared to the FET switches on other CMOS A/D converters, releases 5%-10% of the charge. There is also a resistive front end which attenuates any charge which is released. The end result is a minimal requirement for the anti-alias filter on the front end. Any op amp sufficient for the signal in an application will be sufficient to drive the ADS7820. POWER For optimum performance, tie the analog and digital power pins to the same +5V power supply and tie the analog and digital grounds together. As noted in the electrical specifications, the ADS7820 uses 90% of its power for the analog circuitry. The ADS7820 should be considered as an analog component. The +5V power for the A/D should be separate from the +5V used for the system’s digital logic. Connecting VDIG (pin 28) directly to a digital supply can reduce converter performance due to switching noise from the digital logic. For best performance, the +5V supply can be produced from whatever analog supply is used for the rest of the analog signal conditioning. If +12V or +15V supplies are present, a simple +5V regulator can be used. Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter the supply. Either using a filtered digital supply or a regulated analog supply, both VDIG and VANA should be tied to the same +5V source. INTERMEDIATE LATCHES The ADS7820 does have tri-state outputs for the parallel port, but intermediate latches should be used if the bus will be active during conversions. If the bus is not active during conversion, the tri-state outputs can be used to isolate the A/D from other peripherals on the same bus. Tri-state outputs can also be used when the A/D is the only peripheral on the data bus. Intermediate latches are beneficial on any monolithic A/D converter. The ADS7820 has an internal LSB size of 610µV. Transients from fast switching signals on the parallel port, even when the A/D is tri-stated, can be coupled through the substrate to the analog circuitry causing degradation of converter performance. The effects of this phenomenon will be more obvious when using the pin-compatible ADS7821 or any of the other 16-bit converters in the ADS Family. This is due to the smaller internal LSB size of 38µV. GROUNDING Three ground pins are present on the ADS7820. DGND is the digital supply ground. AGND2 is the analog supply ground. AGND1 is the ground which all analog signals internal to the A/D are referenced. AGND1 is more susceptible to current induced voltage drops and must have the path of least resistance back to the power supply. All the ground pins of the A/D should be tied to the analog ground plane, separated from the system’s digital logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to the “system” ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents from modulating the analog ground through a common impedance to power ground. ® ADS7820 10