® ADS ADS804 804 ADS U 804 E DEMO BOARD AVAILABLE 12-Bit, 10MHz Sampling ANALOG-TO-DIGITAL CONVERTER TM FEATURES APPLICATIONS ● ● ● ● ● ● ● ● ● ● ● HIGH SFDR: 80dB at NYQUIST HIGH SNR: 69dB LOW POWER: 180mW SMALL 28-LEAD SSOP AND SOIC PACKAGES LOW DLE: ±0.3LSB FLEXIBLE INPUT RANGE OVERRANGE INDICATOR DESCRIPTION The ADS804 is a high-speed, high dynamic range, 12-bit pipelined analog-to-digital converter. This converter includes a high-bandwidth track/hold that gives excellent spurious performance up to and beyond the Nyquist rate. This high-bandwidth, linear track/hold minimizes harmonics and has low jitter, leading to excellent SNR performance. The ADS804 is also pin-compatible with the 5MHz ADS803 and the 20MHz ADS805. The ADS804 provides an internal reference and can be programmed for a 2Vp-p input range for the best spurious performance and ease of driving. Alternatively, the 5Vp-p input range can be used for the lowest input referred noise of 0.09 LSBs rms giving superior IF AND BASEBAND DIGITIZATION CCD IMAGING SCANNERS TEST INSTRUMENTATION imaging performance. There is also a capability to set the input range in between the 2Vp-p and 5Vp-p input ranges or to use external reference. The ADS804 also provides an overrange indicator flag to indicate an input range that exceeds the full-scale input range of the converter. This flag can be used to reduce the gain of the front end gain-ranging circuitry. The ADS804 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for communications, medical imaging, video and test instrumentation applications. The ADS804 is available in 28-Lead SSOP and SOIC packages. +VS VDRV CLK ADS804 Timing Circuitry VIN IN 12-Bit Pipelined A/D Core T/H IN (Opt.) Error Correction Logic 3-State Outputs D0 • • • D11 CM OVR Reference Ladder and Driver Reference and Mode Select REFT VREF SEL REFB OE International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1997 Burr-Brown Corporation PDS-1381C Printed in U.S.A. October, 1998 SPECIFICATIONS At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, sampling rate = 10MHz, unless otherwise specified. ADS804U PARAMETER CONDITIONS MIN RESOLUTION SPECIFIED TEMPERATURE RANGE CONVERSION CHARACTERISTICS Sample Rate Data Latency ANALOG INPUT Single-Ended Input Range Single-Ended Input Range (Optional) Common-Mode Voltage Input Impedance Track-Mode Input Bandwidth DYNAMIC CHARACTERISTICS Differential Linearity Error (Largest Code Error) f = 500kHz No Missing Codes Spurious Free Dynamic Range(2) f = 4.8MHz Two-Tone Intermodulation Distortion(4) f = 3.5MHz and 4.0MHz (–7dBFS each tone) Signal-to-Noise Ratio (SNR) f = 4.8MHz Signal-to-(Noise + Distortion) (SINAD) f = 4.8MHz Effective Number of Bits at 4.8MHz(5) Input Referred Noise Integral Nonlinearity Error f = 500kHz Aperture Delay Time Aperture Jitter Overvoltage Recovery Time Full-Scale Step Acquisition Time DIGITAL INPUTS Logic Family Convert Command High Level Input Current (VIN = 5V)(6) Low Level Input Current (VIN = 0V) High Level Input Voltage Low Level Input Voltage Input Capacitance DIGITAL OUTPUTS Logic Family Convert Command Output Voltages, VDRV = +5V Low-Level High-Level Low-Level High-Level Output Voltages, VDRV = +3V Low-Level High-Level 3-State Enable Time 3-State Enable Time Output Capacitance ACCURACY (5Vp-p Input Range) Zero Error (Referred to –FS) Zero Error Drift Gain Error(7) Gain Error Drift(7) Gain Error(8) Gain Error Drift(8) Power Supply Rejection of Gain Reference Input Resistance Internal Voltage Reference Tolerance (VREF = 2.5V) Internal Voltage Reference Tolerance (VREF = 1.0V) MAX MIN –40 to +85 –40 to +85 °C 10M ✻ ✻ Samples/s Clk Cycles ✻ ✻ V V V MΩ || pF MHz ✻ LSB ✻ 3.5 5 ✻ ✻ ✻ ✻ ✻ +2.5 1.25 || 16 270 ±0.3 ±0.75 Guaranteed 73 ✻ Guaranteed ✻ 80 76 ✻ dBFS ✻ dBc 66.5 69 ✻ ✻ dBFS 65 68 11 0.09 0.23 ✻ ✻ ✻ ✻ ✻ dBFS Bits LSBs rms LSBs rms 0V to 5V Input 1.5V to 3.5V Input ±1 1 4 2 30 1.5 x FS Input ±2 ✻ ✻ ✻ ✻ ✻ ✻ CMOS Compatible CMOS Compatible Rising Edge of Convert Clock Rising Edge of Convert Clock 100 ✻ 10 ✻ +3.5 ✻ +1.0 ✻ 5 ✻ Start Conversion CMOS/TTL Compatible Straight Offset Binary IOL = 50µA IOH = 50µA IOL = 1.6mA IOH = 0.5mA ✻ ✻ ✻ +0.4 ✻ +2.4 ✻ +0.1 ✻ +2.5 At 25°C 20 2 5 40 10 ✻ ✻ ✻ ✻ ✻ 0.2 ±5 ±1.5 ✻ ✻ ✻ At 25°C ±15 At 25°C ∆ VS = ±5% 60 ±15 82 1.6 ±2.0 2 ✻ ✻ ±1.5 ✻ ✻ ±35 ±14 At 25°C At 25°C LSB ns ps rms ns ns µA µA V V pF CMOS/TTL Compatible Straight Offset Binary +0.1 +4.6 IOL = 50µA IOH = 50µA OE = L OE = H UNITS Bits 1.5 0 –3dBFS Input MAX ✻(1) 6 2Vp-p 5Vp-p TYP 12 10k ® ADS804 TYP ADS804E ✻ ✻ ✻ ✻ ✻ V V V V V V ns ns pF %FS ppm/°C %FS ppm/°C %FS ppm/°C dB kΩ mV mV SPECIFICATIONS (CONT) At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, sampling rate = 10MHz, unless otherwise specified. ADS804U PARAMETER CONDITIONS MIN POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Power Dissipation Thermal Resistance, θJA 28-Lead SOIC 28-Lead SSOP +4.7 TYP +5.0 36 180 ADS804E MAX MIN TYP MAX +5.3 40 200 ✻ ✻ ✻ ✻ ✻ ✻ ✻ 75 50 UNITS V mA mW °C/W °C/W NOTES: (1) An asterisk (✻) indicates same specifications as the ADS804U. (2) Spurious Free Dynamic Range difference in dB between the rms input amplitude to the peak spar level in the output frequency spectrum. (3) dBFS means dB relative to full scale. (4) Two-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (5) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (6) Internal 50kΩ pull-down resistor. (7) Includes internal reference. (8) Excludes internal reference. ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY +VS, VDRV ........................................................................................... +6V Analog Input ........................................................... (–0.3V) to (+VS +0.3V) Logic Input ............................................................. (–0.3V) to (+VS +0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +150°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. DEMO BOARD ORDERING INFORMATION PRODUCT DEMO BOARD ADS804U DEM-ADS80xU ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) ADS804U ADS804E " SO-28 Surface Mount SSOP-28 Surface Mount " 217 324 " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA –40°C to +85°C –40°C to +85°C " ADS804U ADS804E " ADS804U ADS804E ADS804E/1K Rails Rails Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. For detailed Tape and Reel mechanical information refer to Appendix B of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 ADS804 PIN CONFIGURATION PIN DESCRIPTIONS Top View SOIC/SSOP OVR 1 28 VDRV B1 2 27 +VS B2 3 26 GND B3 4 25 IN B4 5 24 GND B5 6 23 IN B6 7 22 REFT B7 8 21 CM B8 9 20 REFB B9 10 19 VREF B10 11 18 SEL B11 12 17 GND B12 13 16 +VS CLK 14 15 OE ADS804 PIN DESIGNATOR 1 OVR 2 3 4 5 6 7 8 9 10 11 12 13 14 15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 CLK OE 16 17 18 +VS GND SEL 19 20 21 22 23 24 25 26 27 28 VREF REFB CM REFT IN GND IN GND +VS VDRV DESCRIPTION Over Range Indicator (See Application Section) Data Bit 1(D11) (MSB) Data Bit 2 (D10) Data Bit 3 (D9) Data Bit 4 (D8) Data Bit 5 (D7) Data Bit 6 (D6) Data Bit 7 (D5) Data Bit 8 (D4) Data Bit 9 (D3) Data Bit 10 (D2) Data Bit 11 (D1) Data Bit 12 (D0) (LSB) Convert Clock Input Output Enable. H = High Impedance State. L = Low or floating, normal operation (Internal pull-down resistor). +5V Supply Ground Input Range Select (See Application Section) Reference Voltage Select (I/O) Bottom Reference Common-Mode Voltage Top Reference Analog Input (–) Ground Analog Input (+) Ground +5V Supply Output Driver Voltage (See Application Section). TIMING DIAGRAM N+2 N+1 Analog In N+4 N+3 N tD N+5 tL tCONV N+7 N+6 tH Clock 6 Clock Cycles t2 Data Out N–6 N–5 N–4 N–3 N–2 N-1 N Data Invalid SYMBOL tCONV tL tH tD t1 t2 t1 DESCRIPTION MIN Convert Clock Period Clock Pulse Low Clock Pulse High Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max 100 48 48 ® ADS804 N+1 4 TYP MAX UNITS 100µs ns ns ns ns ns ns 49 49 2 3.9 12 TYPICAL PERFORMANCE CURVES At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, sampling rate = 10MHz, unless otherwise specified. SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 0 fIN = 4.8MHz –20 –40 –40 Amplitude (dB) Amplitude (dB) fIN = 500kHz –20 –60 –80 –100 –60 –80 –100 –120 –120 0 1.0 2.0 3.0 4.0 5.0 0 1.0 Frequency (MHz) TWO-TONE INTERMODULATION 3.0 4.0 5.0 DIFFERENTIAL LINEARITY ERROR 0 1.0 fIN = 4.8MHz f1 = 3.5MHz at –7dB f2 = 4MHz at –7dB IMD (3) = –76dBc –20 0.5 –40 DLE (LSB) Magnitude (dBFSR) 2.0 Frequency (MHz) –60 0 –80 –0.5 –100 –120 –1.0 0 1.25 2.5 3.75 5.0 0 1024 2048 Frequency (MHz) 3072 INTEGRAL LINEARITY ERROR SWEPT POWER SFDR 4.0 100 fIN = 500kHz fIN = 4.8MHz 80 SFDR (dBFS, dBc) 2.0 ILE (LSB) 4096 Output Code 0 –2.0 dBFS 60 dBc 40 20 0 –4.0 0 1024 2048 3072 4096 –60 Output Code –50 –40 –30 –20 –10 0 Input Amplitude (dBFS) ® 5 ADS804 TYPICAL PERFORMANCE CURVES (CONT) At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, sampling rate = 10MHz, unless otherwise specified. DYNAMIC PERFORMANCE vs INPUT FREQUENCY (Differential Input, VIN = 5Vp-p) 85 85 80 80 SFDR, SNR (dBFS) SFDR, SNR (dBFS) DYNAMIC PERFORMANCE vs INPUT FREQUENCY SFDR 75 70 SNR 65 SFDR 75 70 SNR 65 60 60 0.1 1 0.1 10 1 10 Frequency (MHz) Frequency (MHz) DIFFERENTIAL LINEARITY vs TEMPERATURE SPURIOUS FREE DYNAMIC RANGE vs TEMPERATURE 84 0.40 fIN = 4.8MHz SFDR (dBFS) fIN = 500kHz 0.30 fIN = 500kHz 80 fIN = 4.8MHz 78 76 0.25 –50 –25 0 25 50 75 –50 100 –25 0 25 50 Temperature (°C) Temperature (°C) SIGNAL-TO-NOISE RATIO vs TEMPERATURE SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE 75 100 75 100 70 72 fIN = 500kHz SINAD (dBFS) 70 SNR (dBFS) DLE (LSB) 82 0.35 68 fIN = 4.8MHz 69 fIN = 500kHz 68 66 fIN = 4.8MHz 67 64 –50 –25 0 25 50 75 –50 100 ® ADS804 –25 0 25 50 Temperature (°C) Temperature (°C) 6 TYPICAL PERFORMANCE CURVES (CONT) At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, sampling rate = 10MHz, unless otherwise specified. POWER DISSIPATION vs TEMPERATURE OUTPUT NOISE HISTOGRAM (DC INPUT) 185 800k Counts Power (mW) 600k 180 400k 175 200k 170 0 –50 –25 0 25 50 75 100 N-2 Temperature (°C) N-1 N N+1 N+2 Code OUTPUT NOISE HISTOGRAM (DC Input, VIN = 5Vp-p Range) 800k Counts 600k 400k 200k 0 N-2 N-1 N N+1 N+2 Code ® 7 ADS804 APPLICATION INFORMATION input of the ADS804 will be beneficial in almost all interface configurations. This will decouple the op amp’s output from the capacitive load and avoid gain peaking, which can result in increased noise. For best spurious and distortion performance, the resistor value should be kept below 100Ω. Furthermore, the series resistor together with the 100pF capacitor establish a passive low-pass filter, limiting the bandwidth for the wideband noise thus, help improving the SNR performance. DRIVING THE ANALOG INPUT The ADS804 allows its analog inputs to be driven either single-ended or differentially. The focus of the following discussion is on the single-ended configuration. Typically, its implementation is easier to achieve and the rated specifications for the ADS804 are characterized using the singleended mode of operation. DC-COUPLED WITHOUT LEVEL SHIFT In some applications the analog input signal may already be biased at a level which complies with the selected input range and reference level of the ADS804. In this case, it is only necessary to provide an adequately low source impedance to the selected input, IN or IN. Always consider wideband op amps since their output impedance will stay low over a wide range of frequencies. For those applications requiring the driving amplifier to provide a signal amplification, with a gain ≥ 3, consider using the decompensated voltage feedback op amp OPA643. AC-COUPLED INPUT CONFIGURATION Given in Figure 1 is the circuit example of the most common interface configuration for the ADS804. With the VREF pin connected to the SEL pin, the full-scale input range is defined to be 2Vp-p. This signal is ac-coupled in singleended form to the ADS804 using the low distortion voltagefeedback amplifier OPA642. As is generally necessary for single supply components, operating the ADS804 with a full-scale input signal swing requires a level-shift of the amplifier’s zero centered analog signal to comply with the A/D converters input range requirements. Using a DC blocking capacitor between the output of the driving amplifier and the converter’s input, a simple level-shifting scheme can be implemented. In this configuration, the top and bottom references (REFT, REFB) provide an output voltage of +3V and +2V, respectively. Here, two resistor pairs (2 x 2kΩ) are used to create a common-mode voltage of approximately +2.5V to bias the inputs of the ADS804 (IN, IN) to the required DC voltage. DC-COUPLED WITH LEVEL SHIFT Several applications may require that the bandwidth of the signal path include DC, in which case the signal has to be DC-coupled to the A/D converter. In order to accomplish this, the interface circuit has to provide a DC-level shift. The circuit shown in Figure 2 employs an op amp, A1, to sum the ground centered input signal with a required DC offset. The ADS804 typically operates with a +2.5V common-mode voltage, which is established at the center tap of the ladder and connected to the IN input of the converter. Amplifier A1 operates in inverting configuration. Here resistors R1 and R2 set the DC-bias level for A1. Because of the op amp’s noise gain of +2V/V, assuming RF = RIN, the DC offset voltage applied to its non-inverting input has to be divided down to +1.25V, resulting in a DC output voltage of +2.5V. An advantage of ac-coupling is that the driving amplifier still operates with a ground-based signal swing. This will keep the distortion performance at its optimum since the signal swing stays within the linear region of the op amp and sufficient headroom to the supply rails can be maintained. Consider using the inverting gain configuration to eliminate CMR induced errors of the amplifier. The addition of a small series resistor (RS) between the output of the op amp and the +5V –5V 2Vp-p VIN +VIN 0.1µF RS 24.9Ω 2kΩ REFT (+3V) 2kΩ IN OPA642 0V 100pF –VIN RF 402Ω ADS804 2kΩ RG 402Ω +2.5VDC IN 0.1µF 2kΩ (+2V) REFB (+1V) VREF SEL FIGURE 1. AC-Coupled Input Configuration for 2Vp-p Input Swing and Common-Mode Voltage at +2.5V Derived from Internal Top and Bottom Reference. ® ADS804 8 RF RIN +1V 0 +VS VIN REFT 2kΩ RS 24.9Ω IN OPA681 –1V 2Vp-p 100pF R1 ADS804 R2 +VS +2.5V + 0.1µF IN 0.1µF 10µF REFB (+1V) VREF SEL 2kΩ NOTE: RF = RIN, G = –1 FIGURE 2. DC-Coupled, Single-Ended Input Configuration with DC-level Shift. DC voltage differences between the IN and IN inputs of the ADS804 effectively will produce an offset, which can be corrected for by adjusting the values of resistors R1 and R2. The bias current of the op amp may also result in an undesired offset. The selection criteria of the appropriate op amp should include the input bias current, output voltage swing, distortion and noise specification. Note that in this example the overall signal phase is inverted. To re-establish the original signal polarity it is always possible to interchange the IN and IN connections. RG 0.1µF 22Ω 1:n VIN IN 100pF RT ADS804 22Ω IN CM 100pF SINGLE-ENDED-TO-DIFFERENTIAL CONFIGURATION (TRANSFORMER COUPLED) In order to select the best suited interface circuit for the ADS804, the performance requirements must be known. If an ac-coupled input is needed for a particular application, the next step is to determine the method of applying the signal; either single-ended or differentially. The differential input configuration may provide a noticeable advantage of achieving good SFDR performance based on the fact that in the differential mode, the signal swing can be reduced to half of the swing required for single-ended drive. Secondly, by driving the ADS804 differentially, the even-order harmonics will be reduced. Figure 3 shows the schematic for the suggested transformer-coupled interface circuit. The resistor across the secondary side (RT) should be set to get an input impedance match (e.g., RT = n2 • RG). + 0.1µF 4.7µF FIGURE 3. Transformer-Coupled Input. gain for the internal reference buffer. For more design flexibility, the internal reference can be shut off and an external reference voltage used. Table I provides an overview of the possible reference options and pin configurations. REFERENCE OPERATION Integrated into the ADS804 is a bandgap reference circuit including logic that provides either a +1V or +2.5V reference output, by simply selecting the corresponding pin-strap configuration. Different reference voltages can be generated by the use of two external resistors, which will set a different MODE INPUT FULL-SCALE RANGE Internal Internal Internal External REQUIRED VREF CONNECT 2Vp-p +1V SEL VREF 5Vp-p +2.5V SEL GND TO 2V≤ FSR < 5V 1V < VREF < 2.5V R1 VREF and SEL FSR = 2 x VREF VREF = 1 + (R1/R2) R2 SEL and Gnd 1V < FSR < 5V 0.5V < VREF < 2.5V SEL +VS VREF Ext. VREF TABLE I. Selected Reference Configuration Examples. ® 9 ADS804 Disable Switch SEL VREF 1VDC to A/D REFT Resistor Network and Switches 800Ω Bandgap and Logic Reference Driver CM 800Ω REFB to A/D ADS804 FIGURE 4. Equivalent Reference Circuit. A simple model of the internal reference circuit is shown in Figure 4. The internal blocks are a 1V-bandgap voltage reference, buffer, the resistive reference ladder and the drivers for the top and bottom reference which supply the necessary current to the internal nodes. As shown, the output of the buffer appears at the VREF pin. The full-scale input span of the ADS804 is determined by the voltage at VREF, according to the equation (1): Full-Scale Input Span = 2 x VREF operation with all reference configurations, it is necessary to provide solid bypassing to the reference pins in order to keep the clock feedthrough to a minimum. Figure 5 shows the recommended decoupling network. (1) Note that the current drive capability of this amplifier is limited to about 1mA and should not be used to drive low loads. The programmable reference circuit is controlled by the voltage applied to the select pin (SEL). Refer to Table I for an overview. IN In addition, the common-mode voltage (CMV) may be used as a reference level to provide the appropriate offset for the driving circuitry. However, care must be taken not to appreciably load this node, which is not buffered and has a high impedance. An alternate method of generating a commonmode voltage is given in Figure 6. Here, two external precision resistors (tolerance 1% or better) are located between the top and bottom reference pins. The commonmode level will appear at the midpoint. The output buffers of the top and bottom reference are designed to supply approximately 2mA of output current. VREF + 10µF + 0.1µF 10µF 0.1µF FIGURE 5. Recommended Reference Bypassing Scheme. ® ADS804 REFB FIGURE 6. Alternative Circuit to Generate Common-Mode Voltage. CM 0.1µF CMV 0.1µF 0.1µF 0.1µF R1 R2 IN ADS804 REFB 0.1µF ADS804 The top reference (REFT) and the bottom reference (REFB) are brought out mainly for external bypassing. For proper REFT REFT 10 SELECTING THE INPUT RANGE AND REFERENCE Figures 7 through 9 show a selection of circuits for the most common input ranges when using the internal reference of the ADS804. All examples are for single-ended input and operate with a nominal common-mode voltage of +2.5V. EXTERNAL REFERENCE OPERATION Depending on the application requirements, it might be advantageous to operate the ADS804 with an external reference. This may improve the DC accuracy if the external reference circuitry is superior in its drift and accuracy. To use the ADS804 with an external reference, the user must disable the internal reference (see Figure 10). By connecting the SEL pin to +VS, the internal logic will shut down the internal reference. At the same time, the output of the internal reference buffer is disconnected from the VREF pin, which now must be driven with the external reference. Note that a similar bypassing scheme should be maintained as described for the internal reference operation. 5V VIN IN 0V ADS804 IN VREF SEL 4.5V +2.5V VIN IN 0.5V ADS804 FIGURE 7. Internal Reference with 0V to 5V Input Range. REF1004 +2.5V +2.5V ext. IN + 0.1µF 10µF VREF SEL 1.24kΩ +5V +2VDC 3.5V VIN IN 4.99kΩ 1.5V ADS804 +2.5V ext. IN VREF FIGURE 10. External Reference, Input Range 0.5V to 4.5V (4Vp-p), with +2.5V Common-Mode Voltage. SEL +1V DIGITAL INPUTS AND OUTPUTS Over Range (OVR) One feature of the ADS804 is its ‘Over Range’ digital output (OVR). This pin can be used to monitor any out-of-range condition, which occurs every time the applied analog input voltage exceeds the input range (set by VREF). The OVR output is LOW when the input voltage is within the defined input range. It becomes HIGH when the input voltage is beyond the input range. This is the case when the input voltage is either below the bottom reference voltage or above the top reference voltage. OVR will remain active until the analog input returns to its normal signal range and another conversion is completed. Using the MSB and its complement in conjunction with OVR a simple clue logic can be built that detects the overrange and underrange conditions, (see Figure 11). It should be noted that OVR is a digital output which is updated along with the bit information corresponding to the particular sampling incidence of the analog signal. Therefore, the OVR data is subject to the same pipeline delay (latency) as the digital data. FIGURE 8. Internal Reference with 1.5V to 3.5V Input Range. 4V VIN IN 1V ADS804 +2.5V ext. IN VREF SEL R1 5kΩ VREF = 1V 1 + R1 R2 +1.5V R2 10kΩ FSR = 2 x VREF FIGURE 9. Internal Reference with 1V to 4V Input Range. ® 11 ADS804 MSB necessary, external buffers or latches may be used which provide the added benefit of isolating the ADS804 from any digital noise activities on the bus coupling back high frequency noise. In addition, resistors in series with each data line may help maintain the ac performance of the ADS804. Their use depends on the capacitive loading seen by the converter. Values in the range of 100Ω to 200Ω will limit the instantaneous current the output stage has to provide for recharging the parasitic capacitances, as the output levels change from L to H or H to L. Over = H OVR Under = H GROUNDING AND DECOUPLING Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for high frequency designs. Multi-layer PC boards are recommended for best performance since they offer distinct advantages like minimizing ground impedance, separation of signal layers by ground layers, etc. It is recommended that the analog and digital ground pins of the ADS804 be joined together at the IC and be connected only to the analog ground of the system. FIGURE 11. External Logic for Decoding Under- and Overrange Condition. CLOCK INPUT REQUIREMENTS Clock jitter is critical to the SNR performance of high speed, high resolution analog-to-digital converters. It leads to aperture jitter (tA) which adds noise to the signal being converted. The ADS804 samples the input signal on the rising edge of the CLK input. Therefore, this edge should have the lowest possible jitter. The jitter noise contribution to total SNR is given by the following equation. If this value is near your system requirements, input clock jitter must be reduced. JitterSNR = 20 log The ADS804 has analog and digital supply pins, however, the converter should be treated as an analog component and all supply pins should be powered by the analog supply. This will ensure the most consistent results, since digital supply lines often carry high levels of noise that would otherwise be coupled into the converter and degrade the achievable performance. 1 rms signal to rms noise 2 π ƒ IN t A Because of the pipeline architecture, the converter also generates high frequency current transients and noise that are fed back into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed. Figure 12 shows the recommended decoupling scheme for the analog supplies. In most cases, 0.1µF ceramic chip capacitors are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual supply pin. Therefore, they should be located as close to the supply pins as possible. In addition, a larger size bipolar capacitor (1µF to 22µF) should be placed on the PC board in close proximity to the converter circuit. Where: ƒIN is Input Signal Frequency tA is rms Clock Jitter Particularly in undersampling applications, special consideration should be given to clock jitter. The clock input should be treated as an analog input in order to achieve the highest level of performance. Any overshoot or undershoot of the clock signal may cause degradation of the performance. When digitizing at high sampling rates, the clock should have a 50% duty cycle (tH = tL), along with fast rise and fall times of 2ns or less. DIGITAL OUTPUTS The digital outputs of the ADS804 are designed to be compatible with both high speed TTL and CMOS logic families. The driver stage for the digital outputs is supplied through a separate supply pin, VDRV, which is not connected to the analog supply pins. By adjusting the voltage on VDRV, the digital output levels will vary respectively. Therefore, it is possible to operate the ADS804 on a +5V analog supply while interfacing the digital outputs to 3V logic. ADS804 +VS 27 +VS 16 0.1µF GND 17 0.1µF VDRV 28 0.1µF 2.2µF + It is recommended to keep the capacitive loading on the data lines as low as possible (≤ 15pF). Larger capacitive loads demand higher charging currents as the outputs are changing. Those high current surges can feed back to the analog portion of the ADS804 and influence the performance. If +5V +5V/+3V FIGURE 12. Recommended Bypassing for Analog Supply Pins. ® ADS804 GND 26 12