ADS8401 SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 16-BIT, 1.25 MSPS, UNIPOLAR INPUT, MICRO POWER SAMPLING ANALOG-TODIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE FEATURES APPLICATIONS D DWDM D Instrumentation D High-Speed, High-Resolution, Zero Latency D 1.25-MHz Sample Rate D 16-Bit NMC Ensured Over Temperature D Zero Latency Data Acquisition Systems D Unipolar Single-Ended Input Range: 0 V to Vref D Onboard Reference D Transducer Interface D Medical Instruments D Communication D Onboard Reference Buffer DESCRIPTION D High-Speed Parallel Interface The ADS8401 is a 16-bit, 1.25 MHz A/D converter with an internal 4.096-V reference. The device includes a 16-bit capacitor-based SAR A/D converter with inherent sample and hold. The ADS8401 offers a full 16-bit interface and an 8-bit option where data is read using two 8-bit read cycles. D Power Dissipation: 155 mW at 1.25 MHz Typ D Wide Digital Supply D 8-/16-Bit Bus Transfer The ADS8401 has a unipolar single-ended input. It is available in a 48-lead TQFP package and is characterized over the industrial –40°C to 85°C temperature range. D 48-Pin TQFP Package SAR +IN –IN + _ Output Latches and 3-State Drivers CDAC BYTE 16-/8-Bit Parallel DATA Output Bus Comparator RESET REFIN REFOUT 4.096-V Internal Reference Clock Conversion and Control Logic CONVST BUSY CS RD Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002–2003, Texas Instruments Incorporated ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION MODEL MAXIMUM INTEGRAL LINEARITY (LSB) ADS8401I ADS8401IB MAXIMUM DIFFERENTIAL LINEARITY (LSB) ±6 ±3 5 ±3.5 –2~3 2 3 –1~2 1 2 NO MISSING CODES RESOLUTION (BIT) PACKAGE TYPE 15 48 Pin TQFP 16 48 Pin TQFP PACKAGE DESIGNATOR TEMPERATURE RANGE PFB –40 C to –40°C 85°C PFB –40 C to –40°C 85°C ORDERING INFORMATION TRANSPORT MEDIA QUANTITY ADS8401IPFBT Tape and reel 250 ADS8401IPFBR Tape and reel 1000 ADS8401IBPFBT Tape and reel 250 ADS8401IBPFBR Tape and reel 1000 NOTE: For the most current specifications and package information, refer to our website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT +IN to AGND Voltage Voltage range +VA + 0.1 V –IN to AGND 0.5 V +VA to AGND –0.3 V to 7 V +VBD to BDGND –0.3 V to 7 V +VA to +VBD –0.3 V to 2.5 V Digital input voltage to BDGND –0.3 V to +VBD + 0.3 V Digital output voltage to BDGND –0.3 V to +VBD + 0.3 V Operating free-air temperature range, TA –40°C to 85°C Storage temperature range, Tstg –65°C to 150°C Junction temperature (TJ max) Power dissipation TQFP package θJA thermal impedance Vapor phase (60 sec) Lead temperature, temperature soldering Infrared (15 sec) 150°C (TJMax – TA)/θJA 86°C/W 215°C 220°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 SPECIFICATIONS TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Input Full-scale input voltage (see Note 1) +IN – –IN Absolute input voltage 0 +IN –0.2 –IN –0.2 Vref Vref + 0.2 0.2 V V Input capacitance 25 pF Input leakage current 0.5 nA 16 Bits System Performance Resolution No missing codes Integral linearity (see Notes 2 and 3) Differentiallinearity Differential linearity ADS8401I 15 ADS8401IB 16 ADS8401I –6 ±2.5 6 –3.5 ±2 3.5 ADS8401IB ADS8401I –2 ±1 3 ADS8401IB –1 ±0.75 2 Gain error (see Notes 4 and 5) LSB –1.5 ±0.5 1.5 mV –0.75 ±0.25 0.75 mV ADS8401I –0.15 0.15 –0.098 0.098 ADS8401IB Noise DC Power supply rejection ratio LSB ADS8401IB ADS8401I Offset error (see Note 4) Bits At FFFFh output code, +VA = 4.75 V to 5.25 V, Vref = 4.096 V, See Note 4 %FS 60 µV RMS 2 LSB Sampling Dynamics Conversion time Acquisition time 610 150 ns Throughput rate Aperture delay ns 1.25 MHz 2 ns Aperture jitter 25 ps Step response 100 ns 100 ns Overvoltage recovery (1) Ideal input span, does not include gain or offset error. (2) LSB means least significant bit (3) This is endpoint INL, not best fit. (4) Measured relative to an ideal full-scale input (+IN – –IN) of 4.096 V (5) This specification does not include the internal reference voltage error and drift. 3 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 SPECIFICATIONS (CONTINUED) TA = –40°C to 85°C, +VA = +5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Dynamic Characteristics Total harmonic distortion (THD) (see Note 1) Signal-to-noise ratio (SNR) Signal-to-noise + distortion (SINAD) Spurious free dynamic range (SFDR) VIN = 4 Vpp at 100 kHz VIN = 4 Vpp at 100 kHz –93 dB 86 dB VIN = 4 Vpp at 100 kHz VIN = 4 Vpp at 100 kHz 85 dB 93 dB 5 MHz –3dB Small signal bandwidth External Voltage Reference Input Reference voltage at REFIN, Vref 2.5 Reference resistance (see Note 2) 4.096 4.2 500 V kΩ Internal Reference Output Internal reference start-up time from 95% (+VA), with 1 µF storage capacitor 4.065 4.096 120 ms 4.13 V Vref range Source Current IOUT = 0 Line Regulation +VA = 4.75 ~ 5.25 V 0.6 mV Drift IOUT = 0 36 PPM/C Static load 10 µA Digital Input/Output Logic family L i level Logic l l CMOS VIH VIL IIH = 5 µA IIL = 5 µA VOH VOL IOH = 2 TTL loads IOL = 2 TTL loads +VBD–1 +VBD + 0.3 –0.3 0.8 +VBD – 0.6 +VBD 0 V 0.4 Straight Binary Data format Power Supply Requirements Power su supply ly voltage +VBD (see Notes 3 and 4) 2.95 +VA (see Note 4) +VA Supply current (see Note 5) Power dissipation (see Note 5) 4.75 fs = 1.25 MHz fs = 1.25 MHz 3.3 5.25 5 5.25 31 34 155 V V mA mW Temperature Range Operating free-air –40 85 (1) Calculated on the first nine harmonics of the input frequency (2) Can vary ±20% (3) The difference between +VA and +VBD should not be less than 2.3 V, i.e., if +VA is 5.25 V, +VBD should be minimum of 2.95 V. (4) +VBD ≥ +VA – 2.3 V (5) This includes only VA+ current. +VBD current is typically 1 mA with 5 pF load capacitance on output pins. 4 °C ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V (see Notes 1, 2, and 3) PARAMETER tCONV tACQ Conversion time tpd1 tpd2 CONVST low to conversion started (BUSY high) tw1 tsu1 Pulse duration, CONVST low tw2 Pulse duration, CONVST high Acquisition time MIN TYP MAX UNIT 600 610 ns 150 Propagation delay time, End of conversion to BUSY low Setup time, CS low to CONVST low th1 Pulse duration, BUSY signal low 20 ns ns 0 ns 20 ns 10 Min(tACQ) Pulse duration, BUSY signal high Hold time, First data bus data transition (RD low, or CS low for read cycle, or BYTE input changes) after CONVST low ns 20 CONVST falling edge jitter tw3 tw4 ns 35 ps ns 630 ns 40 ns 0 ns 0 ns 50 ns td1 tsu2 Delay time, CS low to RD low tw5 ten Pulse duration, RD low time td2 td3 Delay time, data hold from RD high 0 Delay time, BYTE rising edge or falling edge to data valid 2 tw6 th2 RD high 20 ns Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge 50 ns tpd4 tsu3 Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge Max(td5) 0 ns th3 Hold time, BYTE falling edge to RD falling edge 0 ns tdis Disable time, RD High (CS high for read cycle) to 3-stated data bus td5 Delay time, BUSY low to MSB data valid Setup time, RD high to CS high Enable time, RD low (or CS low for read cycle) to data valid Setup time, BYTE rising edge to RD falling edge 20 tsu4 Setup time, BYTE change before BUSY falling edge 2 (1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagrams. (3) All timings are measured with 20 pF equivalent loads on all data bits and BUSY pins. ns ns 20 ns ns 20 ns 0 ns 20 ns 5 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA = 5 V, +VBD = 3 V (see Notes 1, 2, and 3) PARAMETER tCONV tACQ Conversion time tpd1 tpd2 CONVST low to conversion started (BUSY high) tw1 tsu1 Pulse duration, CONVST low tw2 Pulse duration, CONVST high Acquisition time MIN TYP MAX UNIT 600 610 ns 150 Propagation delay time, end of conversion to BUSY low Setup time, CS low to CONVST low th1 Pulse duration, BUSY signal low 20 ns ns 0 ns 20 ns 10 Min(tACQ) Pulse duration, BUSY signal high Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or BUS 16/16 input changes) after CONVST low ns 20 CONVST falling edge jitter tw3 tw4 ns 40 ps ns 630 ns 40 ns 0 ns 0 ns 50 ns td1 tsu2 Delay time, CS low to RD low tw5 ten Pulse duration, RD low td2 td3 Delay time, data hold from RD high 0 Delay time, BUS16/16 or BYTE rising edge or falling edge to data valid 2 tw6 th2 Pulse duration, RD high time 20 ns Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge 50 ns tpd4 tsu3 Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge Max(td5) ns Setup time, BYTE rising edge to RD falling edge 0 ns th3 Hold time, BYTE falling edge to RD falling edge 0 ns tdis Disable time, RD High (CS high for read cycle) to 3-stated data bus td5 Delay time, BUSY low to MSB data valid delay time Setup time, RD high to CS high Enable time, RD low (or CS low for read cycle) to data valid 30 tsu4 Setup time, BYTE change before BUSY falling edge 2 (1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagrams. (3) All timings are measured with 10 pF equivalent loads on all data bits and BUSY pins. 6 ns ns 30 ns 30 ns 0 ns 30 ns ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 PIN ASSIGNMENTS BUSY BDGND +VBD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 BDGND PFB PACKAGE (TOP VIEW) 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 21 41 20 42 19 43 18 44 17 45 16 46 15 47 14 48 3 4 5 6 7 8 13 9 10 11 12 REFIN REFOUT NC +VA AGND +IN –IN AGND +VA +VA 1 2 +VBD DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 AGND AGND +VA AGND AGND +VBD RESET BYTE CONVST RD CS +VA AGND AGND +VA REFM REFM NC – No connection 7 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 TERMINAL FUNCTIONS NAME AGND BDGND NO. I/O 5, 8, 11, 12, 14, 15, 44, 45 – Analog ground DESCRIPTION 25, 35 – Digital ground for bus interface digital supply BUSY 36 O Status output. High when a conversion is in progress. BYTE 39 I Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[7:0] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[15:8]. CONVST 40 I Convert start CS 42 I Chip select 8-Bit Bus D t B Data Bus BYTE = 0 16-Bit Bus BYTE = 1 BYTE = 0 DB15 16 O D15 (MSB) D7 D15 (MSB) DB14 17 O D14 D6 D14 DB13 18 O D13 D5 D13 DB12 19 O D12 D4 D12 DB11 20 O D11 D3 D11 DB10 21 O D10 D2 D10 DB9 22 O D9 D1 D9 DB8 23 O D8 D0 (LSB) D8 DB7 26 O D7 All ones D7 DB6 27 O D6 All ones D6 DB5 28 O D5 All ones D5 DB4 29 O D4 All ones D4 DB3 30 O D3 All ones D3 DB2 31 O D2 All ones D2 DB1 32 O D1 All ones D1 DB0 33 O D0 (LSB) All ones D0 (LSB) –IN 7 I Inverting input channel +IN 6 I Non inverting input channel NC 3 – No connection REFIN 1 I Reference input REFM 47, 48 I Reference ground REFOUT 2 O Reference output. Add 1 µF capacitor between the REFOUT pin and REFM pin when internal reference is used. RESET 38 I Current conversion is aborted and output latches are cleared (set to zeros) when this pin is asserted low. RESET works independantly of CS. RD 41 I Synchronization pulse for the parallel output. +VA 4, 9, 10, 13, 43, 46 – Analog power supplies, 5-V dc 24, 34, 37 – Digital power supply for bus +VBD 8 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 TIMING DIAGRAMS tw2 tw1 CONVST tpd1 tpd2 tw4 tw3 BUSY tsu1 CS CONVERT† t(CONV) t(CONV) SAMPLING† (When CS Toggle) t(ACQ) BYTE th1 tsu2 tpd4 th2 td1 RD tdis ten DB[15:8] Hi–Z Hi–Z D [15:8] DB[7:0] Hi–Z D [7:0] Hi–Z D [7:0] †Signal internal to device Figure 1. Timing for Conversion and Acquisition Cycles With CS and RD Toggling 9 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 tw1 tw2 CONVST tpd1 tpd2 tw4 tw3 BUSY tsu1 CS CONVERT† t(CONV) t(CONV) SAMPLING† (When CS Toggle) t(ACQ) BYTE th1 tpd4 th2 RD = 0 ten DB[15:8] DB[7:0] Hi–Z Hi–Z tdis D [15:8] D [7:0] D [7:0] Hi–Z Hi–Z †Signal internal to device Figure 2. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND 10 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 tw1 tw2 CONVST tpd1 tpd2 tw4 tw3 BUSY CS = 0 CONVERT† t(CONV) t(CONV) t(ACQ) SAMPLING† (When CS = 0) BYTE th1 tpd4 th2 RD tdis ten DB[15:8] DB[7:0] Hi–Z Hi–Z D [15:8] D [7:0] D [7:0] Hi–Z Hi–Z †Signal internal to device Figure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling 11 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 tw2 tw1 CONVST tpd1 tpd2 tw4 tw3 BUSY CS = 0 CONVERT† t(CONV) t(CONV) t(ACQ) SAMPLING† (When CS = 0) BYTE th1 RD = 0 th1 tdis td3 td5 DB[15:8] Previous D [7:0] Next D [15:8] D [7:0] D [15:8] DB[7:0] Next D [7:0] D [7:0] †Signal internal to device Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND—Auto Read CS RD BYTE ten tdis tdis ten DB[15:0] td3 Hi–Z Valid Hi–Z Valid Valid Figure 5. Detailed Timing for Read Cycles 12 Hi–Z ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 TYPICAL CHARACTERISTICS† SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE HISTOGRAM (DC Code Spread) NEAR FULL SCALE 98304 CONVERSIONS 86.4 40000 +VA = 5 V, Code = 65260 30000 25000 20000 15000 10000 86 85.8 85.6 85.4 85.2 5000 85 –10 Figure 6 65264 65260 65255 0 20 35 50 65 TA – Free-Air Temperature – °C 93.3 SFDR – Spurious Free-Dynamic Range – dB fi = 100 kHz (+IN– –IN) = Full Scale 85.2 85 84.8 84.6 84.4 5 20 35 50 65 TA – Free-Air Temperature – °C Figure 8 80 SPURIOUS FREE-DYNAMIC RANGE vs FREE-AIR TEMPERATURE 85.4 84.2 –10 5 Figure 7 SIGNAL-TO-NOISE PLUS DISTORTION vs FREE-AIR TEMPERATURE SINAD – Signal-To-Noise Plus Distortion – dB fi = 100 kHz (+IN– –IN) = Full Scale 86.2 SNR – Signal-To- Noise Ratio – dB 35000 80 fi = 100 kHz (+IN– –IN) = Full Scale 93.2 93.1 93 92.9 92.8 92.7 92.6 92.5 92.4 92.3 92.2 –40 –20 0 20 40 60 80 TA – Free-Air Temperature – °C Figure 9 † At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted) 13 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE 87.2 fi = 100 kHz (+IN– –IN) = Full Scale –92.3 TA = 25°C (+IN– –IN) = Full Scale 87 SNR – Signal-To- Noise Ratio – dB THD – Total Harmonic Distortion – dB –92.2 –92.4 –92.5 –92.6 –92.7 –92.8 –92.9 –93 –93.1 86.8 86.6 86.4 86.2 86 –93.2 –93.3 –40 –25 85.8 –10 5 20 35 50 65 0 80 20 TA – Free-Air Temperature – °C Figure 10 60 80 100 40 60 80 fi – Input Frequency – kHz 100 Figure 11 ENOB vs INPUT FREQUENCY SIGNAL-TO-NOISE PLUS DISTORTION vs INPUT FREQUENCY 14.2 87 TA = 25°C (+IN– –IN) = Full Scale 86.8 14.15 86.6 14.1 86.4 ENOB – Bits SINAD – Signal-To-Noise Plus Distortion – dB 40 fi – Input Frequency – kHz 86.2 86 85.8 85.6 14.05 14 13.95 13.9 85.4 13.85 85.2 13.8 85 0 20 40 60 fi – Input Frequency – kHz Figure 12 80 100 0 20 Figure 13 † At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted) 14 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY SPURIOUS FREE-DYNAMIC RANGE vs INPUT FREQUENCY –92 TA = 25°C (+IN– –IN) = Full Scale 104 THD – Total Harmonic Distortion – dB SFDR – Spurious Free-Dynamic Range – dB 106 102 100 98 96 –94 –96 –98 –100 –102 TA = 25°C (+IN– –IN) = Full Scale –104 94 –106 92 0 20 40 60 80 100 0 20 fi– Input Frequency – kHz 40 60 80 fi – Input Frequency – kHz 100 Figure 15 Figure 14 GAIN ERROR vs SUPPLY VOLTAGE SUPPLY CURRENT vs SAMPLE RATE 31.5 TA = 25°C Current of +VA only 0.022 30.5 EG – Gain Error – %FS I CC – Supply Current – mA 31 30 29.5 29 28.5 0.019 0.017 0.014 28 TA = 25°C External Reference = 4.096 V (REFIN) 27.5 27 250 500 750 1000 Sample Rate – KSPS Figure 16 1250 0.012 4.75 4.85 4.95 5.05 5.15 +VA – Supply Voltage – V 5.25 Figure 17 † At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted) 15 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 INTERNAL REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE OFFSET ERROR vs SUPPLY VOLTAGE 4.104 Vref – Internal Reference Voltage – V 0.14 EO – Offset Error – mV 0.12 0.10 0.08 0.06 0.04 0.02 0 4.75 TA = 25°C External Reference = 4.096 V (REFIN) 4.85 4.95 5.05 5.15 +VA – Supply Voltage – V 5.25 4.100 4.096 4.092 4.088 4.084 –40 –25 –10 5 20 35 50 65 80 TA – Free-Air Temperature – °C Figure 19 Figure 18 OFFSET ERROR vs FREE-AIR TEMPERATURE GAIN ERROR vs FREE-AIR TEMPERATURE 0.028 0.30 External Reference = 4.096 V (REFIN) 0.25 EO – Offset Error – mV EG – Gain Error – %FS 0.024 0.019 0.014 0.009 0.004 0 –40 0.20 0.15 0.10 External Reference = 4.096 V (REFIN) 0.05 –25 –10 5 20 35 50 65 TA – Free-Air Temperature – °C Figure 20 80 0 –40 –25 –10 5 20 35 50 65 80 TA – Free-Air Temperature – °C Figure 21 † At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted) 16 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 DIFFERENTIAL NONLINEARITY (MAX) vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 1.24 DNL – Differential Nonlinearity (Max) – LSB I CC – Supply Current – mA 31.4 31.2 31.0 30.8 External Reference = 4.096 V (REFIN) Current of +VA Only 30.6 –40 –25 –10 5 20 35 50 65 TA – Free-Air Temperature – °C External Reference = 4.096 V (REFIN) 1.20 1.16 1.12 1.08 1.04 1 –40 80 –25 –10 Figure 22 35 50 65 80 INTEGRAL NONLINEARITY (MAX) vs FREE-AIR TEMPERATURE 2 INL – Integral Nonlinearity (MAX) – LSB –0.72 DNL – Differential Nonlinearity (MIN) – LSB 20 Figure 23 DIFFERENTIAL NONLINEARITY (MIN) vs FREE-AIR TEMPERATURE –0.76 –0.80 –0.84 External Reference = 4.096 V (REFIN) –0.88 –40 5 TA – Free-Air Temperature – °C –25 –10 5 20 35 50 65 TA – Free-Air Temperature – °C Figure 24 80 1.6 1.2 0.8 0.4 External Reference = 4.096 V (REFIN) 0 –40 –25 –10 5 20 35 50 65 80 TA – Free-Air Temperature – °C Figure 25 † At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted) 17 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 INTEGRAL NONLINEARITY (MIN) vs FREE-AIR TEMPERATURE INTEGRAL NONLINEARITY vs REFERENCE VOLTAGE 5 +VA = +VBD = 5 V, TA = 25°C 4 INL – Integral Nonlinearity – LSB INL – Integral Nonlinearity (MIN) – LSB –2 –2.4 –2.8 –3.2 –3.6 –25 –10 5 20 35 50 65 TA – Free-Air Temperature – °C Max 2 1 0 –1 Min –2 –3 External Reference = 4.096 V (REFIN) –4 –40 3 80 –4 2.0 2.5 3.0 3.5 4.0 4.5 Vref – Reference Voltage – V Figure 26 Figure 27 DIFFERENTIAL NONLINEARITY vs REFERENCE VOLTAGE DNL – Differential Nonlinearity – LSB 3.0 +VA = +VBD = 5 V, TA = 25°C 2.5 2.0 Max 1.5 1.0 0.5 0.0 Min –0.5 –1.0 2.0 2.5 3.0 3.5 4.0 Vref – Reference Voltage – V 4.5 Figure 28 † At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted) 18 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 DNL – LSB DNL 1.2 1 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 –1.2 16384 0 32768 65536 49152 Code TA = 25°C, External Reference = 4.096 V (REFIN) Figure 29 INL INL – LSB 2.5 2 1.5 1 0.5 0 –0.5 –1 –1.5 –2 –2.5 16384 0 32768 49152 65536 Code TA = 25°C, External Reference = 4.096 V (REFIN) Figure 30 FFT SPECTRUM RESPONSE Magnitude – dB of Full Scale 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 0 100 32768 Points, fS = 1.25 MHz, Internal Reference = 4.096 V (REFIN), TA = 25°C, fi = 100 kHz, (+IN– –IN) = Full Scale 200 300 400 500 600 Frequency – kHz Figure 31 † At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted) 19 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 APPLICATION INFORMATION MICROCONTROLLER INTERFACING ADS8401 to 8-Bit Microcontroller Interface Figure 32 shows a parallel interface between the ADS8401 and a typical microcontroller using the 8-bit data bus. The BUSY signal is used as a falling-edge interrupt to the microcontroller. Analog 5 V 0.1 µF AGND 10 µF Ext Ref Input 0.1 µF 1 µF –IN +VA REFIN REFM AGND +IN Analog Input Micro Controller Digital 3 V GPIO ADS8401 CS BYTE GPIO P[7:0] DB[15:8] RD CONVST BUSY RD GPIO INT 0.1 µF BDGND BDGND +VBD Figure 32. ADS8401 Application Circuitry (using external reference) Analog 5 V 0.1 µF AGND 10 µF 0.1 µF AGND AGND REFM REFIN REFOUT +VA 1 µF ADS8401 Figure 33. Use Internal Reference 20 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 PRINCIPLES OF OPERATION The ADS8401 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The architecture is based on charge redistribution, which inherently includes a sample/hold function. See Figure 32 for the application circuit for the ADS8401. The conversion clock is generated internally. The conversion time of 610 ns is capable of sustaining a 1.25-MHz throughput. The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. REFERENCE The ADS8401 can operate with an external reference with a range from 2.5 V to 4.2 V. A 4.096-V internal reference is included. When internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN) with an 0.1 µF decoupling capacitor and 1 µF storage capacitor between pin 2 (REFOUT) and pins 47 and 48 (REFM) (see Figure 33). The internal reference of the converter is double buffered. If an external reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the capacitors of the CDAC during conversion. Pin 2 (REFOUT) can be left unconnected (floating) if external reference is used. ANALOG INPUT When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. The voltage on the –IN input is limited between –0.2 V and 0.2 V, allowing the input to reject small signals which are common to both the +IN and –IN inputs. The +IN input has a range of –0.2 V to Vref + 0.2 V. The input span (+IN – (–IN)) is limited to 0 V to Vref. The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8401 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (25 pF) to an 16-bit settling level within the acquisition time (150 ns) of the device. When the converter goes into the hold mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the +IN and –IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, the converter’s linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters should be used. Care should be taken to ensure that the output impedance of the sources driving +IN and –IN inputs are matched. If this is not observed, the two inputs could have different setting time. This may result in offset error, gain error and linearity error which varies with temperature and input voltage. DIGITAL INTERFACE Timing And Control See the timing diagrams in the specifications section for detailed information on timing signals and their requirements. The ADS8401 uses an internal oscillator generated clock which controls the conversion rate and in turn the throughput of the converter. No external clock input is required. Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8401 switches from the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal is important to the performance of the converter. The BUSY output is brought high after CONVST goes low. BUSY stays high throughout the conversion process and returns low when the conversion has ended. 21 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS when BUSY is low. Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus with the conversion. Reading Data The ADS8401 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST. This is 100 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should be attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is used for multiword read operations. BYTE is used whenever lower bits of the converter result are output on the higher byte of the bus. Refer to Table 1 for ideal output codes. Table 1. Ideal Input Voltages and Output Codes DESCRIPTION ANALOG VALUE FULL SCALE RANGE Least significant bit (LSB) Full scale Midscale Midscale – 1 LSB Zero DIGITAL OUTPUT STRAIGHT BINARY Vref Vref/65536 BINARY CODE HEX CODE Vref – 1 LSB Vref/2 1111 1111 1111 1111 FFFF 1000 0000 0000 0000 8000 Vref/2 – 1 LSB 0V 0111 1111 1111 1111 7FFF 0000 0000 0000 0000 0000 The output data is a full 16-bit word (D15–D0) on DB15–DB0 pins (MSB–LSB) if BYTE is low. The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15–DB8. In this case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on pins DB15–DB8, then bringing BYTE high. When BYTE is high, the low bits (D7–D0) appear on pins DB15–D8. These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity. DATA READ OUT BYTE DB15–DB8 DB7–DB0 High D7–D0 All one’s Low D15–D8 D7–D0 RESET RESET is an asynchronous active low input signal (that works independently of CS). Minimum RESET low time is 20 ns. Current conversion will be aborted no later than 50 ns after the converter is in the reset mode. In addition, all output latches are cleared (set to zero’s) after RESET. The converter goes back to normal operation mode no later than 20 ns after RESET input is brought high. The converter starts the first sampling period 20 ns after the rising edge of RESET. Any sampling period except for the one immediately after a RESET is started with the falling edge of the previous BUSY signal or the falling edge of CS, whichever is later. POWER-ON INITIALIZATION One RESET pulse followed by three conversion cycles must be given to the converter after powerup to ensure proper operation. The next pulse can be issued once both +VA and +VBD reach 95% of the minimum required value. 22 ADS8401 www.ti.com SLAS376B – DECEMBER 2002 – REVISED APRIL 2003 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8401 circuitry. As the ADS8401 offers single-supply operation, it is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. On average, the ADS8401 draws very little current from an external reference, as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor and a 1-µF storage capacitor are recommended from pin 1 (REFIN) directly to pin 48 (REFM). REFM and AGND should be shorted on the same ground plane under the device. The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog ground. Avoid connections which are close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry. As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. Power to the ADS8401 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible. See Table 2 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the 5-V supply, removing the high frequency noise. Table 2. Power Supply Decoupling Capacitor Placement POWER SUPPLY PLANE SUPPLY PINS CONVERTER ANALOG SIDE CONVERTER DIGITAL SIDE Pin pairs that require shortest path to decoupling capacitors (4,5), (8,9), (10,11), (13,15), (43,44), (45,46) (24,25), (34, 35) Pins that require no decoupling 12, 14 37 23 MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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