AFEDRI8201 SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 IF ADC Front End for AM/FM and HD Radios FEATURES DESCRIPTION D Interfaces To Texas Instruments DRIx50 HD The AFEDRI8201 implements the receive channel analog functions required for intermediate-frequency (IF) sampled AM/FM and HD digital radio receivers. It is designed to be used with TI’s DRIx50 digital baseband processor. The AFEDRI8201 is programmed by the DRIx50 for use in AM/FM and HD radio. The AFEDRI8201 oversamples the radio tuner IF output at speeds of up to 80MHz to reduce noise and improve dynamic range. The radio tuner output IF is typically 10.7MHz for AM or FM as well as 450kHz or 455kHz for AM, as desired. The AFEDRI8201 then mixes, filters, and decimates the signal to provide baseband I and Q output signals to the digital baseband processor. The AFEDRI8201 also includes a general-purpose 12-bit control digital-to-analog converter (DAC) to provide a gain control signal or other analog feedback to the tuner. Radio Baseband Processors D 12-Bit, 80MSPS ADC Reduces Noise and Improves Sensitivity D Typical SNR of 102dB in 3kHz Bandwidth D Programmable Input Range For Optimum Tuner Dynamic Range D D D D D D Integrated Digital Downconverter (DDC) − Quadrature Mixer, NCO, CIC Decimation Filter, And FIR Filters Mixer: 32-Bit Frequency and Phase Decimation Ratio: 32 to 4096 User-Programmable FIR Filters with 16-Bit Coefficients 12-Bit Auxiliary DAC Code Composer Module for Easy Software Generation SPI Control Interface The DRIx50 digital baseband device writes control register data as well as decimation filter coefficients to the AFEDRI8201 through the industry-standard SPI control interface. The baseband output signals are transported to the DRIx50 through a general-purpose, high-speed serial interface (TI’s Buffered Serial Ports, McBSP). APPLICATIONS D D D D This unit uses 3.3V analog and 1.8V digital power supplies. Typical power dissipation is 490mW. The digital I/O lines can be powered by a 3.3V supply. AM/FM and HD Radio Receivers IF Receive Channels Software Radios Narrowband Receivers IFP 12−Bit Pipeline ADC IFM DOUT0 Quadrature Mixer CIC Filter N FIR Filter 1 2 FIR Filter 2A 2 DOUT1 Data Interface D NCO FIR Filter 2B DFSO DCLK 2 DIN AUX Auxiliary DAC DFSI Voltage Reference REFM VCM REFP VGB Clock Interface MCLK Timing Generator MCLKB PWD SYNC RESET SPI Control Interface SCK MOSI MISO CS Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. Copyright 2003−2005, Texas Instruments Incorporated ! ! www.ti.com "#$%&' www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING AFEDRI8201 TQFP-48 PFB −40°C to +85°C DRI8201 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY AFEDRI8201PFBT Tape and Reel, 250 AFEDRI8201PFBR Tape and Reel, 2000 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) AFEDRI8201 UNIT AVDD −0.5 to 4.0 V DVDD −0.5 to 2.3 V IOVDD −0.5 to 3.6 V Voltage between AGND and DGND −0.3 to 0.5 V Voltage between AVDD and DVDD Digital inputs(2) −3.3 to 3.3 V −0.3 to DVDD + 0.3 V Digital data output −0.3 to DVDD + 0.3 V −40 to +85 °C Supply Voltage Range Operating free-air temperature range, TA Storage temperature range −55 to +125 °C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) Measured with respect to DGND. RECOMMENDED OPERATING CONDITIONS MIN Supplies and References UNIT −40 +85 °C Analog supply voltage range, AVDD 3.15 3.3 3.45 V Digital supply voltage range, DVDD 1.71 1.8 1.89 V Output driver supply voltage range, IOVDD 3.15 3.3 3.45 V Differential input voltage Sample rate, fS Differential input mode voltage input swing 2 MAX Operating free-air temperature range, TA Input common-mode voltage Clock Inputs: MCLK and MCLKB TYP Single-ended mode high-level input voltage, VIHC VCM V 2 VPP 5 80 MHz 0.4 3.3 V 2 V Single-ended mode low-level input voltage, VILC 0.8 V Clock pulse width high, tW(H) 5.625 6.25 ns Clock pulse width low, tW(L) 5.625 6.25 ns "#$%&' www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 AUXILIARY DAC CHARACTERISTICS All specifications at +25°C, AVDD = +3.3V, and DVDD = +1.8V, unless otherwise noted. PARAMETER CONDITIONS MIN Resolution Output voltage range UNIT bits Input code 0x000 0.0 V Input code 0xFFF 2.75 V 1 kΩ to 0.1% FSR 10 Offset µs ±1 % of FSR ±5 % of FSR ±0.5 LSB After correcting for gain and offset errors ±2 LSB Input code 0x400, AVDD = 3.15VDC to 3.45VDC 60 dB Gain error DC performance MAX 12 Output impedance Settling time TYP Differential nonlinearity, DNL Ensured monotonic Integral nonlinearity, INL Power-supply rejection ratio, PSRR RECEIVE CHANNEL CHARACTERISTICS All specifications at +25°C, fS = 80MSPS, AVDD = +3.3V, DVDD = +1.8V, IOVDD = +3.3V, Gain = 1, Decimation Ratio = 80, Internal Digital Filter Bandwidth = 284kHz, and Input Signal = 10.7MHz, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNIT Differential nonlinearity, DNL −0.0244 ±0.0122 +0.0244 %FSR Integral nonlinearity, INL −0.0244 ±0.012 +0.0244 %FSR DC Accuracy Input impedance 6.25 kΩ Offset error 3 mV Gain error 1 %FS Gain = 1 Full-scale input level (peak differential) 1.0 V Gain = 1.14 0.875 V Gain = 1.33 0.75 V Gain = 1.6 0.625 V Gain = 2.0 0.5 V Gain = 2.67 0.375 V Gain = 4.0 0.25 V Gain change settling time Number of samples to achieve rated accuracy 2 Samples Power-supply rejection ratio, PSRR AVDD = 3.15VDC to 3.45VDC 70 dB References Negative reference, VREFN 1.1 1.25 1.4 V Positive reference, VREFP 2.1 2.25 2.4 V Common-mode voltage, VCM 1.8 V 76 dBc 86 dBc 75 dB 74 dB 102 dB 2 ns 0.2 ps AC Performance Input 455kHz, −1dBFS Spurious-free dynamic range, SFDR Input 10.7MHz, −1dBFS 76 Input 455kHz, −1dBFS Signal-to-noise ratio, SNR Input 10.7MHz, −1dBFS 70 In 3kHz bandwidth, −1dBFS, 10.7MHz, 20kHz from fundamental Aperture delay Aperture uncertainty Power Supply Analog supply voltage, AVDD 3.15 3.3 3.45 V Digital supply voltage, DVDD 1.71 1.8 1.89 V Output driver supply voltage, IOVDD 3.15 3.3 3.45 V Normal operation 490 570 mW Power-down Power dissipation 20 mW Digital I/O supply current 7 mA Digital supply current 72 mA Analog supply current 103 mA 3 "#$%&' www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 AVDD AGND AVDD AVDD AGND AGND DGND DVDD IOGND IOVDD IOGND PWD PIN ASSIGNMENTS 48 47 46 45 44 43 42 41 40 39 38 37 AVDD 1 36 SYNC AGND 2 35 RESET IFP 3 34 DOUT1 IFM 4 33 DOUT0 AGND 5 32 DCLK VCM 6 AVDD 7 31 DFSO 30 DIN VREFN 8 29 DFSI VREFP 9 28 SCK AFEDRI8201 AVDD 10 27 MISO AGND 11 26 MOSI VBG 12 18 19 20 21 22 23 24 AVDD DGND DVDD IOGND IOVDD AGND 17 MCLKB AUX 16 MCLK 15 AGND 14 NC 13 AVDD 25 CS PIN DESCRIPTIONS 4 NAME PIN TYPE IFP 3 Input FUNCTION Positive IF input IFM 4 Input Negative IF input VCM 6 Output Common-mode voltage output VREFN 8 Output Negative reference voltage output VREFP 9 Output Positive reference Voltage output VBG 12 Output Bandgap voltage output AUX 14 Output Auxiliary DAC output MCLK 18 Input Master clock input MCLKB 19 Input Complementary master clock input CS 25 Input SPI chip select (active low) MOSI 26 Input SPI serial Input MISO 27 Output SPI serial output SCK 28 Input SPI serial clock DFSI 29 Input Data interface input frame sync DIN 30 Input Data interface input data DFSO 31 Output Data interface output frame sync DCLK 32 Output Data interface clock output DOUT0 33 Output Data interface filter 0 output data DOUT1 34 Output Data interface filter 1 output data RESET 35 Input Global reset (active low). Resets all registers to zero, except for FIR filters. SYNC 36 Input External sync PWD 37 Input Power-down: PWD = 1; normal operation: PWD = 0 AVDD 1, 7, 10, 13, 20, 45, 46, 48 Supply Analog supply (3.3V) AGND 2, 5, 11, 15, 17, 43, 44, 47 Ground Analog ground DVDD 22, 41 Supply Digital supply (1.5V to 1.8V) DGND 21, 42 Ground Digital ground IOVDD 24, 39 Supply Digital I/O supply (3.3V) IOGND 23, 38, 40 Ground Digital I/O ground NC 16 — Not connected "#$%&' www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 DIGITAL INTERFACE SPECIFICATIONS All specifications at +25°C, AVDD = 3.3V, DVDD = 1.8V, IOVDD = 3.3V, and maximum 20pF load, unless otherwise noted. PARAMETER CONDITIONS MIN MAX UNITS High-level input current, IIH VIH = 1.6V to 3.6V −10 TYP 10 µA Low-level input current, IIL VIL = 0V to 0.4V −10 10 µA High-level output voltage, VOH IOH = −50µA 0.8 × IOVDD Low-level output voltage, VOL IOL = 50µA V 0.2 × IOVDD 0.7 × IOVDD High-level input voltage, VIH V V 0.25 × IOVDD Low-level input voltage, VIL V DATA INTERFACE TIMING DCLK DFSO DOUT0 IA[15] DOUT1 IA[14] IB[15] t d1 IA[13] IB[14] td2 IA[12] IB[13] IB[12] td3 Figure 1. Output Data Interface TIming MAX UNITS DCLK to DFSO delay, td1 PARAMETER CONDITIONS −0.4 MIN TYP 3.2 ns DCLK to DOUT0 delay, td2 −0.2 2.5 ns DCLK to DOUT1 delay, td3 −0.2 2.5 ns DCLK DFSI DIN D[15] tsu1 D[14] D[13] D[12] tsu2 th1 th2 Figure 2. Input Data Interface TIming PARAMETER CONDITIONS MIN TYP MAX UNITS DFSI to DCLK setup time, tsu1 1.2 ns DFSI to DCLK hold time, th1 0.4 ns DIN to DCLK setup time, tsu2 1.0 ns DIN to DCLK hold time, th2 0.4 ns 5 "#$%&' www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 CONTROL INTERFACE TIMING SCK CS MOSI MISO tL tsu3 th3 tT t d4 tI Figure 3. Control Interface Timing PARAMETER CONDITIONS MIN Maximum SCK frequency TYP MAX UNITS 1 MHz CS leading time, tL Trailing CS to leading SCK 5.0 ns CS trailing time, tT Trailing SCK to leading CS 5.0 ns Leading CS to trailing CS 5.0 ns MOSI to SCK setup time, tsu3 5.0 ns MOSI to SCK hold time, th3 1.0 ns SCK to MISO delay time, td4 1.0 CS idle time, tI 6 8 ns "#$%&' www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 DETAILED DESCRIPTION The AFEDRI8201 consists of a general-purpose, 80MSPS, 12-bit analog-to-digital converter (ADC) with programmable input range, digital downconverter (DDC), and user programmable digital filters with 16-bit coefficients. It is designed to sample narrowband (up to 2.5MHz) IF signals and digitally mix, filter, and decimate the signals to baseband. The ADC integrates a programmable gain sample-and-hold amplifier that is variable over gains of 1x to 4x to change the full-scale input voltage range of the device from 1.0V peak to 0.25V peak. When the gain is changed, two sample periods may be needed for the output of the ADC to settle to the correct value. The DDC consists of a digital quadrature mixer followed by a CIC decimation filter and FIR filters (FIR1 and FIR2). The mixer frequency and initial phase are independently programmed by 32-bit control words. The quadrature mixer generates I and Q signals, each of which are decimated by the CIC filter. The CIC is a 5th-order Comb filter with a decimation factor that is programmable over a range of 8 to 1024. Each of the FIR filters adds an additional decimation factor of 2, for a total range of 32 to 4096. The I and Q signals generated by the quadrature mixer are then passed on to the first FIR filter (FIR1). This decimate-by-two FIR filter can implement even, odd, halfband, and arbitrary impulse responses. The length of the filter response is dependent on the decimation factor of the CIC filter and the FIR filter response type, up to a maximum of 62 taps. Coefficients for multiple filter responses may be stored in the coefficient memory (up to 64 unique coefficients may be stored); responses can be changed by changing a control register to point the filter to a different section of coefficient memory. Following FIR1 are two parallel decimate-by-two FIR filters (FIR2A and FIR2B). These filters are similar to FIR1, but have twice the data and coefficient memory and can therefore realize longer filter responses. The responses of the FIR2A and FIR2B can be different from each other (with some limitations). In addition, FIR2A and FIR2B can be optionally interleaved to form a single extra-long FIR filter that can realize up to 251 taps. Control register information, as well as decimation filter coefficients, are written to the AFEDRI8201 through the industry-standard SPI control interface. The baseband output signals are transported through a high-speed serial interface that is compatible with the TI C5x/C6x DSP buffered serial ports (McBSP). The AFEDRI8201 also contains a 12-bit auxiliary digital-to-analog converter (DAC) which can be used for a number of purposes, including tuner automatic gain control or frequency control. Input data for the DAC may be sent either from the DSP through the serial data port or from a microcontroller through the SPI control interface. 7 "#$%&' www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 CONTROL INTERFACE The AFEDRI8201 uses an SPI slave interface to read and write control data. Control data consists of eleven 16-bit control registers, as shown in Table 1, and three memory banks (see Table 2). The control registers are used to program all chip parameters. The memory banks store 16-bit FIR filter coefficient data. To read and write to control registers and memory banks, data is transferred by a 16-bit instruction followed by 16 bits of data. Memory bank read and write operations also support block transfer. Memory bank block transfer consists of a 16-bit instruction followed by multiple 16-bit data words. Table 1. Control Registers REGISTER ADDRESS DESCRIPTION 0 Data interface parameters DIV, MODE 1 NCO frequency (bits 0−15) 2 NCO frequency (bits 16−31) 3 NCO Initial Phase (bits 0−15) 4 NCO Initial Phase (bits 16−31) 5 CIC Filter Decimation Rate: DEC_RATE 6 CIC Filter Parameters: SCALE, SHIFT 7 First FIR Filter Parameters: BASE_ADDR, NCOEFF, MODE 8 Second FIR A Filter Parameters: BASE_ADDR, NCOEFF, MODE 9 Second FIR B Filter Parameters: BASE_ADDR, NCOEFF, MODE 10 Setup for the Second FIR 11 Auxiliary DAC: DAC_DATA 12 ADC Parameters: GAIN, PWD Table 2. Memory Banks MEMORY BANK ADDRESS DESCRIPTION SIZE 00 FIR Filter 1 Coefficients 64 Coefficients DATA MEMORY 62 Samples 01 FIR Filter 2A Coefficients 128 Coefficients 126 Samples 10 FIR Filter 2B Coefficients 128 Coefficients 126 Samples The SPI interface consists of four signals: a serial clock (SCK), an active-low chip select (CS), a serial data input (MOSI—Master Out, Slave In), and a serial data output (MISO—Master In, Slave Out). Data is transferred in groups of 32 bits. The first 16 bits are the instruction, which indicate: (1) if data is to be written or to be read; (2) if the data target is a control register or a memory bank; and (3) the address of the data target. The second 16 bits are the data transfer, which is input on MOSI for a write cycle or output on MISO for a read cycle. 8 "#$%&' www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 A single data word write cycle is shown in Figure 4. The cycle is initiated by the high-to-low transition of the CS line. 32 SCK pulses clock the instruction and the data into the MOSI line. Instructions and data are clocked in MSB first. The first 16 bits are the instruction; the second 16 bits are the data word. There are two possible single data word write cycle instructions: register write and memory write. The formats for these instructions are shown in Figure 5 and Figure 6. SCK CS MSB LSB MOSI MISO Instruction Data Figure 4. Single Data Word Control Interface Write Cycle for Registers or Memory 1 0 0 15 14 13 REG_ADDR 12 11 10 Don’t Care 9 8 7 6 5 4 3 2 1 0 2 1 0 Figure 5. Register Write Instruction Format 1 0 1 15 14 13 Don’t Care 12 11 MEM 10 9 MEM_ADDR 8 7 6 5 4 3 Figure 6. Memory Write Instruction Format In case RESET is applied, either wait at least three SCK clocks before applying CS, or execute a dummy read operation (either from a register or memory) in order to initialize the SPI interface correctly. The only information required for a register write is the 5-bit register address (REG_ADDR). For a memory write, the 2-bit memory select (MEM) and the 8-bit memory address (MEM_ADDR) are required (see Table 2). Following the 16-bit instruction, the 16-bit data word is clocked in, again MSB first. At the end of the write cycle this data word is written to the appropriate register or memory location in the AFE. 9 "#$%&' www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 The read cycle is illustrated in Figure 7. It is similar to the write cycle, except that instead of the data word being clocked into MOSI during the second half of the cycle, the data word is clocked out of MISO. The two data read instructions are similar to the corresponding data write instructions and are shown in Figure 8 and Figure 9. SCK CS MSB LSB MOSI MSB LSB MISO Instruction Data Figure 7. Single Data Word Control Interface Read Cycle for Registers or Memory 0 1 0 15 14 13 REG_ADDR 12 11 10 Don’t Care 9 8 7 6 5 4 3 2 1 0 2 1 0 Figure 8. Register Read Instruction Format 0 1 1 15 14 13 Don’t Care 12 11 MEM 10 9 MEM_ADDR 8 7 6 5 4 3 Figure 9. Memory Read Instruction Format Block transfers are supported for memory reading and writing. Multiple data words are transmitted following the memory read or write instruction for a block transfer. The data words are sequentially read from or written to RAM sequentially starting at the address contained in the instruction. The sequential RAM access terminates when the CS line goes high. Figure 10 shows a memory block read cycle. In the illustration, three successive memory locations are read starting at address N. The memory block write cycle is similar, except of course data is clocked into MOSI. SCK CS MSB LSB MSB LSB MISO Instruction Data (N) Data (N + 1) Data (N + 2) Figure 10. Block Memory Read Cycle Control Interface In all cases, the control interface is reset when CS goes high. If the final SCK is not received before CS goes high, then the cycle will end prematurely. For a read cycle, transfer of data will terminate; for a write cycle, no data will be written to register or memory. 10 "#$%&' www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 DATA INTERFACE The data interface consists of six signals: 1. serial data clock DCLKO; 2. output frame sync DFSO; 3. output data line DOUT0; 4. output data line DOUT1; 5. input frame sync DFSI; and 6. input data line DIN. The decimation filter outputs from the DDC (either IA and QA, or IA, QA, IB, and QB) are multiplexed onto the data outputs. The control DAC data is shifted into the data input. Control Register 0 programs the functionality of the data interface, as seen in Figure 11. 0 0 0 0 0 Register Address Don’t Care 15 14 13 12 11 10 9 DIV 8 7 6 5 4 3 2 MODE 1 0 Figure 11. Data Interface Control Register Two parameters, DIV and MODE, control the data interface and are programmed by register 0. The first parameter is DIV. The serial data clock, DCLKO, is derived from MCLK in a manner controlled by DIV such that the frequency of DCLKO is: f DCLKO + f MCLK 2 DIV (1) where DIV ranges from 0 to 3. As an example, if MCLK is 80MHz, DCLK0 can be either 80MHz, 40MHz, 20MHz, or 10MHz. DCLK0, of course, must be fast enough to clock out the I and Q data words generated by the on-chip DDC and filters. The second parameter is MODE. When MODE is 0, all four DDC outputs are time multiplexed onto DOUT0, as shown in Figure 12. When MODE is 1, IA and QA outputs are multiplexed onto DOUT0 while IB and QB outputs are multiplexed onto DOUT1, see Figure 13. If only one set of I/Q outputs is used, MODE 1 is recommended so that data is output through DOUT0. DCLKO DFSO MSB DOUT0 LSB IA QA IB QB DOUT1 DFSI MSB DIN LSB DAC Figure 12. Data Interface Timing for MODE = 0 11 "#$%&' www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 DCLKO DFSO MSB DOUT0 LSB IA QA IB QB MSB DOUT1 LSB DFSI MSB LSB DIN DAC Figure 13. Data Interface Timing for MODE = 1 When the data interface receives new outputs from the decimation filters, an output cycle is started by asserting DFSO for one DCLKO period. On successive leading edges of DCLKO, the filter output data is shifted out MSB first on DOUT0 (and DOUT1 for MODE = 1), as shown in the timing diagrams. The spacing of the DFSO pulses depends on two settings: the overall decimation ratio R of the DDC and the factor DIV. The number of bits which need to be transmitted in one frame, NBITS, is 64 for MODE = 0 and 32 for MODE = 1. In order to have enough DCLKO cycles between DFSO pulses, the following relationship must be true: R w NBITS 2 DIV or DIV v log 2 R Ǔ ǒNBITS (2) (3) For example, assume the overall decimation ratio, R, for the DDC is 80. For MODE = 0, the largest allowable value for DIV is 0. In other words, if MCLK is 80MHz, for R = 80, DCLKO must be 80MHz so that all of the 64 data bits may be clocked out before the next I and Q data words must be clocked out. For MODE = 1, since only 32 bits need to be clocked out during one cycle, DCLKO can be reduced to 40MHz (which means that DIV may be increased to 1, cutting the frequency of DCLKO in half). DFSI and DIN are used to send control DAC data to the AFEDRI8201. DCLKO supplied by the AFEDRI8201 is used as the serial clock. An input cycle is initiated by holding DFSI high through one rising edge of DCLKO. On the successive 16 leading edges of DCLKO the input data word is read in serially, MSB first. The lower 12 bits of the data word are sent to the DAC as the unsigned DAC input. Note that the input data does not need to bear any timing relationship to the output data, except that both data streams are synchronous with DCLKO. QUADRATURE MIXER/NCO The NCO frequency and initial phase are set by the 32-bit unsigned variables FREQ and PHASE. Each of these variables is set via a pair of control registers; see Figure 14. The I and Q outputs of the mixer are given by: I + ADC Q + ADC sin(2pft ) f) and cos(2pft ) f) (4) (5) where ADC is the output of the IF analog-to-digital converter, f is the NCO frequency given by: FREQ 2 32 (6) PHASE 232 (7) f + f MCLK and φ is the NCO phase offset (in radians) given by: f + 2p 12 "#$%&' www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 MSB 0 0 0 0 1 Register Address 0 0 0 1 0 0 1 0 1 0 15 14 13 12 11 10 9 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 PHASE[15:0] 15 14 13 12 11 10 9 0 Register Address 8 FREQ[31:16] 1 Register Address 0 FREQ[15:0] 0 Register Address 0 LSB 8 7 PHASE[31:16] 15 14 13 12 11 10 9 8 7 Figure 14. Mixer Control Registers The SYNC pin can be used to externally control the phase of the mixer. While the SYNC pin is high, the phase accumulator is held to a constant value PHASE, essentially holding t to zero in the I and Q equations. When the SYNC pin is brought low, the phase accumulator is incremented by the value FREQ once per MCLK cycle. Note that the mixer can be bypassed by setting FREQ and PHASE to 0 and using only the Q (real) output. CIC FILTER The first stage of decimation filtering is provided by a 5th-order CIC filter. The operation of the CIC filter is controlled by the unsigned variable DEC_RATE, SCALE, and SHIFT which are mapped into control registers as illustrated in Figure 15. The valid range for DEC_RATE is from 8 to 1024. 0 0 1 0 1 Register Address 0 0 1 1 15 0 Register Address DEC_RATE Don’t Care 14 13 12 11 10 Don’t Care 15 14 13 9 8 7 6 5 4 3 SCALE 12 11 10 9 8 2 1 0 2 1 0 SHIFT 7 6 5 4 3 Figure 15. CIC Filter Control Registers The inherent dc gain of the CIC filter is DEC_RATE5. The control variables SHIFT and SCALE are used to reduce this very high gain before the signal is output to the next stage of decimation filter. The combined effect of DEC_RATE, SHIFT, and SCALE produces an overall dc gain for the CIC filter of: Gain + DEC_RATE 5 ǒ Ǔ Scaleń32 2 shift (8) In general, SHIFT and SCALE should be chosen to make GAIN as close to 1 as possible. For example, if DEC_RATE is 20, setting SHIFT to 22 and scale to 41 will result in a GAIN of 0.9775. 13 "#$%&' www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 FIRST FIR FILTER The block following the CIC filter is a decimate-by-two FIR filter with programmable coefficients. MODE sets the type of filter response—ODD (MODE = 00: symmetric impulse response, odd number of taps), EVEN (MODE = 01: symmetric impulse response, even number of taps), HALFBAND (MODE = 10), and ARBITRARY (MODE = 11: non-symmetric impulse response). The 16-bit wide filter coefficients are stored in memory bank 0. Up to 64 coefficients can be stored in this memory. Depending on the types of filters desired and the number of taps, coefficients for multiple filter responses may be stored in the memory bank. The filter response may be changed simply by updating the control register with new values for MODE, NCOEFF, and BASE_ADDR, as shown in Figure 16. 0 0 1 1 1 Register Address Don’t Care 15 14 BASE_ADDR 13 12 11 10 NCOEFF 9 8 7 6 5 4 MODE 3 2 1 0 Figure 16. First FIR Filter Control Register NCOEFF defines the number of unique filter coefficients which make up the filter response. BASE_ADDR defines the memory location where the first filter coefficient is stored. The actual filter length is a function of MODE and NCOEFF: Filter length = 2(NCOEFF − 1) + 1 for ODD Filter length = 2NCOEFF for EVEN Filter length = 4(NCOEFF − 1) + 1 for HALFBAND Filter length = NCOEFF for ARBITRARY The maximum filter length which can be realized is limited by two factors. First, the number of clock cycles between successive filter outputs limits the number of coefficients which can be processed to: NCOEFF v 2 DEC_RATE * 4 (9) where DEC_RATE is the decimation ration of the CIC filter. Second, the size of the data memory (which stores incoming data samples) limits filter length to 62 taps. A filter response is defined by a set of NCOEFF 16-bit filter coefficients stored in memory bank 0 (MEM = 0) starting at address BASE_ADDR. MODE determines how the coefficients are applied to the samples stored in data memory. Figure 17 is an example illustrating how the filter coefficients are applied to stored input samples in the various filter modes with NCOEFF = 6. Because NCOEFF = 6 in this example, six computation cycles are required to calculate the filter output regardless of the filter mode. The leftmost grouping in Figure 17 represents the six filter coefficients stored at ascending memory address in the coefficient memory starting at BASE_ADDR. At each computation cycle, the coefficient being applied to the input data is highlighted. The leftmost grouping in Figure 17 represents the six filter coefficients stored at ascending memory address in the coefficient memory starting at BASE_ADDR. At each computation cycle, the coefficient being applied to the input data is highlighted. The four groupings on the right in Figure 17 represent the four filter modes: EVEN, ODD, HALFBAND, and ARBITRARY. In each column, the locations in data memory that are operated on at each computation cycle is shown. The leftmost data sample in each group is the newest sample, the rightmost sample is the oldest. The chart illustrates the order in which computation on data occurs. To use the chart, select the filter mode of interest, then move down the chart through the six computation cycles to understand the sequence of calculations. 14 B A SE _A DD R+5 N B A SE_ A DD R+3 B A SE_ A DD R+4 B A SE_ A DD R+5 BAS E _AD DR +3 BAS E _AD DR +4 BAS E _AD DR +5 BA S E_A DD R N +8 N +9 N+ 2 N+ 3 N+ 4 N+ 5 N+ 6 N+ 7 N+ 8 N +2 N +3 N +4 N +5 N +6 N +7 N +8 N+9 N +1 0 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N +10 N +11 N +12 N +13 N +14 N +15 N +16 N +17 N +18 N +9 N+ 10 N N +1 N +2 N +3 N +4 N +5 N +6 N +7 N +8 N +9 N+1 0 N+1 1 N+1 2 N+1 3 N+1 4 N+1 5 N+1 6 N+1 7 N+1 8 N+ 4 N+ 5 N+8 N +8 N+ 3 N+7 N +7 N+4 N+5 N+6 N +6 N+3 N N+5 N +5 N +4 N +5 N +3 N +1 N +2 N+1 7 N+1 6 N+1 5 N+1 4 N+1 3 N+1 2 N+1 1 N+1 0 N +8 N +9 N +7 N +6 N +5 N +4 N +2 N +3 N N +1 N +1 0 N+9 N+8 N+7 N+6 N+5 N+3 N+4 N+2 N +4 N +5 N +3 N +1 N +2 N N+ 18 N+ 17 N+ 16 N+ 15 N+ 14 N+ 13 N+ 12 N+ 11 N+ 10 N +8 N +9 N +7 N +6 N +5 N +4 N +2 N +3 N N +1 N+10 N +9 N +8 N +7 N +6 N +5 N +3 N +4 N +2 N +4 N +5 N +3 N +1 N +2 N N +1 8 N +1 7 N +1 6 N +1 5 N +1 4 N +1 3 N +1 2 N +1 1 N +1 0 N+ 8 N+ 9 N+ 7 N+ 6 N+ 5 N+ 4 N+ 2 N+ 3 N N+ 1 N +1 0 N+ 9 N+ 8 N+ 7 N+ 6 N+ 5 N+ 3 N+ 4 N+ 2 N N+ 1 N+4 N+5 N+3 N+1 N+2 N N +1 8 N +1 7 N +1 6 N +1 5 N +1 4 N +1 3 N +1 2 N +1 1 N +1 0 N+8 N+9 N+7 N+6 N+5 N+4 N+2 N+3 N N+1 N +10 N+9 N+8 N+7 N+6 N+5 N+3 N+4 N+2 N N+1 N +11 N +10 N+9 N+8 N+6 N+7 N+4 N+5 N+3 HALFBAND N N+3 N+4 N +3 N +4 N N +1 N +1 1 N N+2 N+1 ODD N+ 1 N+ 2 N+2 N +2 N N+1 N+ 11 N +1 0 N+ 9 N+ 8 N+ 6 N+ 7 N+ 4 N+ 5 N+ 3 N+ 2 N+ 1 EVEN N N N+1 N N +1 N +1 1 N+ 10 N +9 N +8 N +6 N +7 N +4 N +5 N +3 N +2 N +1 N B AS E _AD D R+5 B AS E _AD DR +5 N B ASE _ AD DR +4 B AS E _AD D R+4 B ASE _ AD DR +5 B ASE _ AD DR +3 B AS E _AD D R+3 B AS E _AD DR +4 B ASE _ AD DR +2 B AS E _AD D R+2 B AS E _AD DR +3 BAS E_ AD DR B ASE _ AD DR +1 BA S E_A DD R B AS E _AD D R+1 B A S E_A D DR 3 B AS E _AD DR +2 2 B AS E _AD DR +1 COEFFICIENT BANK N+1 N+2 N+1 8 N +1 1 N+ 11 N +1 0 N+ 9 N +1 0 N +9 N+ 10 N +6 N +7 N +4 N +5 N +3 N +2 N +1 N N+ 1 N N +1 B A SE _A DD R+4 B A SE _A DD R+3 B A SE _A DD R+2 B A SE _A DD R+1 B ASE _A DD R B A SE_ A DD R+2 6 B A SE_ A DD R+1 5 BA SE _A D DR 1 BAS E _AD DR +2 COMPUTATION CYCLE BAS E _AD DR +1 "#$%&' www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 FILTER PROCESSING ARBITRARY 4 Figure 17. Application of Filter Coefficients in Different Filter Modes 15 "#$%&' www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 For example, using the ODD mode in the first cycle of MCLK, the filter coefficient at BASE_ADDR is applied to two values in data memory, the most recent at address N and the oldest at address N+10. In the next cycle of MCLK the coefficient at BASE_ADDR+1 is applied to the data values at N+1 and N+9, and so on until the last coefficient at BASE_ADDR+5 is reached. Because this is an odd filter, the final coefficient is applied only to the data value at address N+5. The full cycle is shown in Table 3. Table 3. ODD Mode Calculation Example with Six Filter Coefficients CYCLE FILTER COEFFICIENT ADDRESS APPLIED TO DATA ADDRESS 1 BASE_ADDR N and N+10 2 BASE_ADDR+1 N+1 and N+9 3 BASE_ADDR+2 N+2 and N+8 4 BASE_ADDR+3 N+3 and N+7 5 BASE_ADDR+4 N+4 and N+6 6 BASE_ADDR+5 N+5 Figure 17 clearly illustrates that the overall filter length is different in different filter modes even if NCOEFF is unchanged. For NCOEFF = 6, filter length ranges from 6 taps for ARBITRARY mode to 19 taps for HALFBAND mode. The dc gain of the FIR filter depends on the coefficient values and the filter mode. For ODD mode and for HALFBAND mode, the dc gain is given by: GAIN + ǒ NCOEFF * 1 h NCOEFF ) S 2hn n + 1 Ǔń ǒ2 15 * 1Ǔ (10) where hn is the nth of NCOEFF filter coefficients stored in memory. For EVEN mode the dc gain is: ǒ S Ǔń NCOEFF GAIN + n + 1 ǒ215 * 1Ǔ 2h n (11) while for ARBITRARY mode the gain is: ǒ S Ǔń NCOEFF GAIN + 16 n + 1 hn ǒ215 * 1Ǔ (12) "#$%&' www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 SECOND FIR FILTER The second FIR filter, shown in Figure 18, is similar to the first FIR filter with four notable exceptions. 1. The depth of the coefficient and data memories are doubled to 128. This allows for filters up to 126 taps to be realized without running out of data memory. It also allows longer sets of filter coefficients to be stored in coefficient memory. Note that BASE_ADDR and NCOEFF are each one bit wider in the control register. 2. Because of the additional decimation by two from the first FIR filter, twice as many MCLK cycles are available to process coefficients, increasing the maximum allowable value of NCOEFF to: NCOEFF v 4 DEC_RATE * 4 (13) 3. In the first FIR filter, the total of all the filter tap weights must add up to 215 − 1 in order to achieve unity gain through the filter. With longer filters (and thus smaller coefficients), frequency response errors may be introduced because of coefficient truncation. A shift parameter has been added to the second FIR filter to alleviate this problem. The total of all filter tap weights must add up to 215+SHIFT − 1 to achieve unity gain through FIR2A or FIR2B. Note that shift values for FIR2A and FIR2B can be set separately. 4. A second coefficient memory and computational unit is added to allow the simultaneous implementation of two filters with differing responses acting on the same input data stream. Coefficients for filter A are stored in memory bank 1 (MEM = 1) and coefficients for filter B are stored in memory bank 2 (MEM = 2). Note that while the coefficient values for filter A and filter B can be different, the two filters share the same values for MODE, NCOEFF, and BASE_ADDR. 0 1 0 0 0 Register Address 0 1 0 0 1 0 1 15 14 1 Register Address 0 BASE_ADDR_A 13 11 10 9 8 7 6 BASE_ADDR_B 15 14 13 0 Register Address 12 NCOEFF_A 12 11 14 13 12 10 9 8 7 M2X 11 4 3 2 NCOEFF_B Don’t Care 15 5 MODE_A 10 9 8 6 5 6 5 0 MODE_B 4 3 SHIFT_B 7 1 2 1 0 SHIFT_A 4 3 2 1 0 Figure 18. Second FIR Filter Control Register EXTENDED-LENGTH FILTER MODE If FIR2A or FIR2B cannot provide enough filter taps to achieve the desired frequency response, setting control bit M2X to ‘1’ will put the two filters into an interleaved mode, which will double the length of filter which can be realized. The limitations are: 1. only odd symmetrical filters may be realized; 2. the filter length M must be such that (M + 1)/4 is an integer; and 3. only one filter can be realized (in M2X mode the A and B outputs are identical: IB = IA and QB = QA). In addition to setting the M2X bit to ‘1’, FIR2A must be set to EVEN mode and FIR2B must be set to ODD mode. NCOEFF_A and NCOEFF_B are both set to (M+1)/4. SHIFT_A and SHIFT_B should be identical. There are no restrictions on BASE_ADDR_A or BASE_ADDR_B. The M-tap filter will have (M+1)/2 unique coefficients. The first, third, fifth, etc. coefficients are loaded into the FIR2A coefficient memory; the second, fourth, sixth, etc. are loaded into the FIR2B memory. The center coefficient of the filter will end up as the last coefficient loaded into FIR2B. 17 "#$%&' www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 AUXILIARY DAC In normal operation the auxiliary DAC values are sent over the data interface through input pin DIN and framed by DFSI. The auxiliary DAC control register, shown in Figure 19, allows the DAC value to be set through the control interface as an alternative. A new DAC value through either interface will cause the DAC output to change, regardless of which interface set the previous DAC value. Please note, however, that unpredictable results will occur if both interfaces write to the DAC at the same time. 0 1 0 1 1 Register Address Don’t Care 15 14 13 DAC_DATA 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 19. Auxiliary DAC Control Register PGA AND POWER-DOWN The gain of PGA and the power-down mode can be set in register 12. The gain setting of the PGA is shown in Table 4. Table 4. PGA Gain Setting PGA GAIN RANGE 3-BIT CODE (B4, B3, AND B2) 1.00 000 1.14 100 1.33 010 1.60 110 2.00 001 2.67 101 4.00 011 Bit 0 PWD = 0 for normal operation. PWD = 1 for power-down. 0 1 1 0 0 Register Address Don’t Care 15 14 13 12 11 10 GAIN 9 8 7 6 Figure 20. PGA and PWD Register 18 5 4 3 2 Don’t Care PWD 1 0 www.ti.com SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 AFEDRI8201 Revision History DATE REV PAGE 6 SECTION Control Interface Timing DESCRIPTION Changed Maximum SCK Frequency from 10MHz to 1MHz. Changed “16 bit” to “16-bit” (added hyphen) in last sentence of 2nd paragraph. 8 Control Interface 8/25/05 F Changed “16 bits is” to “16 bits are” in last paragraph. Changed 1st sentence of 4th paragraph to include additional info on initializing the SPI interface correctly. 9 13 Quadrature Mixer/NCO Changed “mixer” to “the mixer” in 1st sentence of 1st paragraph. 16 Control Interface Changed “mode” to “modes” in 1st sentence of 2nd paragraph. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 19 PACKAGE OPTION ADDENDUM www.ti.com 23-Aug-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty AFEDRI8201PFBR ACTIVE TQFP PFB 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR AFEDRI8201PFBT ACTIVE TQFP PFB 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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