® DAC600 DEMO BOARD AVAILABLE 12-Bit 256MHz Monolithic DIGITAL-TO-ANALOG CONVERTER FEATURES APPLICATIONS ● 12-BIT RESOLUTION ● 256MHz UPDATE RATE ● DIRECT DIGITAL SYNTHESIS ● ARBITRARY WAVEFORM GENERATION ● –73dB HARMONIC DISTORTION AT 10MHz ● LASER TRIMMED ACCURACY: 1/2LSB ● –5.2V SINGLE POWER SUPPLY ● HIGH RESOLUTION GRAPHICS ● COMMUNICATIONS LOCAL OSCILLATORS Spread Spectrum/Frequency Hopping Base Stations Digitally Tuned Receivers ● EDGE-TRIGGERED LATCH ● LOW GLITCH: 5.6pVs ● WIDEBAND MULTIPLYING REFERENCE INPUT ● 50Ω OUTPUT IMPEDANCE DESCRIPTION CLK CLK The DAC600 is a monolithic, high performance digital-to-analog converter for high frequency waveform generation. The internal segmentation and latching minimize output glitch energy and maximizes AC performance. Resistor laser trimming provides for excellent DC linearity. The DAC600 combines precision thin film and bipolar technology to create a high performance, cost effective solution for modern waveform synthesis. ROFFSET 12-Bit ECL Lines Edge Triggered Bit Latch The ECL compatibility provides for low digital noise at high update rates. The complementary 50Ω outputs and low output capacitance simplifies transmission line design and filtering at the output. VREF Control Amplifier –20mA VOUT VOUT 50Ω 50Ω LGND International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1992 Burr-Brown Corporation PDS-1153E Printed in U.S.A. November, 1996 SPECIFICATIONS ELECTRICAL At +25°C VREF = +1.0V, VEEA = VEED = –5.2V, unless otherwise noted. PARAMETER CONDITIONS DIGITAL INPUTS Logic Resolution ECL Logic Input Levels: VIL IIL VIH IIH CONTROL AMPLIFIER Input Resistance Full Power Bandwidth Offset Input Reference Range MIN Full Full Full Full –1.48 –1.95 –1.1 –0.75 Full Full Full Full Full DC 1.95 1.5 1.9 Full Full Full 19 47.5 MIN DAC600BN TYP MAX UNITS 12 Parallel Input Lines, ECL Logic “0” Logic “1” DIGITAL TIMING Input Data Rate CLK Pulse Width High or Low Set-up Time Hold Time (Referred to CLK) Propagation Delay ANALOG OUTPUT Bipolar Output Current Output Resistance Output Capacitance DAC600AN TYP MAX TEMP RL = 0Ω –3dB Full Full +25°C Full 12 –2 2 0 200 256 1.0 1.7 2 20 50 15 800 10 0 100mV 21 52.5 ±1 ±1.25 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ 49 ✻ ✻ ✻ ✻ ✻ Bits V µA V µA ✻ MHz ns ns ns ns ✻ 51 mA Ω pF ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ 0 ✻ ±0.5 ✻ Ω MHz mV V ±0.012 ±0.024 ±0.1 ±0.012 ±0.024 ±0.1% %FSR %FSR %FSR %FSR %FSR %FSR 100 100 ±1.0 ±2.0 50 µA µA % % µA TRANSFER CHARACTERISTICS Integral Linearity Error(1): VOUT NOT VOUT NOT VOUT Differential Linearity Error(1): VOUT NOT VOUT NOT VOUT 12-Bit Monotonicity Output Offset Current: VOUT NOT VOUT NOT Gain Error(2) Output Leakage Current TIME DOMAIN PERFORMANCE Glitch Energy Fall Time Rise Time Settling Time(3) ±0.1% FSR ±0.024% FSR DYNAMIC PERFORMANCE Spurious Free Dynamic Range (4) fO = 1MHz fO = 10MHz fO = 1MHz fO = 10MHz fO = 20MHz fO = 10MHz fO = 20MHz fO = 50MHz Output Noise POWER SUPPLIES Supply Voltages: VEE Supply Currents: IEEA IEED Power Consumption TEMPERATURE RANGE Specification: DAC600AN, BN θJA Best Fit Straight Line ±0.012 ±0.024 ±0.024 ±0.036 ±0.1 ±0.024 ±0.036 ±0.1% ±0.006 ±0.012 VREF = 0V, Bits 1-12 LOW, VOUT NOT +25°C Full +25°C +25°C Full +25°C +25°C Full +25°C Full +25°C Full +25°C Major Carry 90% to 10% 10% to 90% +25°C +25°C +25°C 5.6 510 770 ✻ ✻ ✻ pVs ps ps Major Carry, 1 LSB Change Full Full 4 15 ✻ ✻ ns ns fCLOCK = 50MHz fCLOCK = 50MHz fCLOCK = 100MHz fCLOCK = 100MHz fCLOCK = 100MHz fCLOCK = 200MHz fCLOCK = 200MHz fCLOCK = 200MHz Bits 1-12 HIGH +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C 74 71 72 68 61 66 58 52 10.6 70 64 70 66 58 66 62 50 77 73 75 70 62 70 67 55 ✻ dBFS(3) dBFS dBFS dBFS dBFS dBFS dBFS dBFS nV/√Hz Pins 33 and 34 Pins 5 and 55 Operating Full Full Full Full –4.5 30 110 –5.5 60 190 1.3 ✻ ✻ ✻ ✻ ✻ ✻ ✻ Ambient Full –40 +85 ✻ Bits 1-12 HIGH Guaranteed Typical 75 150 57 150 ±0.5 ±1.5 ±1.3 ±2.0 10 75 –5.2 46 150 900mW 30 Guaranteed Guaranteed 50 50 ±0.5 ±1.1 5 ✻ ✻ ✻ ✻ ✻ V mA mA W ✻ °C °C/W ✻ Same as specification for DAC600AN. V (FS) –VIDEAL (FS) X 100 NOTES: (1) Linearity tests are measured into a virtual ground (op amp). (2) Gain error in % is calculated by: GE (%) = MEASURED VIDEAL (FS) (3) Settling time is influenced by the load due to fast edge speeds. Use good transmission line techniques for best results. (4) Spurious free dynamic range is measured from the fundamental frequency to any harmonic or non-harmonic spurs within the bandwidth fCLK/2C, unless otherwise specified. ® DAC600 2 ELECTROSTATIC DISCHARGE SENSITIVITY ORDERING INFORMATION DESCRIPTION TEMPERATURE RANGE (AMBIENT) 68-Pin Plastic QUAD –40°C to +85°C PRODUCT DAC600AN, BN This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ABSOLUTE MAXIMUM RATINGS VEEA ............................................................................................ 0.3 to –7 VEED ............................................................................................ 0.3 to –7 Logic Inputs ................................................................................ 0 to –5.5V Reference Input Voltage .......................................................... 0 to +1.25V Reference Input Current ......................................................... 0 to 1.56mA Case Temperature .......................................................... –40°C to +125°C Junction Temperature .................................................................... +150°C Storage Temperature ...................................................... –55°C to +125°C Lead Temperature (soldering, 10s) ................................................ +300°C ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Stresses above these ratings may permanently damage the device. PACKAGE INFORMATION PACKAGE PACKAGE DRAWING NUMBER(1) 68-Pin Plastic QUAD 312-1 PRODUCT DAC600AN, BN NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. PIN DEFINITIONS PIN # DESIGNATION DESCRIPTION PIN # DESIGNATION DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 BYPASS CLK CLKNOT DGND DVEE(1) Bit 9 Bit 10 Bit 11 Bit 12 NC NC NC VOUT VOUT LGND LGND VOUTNOT VOUTNOT NC AGND NC NC NC NC NC BYPASS NC ALTCOMPIB AGND AGND NC LOOPCRNT Disables Latching of Data CLOCK CLOCKNOT Digital Ground –5.2V Supply VEE(1) VEE(1) VREF2 NC NC VREF VREF NC NC ROFFSET NC BYPASS NC NC ALTCOMPC AGND NC LBIAS NC NC NC Bit 1 DVEE DGND DGND Bit 2 Bit 3 Bit 4 NC Bit 5 DGND Bit 6 Bit 7 DGND Bit 8 NC Analog Reference Voltage Center Tap 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 LSB DAC Output DAC Output Ladder Ground Ladder Ground DAC Output Complement DAC Output Complement Analog Ground 0.1µF Bypass to Ground PTAT-IB Reference Compensation(2) Analog Ground Analog Ground DAC Reference Alt. Loop Current (Connect to AGND) –5.2V Supply –5.2V Supply Analog Reference Voltage Analog Reference Voltage Offset Compensation 0.1µF Bypass to Ground Control Amp PTAT Reference Compensation(2) Analog Signal Ground Ladder Bias Alternate Compensation(2) MSB Digital –5.2V Supply Digital Signal Ground Digital Signal Ground Digital Ground Digital Ground NC: no connect NOTE: (1) Pins 5 and 55 typically draw 150mA of current. Pins 33 and 34 combined typically draw 46mA. (2) Connect bypass capacitor to VEE. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 DAC600 DICE INFORMATION DAC600 DIE TOPOGRAPHY MECHANICAL INFORMATION Die Size Die Thickness Min. Pad Size MILS (0.001") MILLIMETERS 160 x 140 ±5 20 ±3 4x4 4.06 x 3.56 ±0.13 0.51 ±0.08 0.10 x 0.10 Backing Metallization FUNCTION PAD FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Bypass CLK CLKNOT DGND DVEE Bit 9 NC Bit 10 Bit 11 Bit 12 VOUT VOUT LGND LGND VOUTNOT VOUTNOT NC AGND NC NC NC NC NC NC NC NC ALTCOMPIB AGND AGND NC LOOPCRNT AVEE AVEE VREF2 NC 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 NC VREF VREF NC NC ROFFSET NC NC NC NC ALTCOMPC AGND NC LBIAS NC NC NC Bit 1 (MSB) DVEE DGND DGND Bit 2 Bit 3 Bit 4 NC NC NC Bit 5 DGND Bit 6 Bit 7 DGND Bit 8 NC Substrate Bias: Negative Supply –VCC. NC = Do not connect. Gold Gold ® DAC600 PAD 4 TYPICAL PERFORMANCE CURVES At TCASE = +25°C, VREF = +1.0V, measured at VOUT NOT. Spurious free dynamic range includes all harmonic or non-harmonic spurs in the bandwidth fCLK/2, unless otherwise noted. DIFFERENTIAL NON-LINEARITY (+85°C) 0.024 0.012 0.012 % of FSR % of FSR DIFFERENTIAL NON-LINEARITY (+25°C) 0.024 0.0 –0.012 0.0 –0.012 –0.024 –0.024 0 1000 2000 3000 4000 0 1000 Code 3000 4000 INTEGRAL NON-LINEARITY (+85°C) 0.024 0.048 0.012 0.024 % of FSR % of FSR DIFFERENTIAL NON-LINEARITY (–40°C) 0.0 –0.012 0.0 –0.024 –0.024 –0.048 0 1000 2000 3000 4000 0 1000 Code 2000 3000 4000 Code INTEGRAL NON-LINEARITY (+25°C) INTEGRAL NON-LINEARITY (–40°C) 0.048 0.048 0.024 0.024 % of FSR % of FSR 2000 Code 0.0 –0.024 0.0 –0.024 –0.048 –0.048 0 1000 2000 3000 4000 0 Code 1000 2000 3000 4000 Code ® 5 DAC600 TYPICAL PERFORMANCE CURVES (CONT) At TCASE = +25°C, VREF = +1.0V, measured at VOUT NOT. Spurious free dynamic range includes all harmonic or non-harmonic spurs in the bandwidth fCLK/2, unless otherwise noted. OUTPUT SPECTRUM AT fCLK = 128MHz, fO = 21.9MHz 0 0 –20 –20 Amplitude (dB) Amplitude (dB) OUTPUT SPECTRUM AT fCLK = 128MHz, fO = 11MHz –40 –60 –60 –80 –80 –100 –100 0 OUTPUT SPECTRUM AT fCLK = 128MHz, fOUT = 41.5MHz OUTPUT SPECTRUM AT fCLK = 256MHz, fO = 33.8MHz 48 64 0 0 –20 –20 –40 –60 –80 64 –40 –60 –80 –100 –100 0 16 32 (MHz) 48 64 0 OUTPUT SPECTRUM AT fCLK = 256MHz, fO = 55.3MHz 32 64 (MHz) 96 128 OUTPUT SPECTRUM AT fCLK = 256MHz, fO = 83.1MHz 0 0 –20 –20 Amplitude (dB) Amplitude (dB) 48 32 (MHz) 32 0 16 (MHz) 16 Amplitude (dB) Amplitude (dB) –40 –40 –60 –80 –40 –60 –80 –100 –100 0 32 64 (MHz) 96 128 0 ® DAC600 6 32 64 (MHz) 96 128 TYPICAL PERFORMANCE CURVES (CONT) At TCASE = +25°C, VREF = +1.0V, measured at VOUT NOT. Spurious free dynamic range includes all harmonic or non-harmonic spurs in the bandwidth fCLK/2, unless otherwise noted. SPURIOUS FREE DYNAMIC RANGE vs CLOCK FREQUENCY (fOUT ≈ 1/16 fCLOCK) SPURIOUS FREE DYNAMIC RANGE vs CLOCK FREQUENCY +80 Spurious Free Dynamic Range (dBc) Spurious Free Dynamic Range (dBc) +75 10MHz +70 +65 20MHz +60 50MHz +55 +50 +75 +70 +65 +60 +55 +45 0 50 100 150 200 fCLOCK (MHz) 250 300 0 350 HARMONIC DISTORTION vs CLOCK FREQUENCY (fOUT ≈ 1/3 fCLOCK) 50 100 150 200 fCLOCK (MHz) 250 300 350 3RD HARMONIC vs CLOCK FREQUENCY (fOUT ≈ 1/4 fCLOCK) –40 –48 Reflected 3rd Harmonic –52 3rd Harmonic (dBc) 2nd and 3rd Harmonic (dBc) –50 –45 –50 –55 –60 Reflected 2nd Harmonic –54 –56 –58 –60 –62 –65 –64 –70 –66 0 50 100 150 200 250 300 350 0 100 150 200 250 300 fCLOCK (MHz) SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY 350 +80 Spurious Free Dynamic Range (dBc) +80 Spurious Free Dynamic Range (dBc) 50 fCLOCK (MHz) +75 +70 50MHz +65 100MHz +60 200MHz 150MHz +55 150MHz +75 200MHz +70 +65 250MHz +60 +55 300MHz +50 +45 +50 0 10 20 30 fOUT (MHz) 40 50 0 60 10 20 30 40 50 60 fOUT (MHz) ® 7 DAC600 TYPICAL PERFORMANCE CURVES (CONT) At TCASE = +25°C, VREF = +1.0V, measured at VOUT NOT. Spurious free dynamic range includes all harmonic or non-harmonic spurs in the bandwidth fCLK/2, unless otherwise noted. SPURIOUS FREE DYNAMIC RANGE vs TEMPERATURE SPURIOUS FREE DYNAMIC RANGE vs TEMPERATURE –70 1MHz +72 –65 20MHz +70 Largest Spur (dBc) Spurious Free Dynamic Range (dBc) +74 +68 +66 +64 20MHz –55 50MHz –45 +60 –60 –40 –20 20 0 40 80 60 100 –60 –40 –20 20 40 60 80 Temperature (°C) REFERENCE VOLTAGE vs DISTORTION (fCLK = 128MHz, fOUT = 21.9MHz) HARMONIC DISTORTION vs REFERENCE VOLTAGE (fOUT ≈ 1/4 fCLOCK) 100 –56 3rd Harmonic 2nd and 3rd Harmonic (dBc) 3rd Harmonic –65 –66 –67 2nd Harmonic –68 –69 –70 0.75 –58 2nd Harmonic –60 –62 –64 –66 –68 0.80 0.85 0.90 VREF (V) 0.95 1.00 1.05 0.4 0.5 REFERENCE CONTROL AMPLIFIER FREQUENCY RESPONSE 0.6 0.7 0.8 VREF (V) 0.9 1.0 1.1 SPURIOUS FREE DYNAMIC RANGE vs REFERENCE FREQUENCY 0.5 Spurious Free Dynamic Range (dB) +80 0.0 –0.5 Delta VOUT (dB) 0 Temperature (°C) –64 2nd and 3rd Harmonic (dBc) –60 –50 10MHz +62 10MHz –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 +75 +70 +65 +60 +55 +50 +45 0 5 10 15 20 25 30 35 0 2 4 6 8 10 VREF (MHz) VREF (MHz) VREF Amplitude +0.75V DC 100mVp-p AC (All Bits on, 47pF Pin 35) VREF Amplitude +0.75V DC 100mVp-p AC (All Bits on, 47pF Pin 35) ® DAC600 8 12 THEORY OF OPERATION Decoding of bits 1-4 into 15 segments and synchronizing the data with a master/slave register reduces glitching. If the BYPASS input is low, data is transferred to the output on the positive going edge of the clock. If BYPASS is high, data is transferred to the output regardless of clock state. All digital inputs are ECL compatible. The DAC600 employs a familiar architecture where input bits switch on the appropriate current sources (Figure 1.) Bits 1-4 are decoded into 15 segments after the first set of latches. The edge triggered master-slave latches are driven by an internal clock buffer. Current sources for bits 5 and 6 are scaled down in binary fashion. These current sources are switched directly to the output of the R-2R ladder. Bits 7-12 are properly scaled and fed to the laser trimmed R-2R ladder. ROFFSET The output current sees 50Ω of output impedance from the equivalent resistance of a R-2R ladder. With all of the current sources off, the output voltage is at 0V. With all current sources on (–20mA), the output voltage is at –1V. Transfer function information is given in Tables I and II. VREF VOUT NOT MSB 2 3 4 5 6 7 8 9 10 11 LSB Current Sources Latches Latches Decoder Current Switches CLK 50Ω 50Ω (Ladder Equivalent Resistance) Clock Buffer Bypass VOUT LGND CLK FIGURE 1. Basic DAC600 Architecture. INPUT BITS 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • • • • 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 OUTPUT VOLTAGES VOUT NVOUT 0 1 0V –244µV –0.999756V 0.999512V 0 1 • • • • –0.5 –0.999756V –0.499756 0 TABLE I. Input Code vs Output Voltage Relationships. BIT VOLTAGE (No External Load, VOUT) 1 2 3 4 5 6 7 8 9 10 11 12 (LSB) –0.5 –0.25 –0.125 –62.5mV –31.25mV –15.625mV –7.8125mV –3.9063mV –1.9531mV –976µV –488µV –244µV TABLE II. Nominal Bit Weight Values. ® 9 DAC600 The DAC600 can also accept a wideband multiplying reference input. The full power bandwidth of this reference is approximately 30MHz. Care must be taken not to exceed the minimum and maximum input reference voltage levels which are 100mV and +1.25V respectively (refer to the absolute maximum ratings section). In the multiplying reference mode, the 0.4µF bypass capacitor on LBIAS and the 0.1µF on pin 35 need to be removed. A 47pF capacitor to ground needs to be connected to pin 35 (Figure 4.) There is also a complementary VOUT NOT output that allows for a differential output signal. The full scale complementary outputs (VOUT and VOUT NOT) can be simply modeled as –20mA in parallel with 50Ω. This gives an output swing of 0.5Vp-p with an external 50Ω load. REFERENCE/GAIN ADJUSTMENT The VREF pin should be supplied by a +1.0V reference that is capable of supplying a nominal current of 1.25mA. An alternative would be the use of a 1.25mA current source. A low drift reference will minimize gain drift. A recommended reference circuit is given in Figure 2 as shown in the Typical Performance Curves, lowering the reference voltage to +0.8V will typically improve the Spurious Free Dynamic Range by a few dB. VREF2 47pF DAC600 VREF LBIAS +5V 35 VREF 38 39 (AC Ref Input) 50 +5V (Open) 0.1µF 0.1µF 8 6 FIGURE 4. Connections for a Multiplying Reference Input. 100µA REF200 TIMING +VS 1 Out OPA602 –VS 0.01µF 100Ω(1) The DAC600 has an internal latch that is triggered on the rising edge of the clock when the BYPASS pin is set LOW. This master-slave mode of operation will assure that the 12 bits will arrive at the current sources with a minimum of data skew. Therefore, this mode is recommended for the vast majority of applications. Observing the minimum set-up and hold time recommendations will ensure proper data latching, refer to Figure 5 for complete timing specifications. +1VREF OUT 0.1µF 10kΩ(1) –5V When BYPASS is set HIGH, the DAC600 will operate in the transparent mode. In this mode, both the master and slave registers are transparent and changes in input data ripple directly to the output. Since the four MSBs have a decoder delay, these bits arrive at the output approximately 600 picoseconds later than the lower 8 LSBs. Because this data skew causes glitch, this mode is not recommended for optimum AC performance. NOTE: (1) 50 to 100 ppm/°C resistors. FIGURE 2. A Low Drift External Reference Circuit. A low-cost alternative reference circuit is shown in Figure 3. This circuit uses the Burr-Brown REF1004-2.5 micropower voltage reference. Gain drift is dependent upon the temperature coefficient of the 1.2kΩ resistor. A TC of < 10ppm/°C is recommended. The DAC600 has a differential ECL clock input. This clock input can also be driven by a single ended clock if desired by trying the CLKNOT input to an external voltage of –1.3V. Using a differential clock provides much improved digital feedthrough immunity, however. +5V DRIVING THE DAC600 1.8kΩ The DAC600 inputs will most likely be driven by high speed ECL gate outputs. These outputs should be terminated using standard high speed transmission line techniques. Consult an ECL handbook for proper methods of termination. 1.2kΩ +1VREFOUT Termination resistors should not be connected to the analog ground plane close to the DAC600. The fast changing digital bit currents will cause noise in the analog ground plane under this layout scheme. These fast changing digital currents should be steered away from the sensitive DAC600 REF1004-2.5 FIGURE 3. Low Cost External Reference Circuit. ® DAC600 10 tPWH tPWL Clock 1 Clock 0 CLK Data Data 1 Data 0 Clock 2 Data 2 VOUT 1 VOUT tP tPLSB tPMSB tSU SYMBOL tP tSU tH tPWL tPWH tPMSB tPLSB tH MIN DESCRIPTION Propagation delay. 50% of CLK to 50% of VOUT. Setup time DATA must remain stable before CLK. Hold time DATA must remain stable after CLK. CLK pulse width low (50% to 50%). CLK pulse width high (50% to 50%). Propagation delay, MSBs, transparent mode only. Propagation delay, LSBs, transparent mode only. 1.5 1.9 1.95 1.95 TYP MAX 2 1.0 1.7 UNITS ns ps ns ns ns ns ns 2.1 1.5 FIGURE 5. Timing Diagram. ALTCOMPB and ALTCOMPC should be bypassed with 0.1µF capacitors connected to VEEA. When not used in the multiplying mode LBIAS should be bypassed with a 0.4µF capacitor connected to VEEA. The heat spreader (pins 26 and 44) should be bypassed with a 0.1µF capacitor. analog ground plane. For speeds of up to 256MHz, series termination with 47Ω resistors will be adequate (Figure 6). This termination technique will greatly lessen the issue of termination currents coupling into the analog ground plane. This is shown in the typical DAC600 connection diagram (Figure 7.) MAXIMIZING PERFORMANCE In addition to optimizing the layout and ground of the DAC600, there are other important issues to consider when optimizing the performance of this DAC in various AC applications. ECL Drive Gates DAC600 47Ω The DAC600 includes an internal 50Ω output impedance to simplify output interfacing to a 50Ω load. Because some loads may be a complex impedance, care must be taken to match the output impedance with the load. Mismatching of impedances can cause reflections which will affect the measured AC performance parameters such as settling time, harmonic distortion, rise/fall times, etc. Often complex impedances can be matched by placing a variable 3 to 10pF capacitor at the output of the DAC to ground. Also, probing the output of the DAC can present a complex impedance. Bit Input Recommended Pull Down Resistor –5.2V FIGURE 6. Series Bit Termination. LAYOUT AND POWER SUPPLIES A multilayer PC board with a solid ground and power planes is recommended. All of the ground pins (both analog and digital) should be connected directly to the analog ground plane at the DAC600. The typical performance curves of Spurious Free Dynamic Range vs various combinations of clock rate and/or input frequency should give a general idea of the spectral performance of the DAC under system specific clock and output frequencies. For variable frequency DDS and ARB applications, having a programmable frequency bandpass (smart) filter at the output of the DAC can greatly improve system Wide busses for the power paths are recommended as good general practice. External bypassing is recommended. A 10µF ceramic capacitor in parallel with a 0.01µF chip capacitor will be sufficient in most applications. ® 11 DAC600 spur and noise performance by filtering out unwanted spur and noise spectra. Even with a programmable bandpass filter, care should be taken to update the DAC at greater than 4 times per cycle to (1) minimize the 2nd and 3rd harmonic magnitudes by having the output slew excessively between any successive clock and (3) to keep the 2nd harmonic and other even order harmonics from folding back close to the fundamental under the condition fOUT = 1/3 fCLK and (3) to keep the 3rd harmonic and other harmonics from folding back close to the fundamental under the condition fOUT = 1/4 fCLK. The making use of the high update rate of the DAC600 helps to lessen the problems of large harmonics “folding back” into the passband. For DDS applications, often the DAC itself is the limit in Spurious Free Dynamic Range (SFDR) performance. However, due to the high linearity of the DAC600, low frequency spurious performance may be limited by the digital truncation error of the phase accumulator/ROM combination. Most vendors supplying a combination of phase accumulator and ROM specify the SFDR of their digital algorithm. DAC600 38 VREF (+1.000V) 39 35 VREF H5 VREF H5 VREF/2 ALTCOMPC 0.1µF 42 47Ω 54 Bit 1 58 Bit 2 59 Bit 3 60 Bit 4 62 Bit 5 64 Bit 6 65 Bit 7 67 Bit 8 6 Bit 9 7 Bit 10 8 Bit 11 9 Bit 12 0.1µF ALTCOMPIB LBIAS ROFFSET Bit 1 (MSB) VOUT Bit 2 VOUT Bit 3 Bit 5 LGND Bit 6 LGND Bit 7 2 3 CLK 1 4 56 57 47Ω 63 66 Bit 9 VOUT Bit 10 VOUT Bit 11 Bit 12 (LSB) CLK DVEE CLK DVEE BYPASS –5.2V 0.1µF 28 –5.2V 0.4µF 50 13 –5.2V VOUT 14 Terminate Unused Output 15 16 17 VOUT 18 33 34 5 55 –5.2V Supply 0.1µF DGND DGND AGND DGND AGND DGND AGND DGND AGND LOOPCRNT –5.2V FIGURE 7. Typical DAC600 Connection Diagram. ® DAC600 0.1µF Bit 8 AVEE 47Ω 44 47 Bit 4 AVEE CLK 26 12 20 29 30 48 32 0.1µF 0.1µF