BB DAC7545

DA
C75
DAC
45
DAC7545
754
5
CMOS 12-Bit Multiplying
DIGITAL-TO-ANALOG CONVERTER
Microprocessor Compatible
FEATURES
DESCRIPTION
● FOUR-QUADRANT MULTIPLICATION
The DAC7545 is a low-cost CMOS, 12-bit fourquadrant multiplying, digital-to-analog converter with
input data latches. The input data is loaded into the
DAC as a 12-bit data word. The data flows through to
the DAC when both the chip select (CS) and the write
(WR) pins are at a logic low.
● LOW GAIN TC: 2ppm/°C typ
● MONOTONICITY GUARANTEED OVER
TEMPERATURE
● SINGLE 5V TO 15V SUPPLY
● TTL/CMOS LOGIC COMPATIBLE
Laser-trimmed thin-film resistors and excellent CMOS
voltage switches provide true 12-bit integral and differential linearity. The device operates on a single
+5V to +15V supply and is available in 20-pin plastic
DIP or 20-lead plastic SOIC packages. Devices are
specified over the commercial.
● LOW OUTPUT LEAKAGE: 10nA max
● LOW OUTPUT CAPACITANCE: 70pF max
● DIRECT REPLACEMENT FOR AD7545,
PM-7545
The DAC7545 is well suited for battery or other low
power applications because the power dissipation is
less than 0.5mW when used with CMOS logic inputs
and VDD = +5V.
RFB
20
VREF 19
12-Bit
Multiplying DAC
12
WR 17
CS 16
Input
Data Latches
1
OUT 1
2
AGND
18
3
VDD
DGND
12
DB11-DB0
(Pins 4-15)
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
1987 Burr-Brown Corporation
PDS-747F
1
Printed in U.S.A. August, 1997
DAC7545
SPECIFICATIONS
ELECTRICAL
VREF = +10V, VOUT 1 = 0V, ACOM = DCOM, unless otherwise specified.
DAC7545
VDD = +5V
VDD = +15V
GRADE
TA = +25°C
TMAX-TMIN(1)
All
J
K
L
GL
J
K
L
GL
J
K
L
GL
12
±2
±1
±1/2
±1/2
±4
±1
±1
±1
±20
±10
±5
±2
12
±2
±1
±1/2
±1/2
±4
±1
±1
±1
±20
±10
±6
±3
12
±2
±1
±1/2
±1/2
±4
±1
±1
±1
±25
±15
±10
±6
12
±2
±1
±1/2
±1/2
±4
±1
±1
±1
±25
±15
±10
±7
Gain Temperature Coefficient(3)
(∆Gain/∆Temperature)
All
±5
±5
±10
±10
DC Supply Rejection(3)
(∆Gain/∆VDD)
Output Leakage Current at Out 1
All
J, K, L, GL
0.015
10
0.03
50
0.01
10
0.02
50
%/%
nA
∆VDD ±5%
DB0-DB11 = 0V; WR, CS = 0V
All
2
2
2
2
µs
To 1/2LSB. Out1 Load = 100Ω
DAC output measured from
falling edge of WR. CS = 0V
300
400
5
5
250
250
5
5
PARAMETER
STATIC PERFORMANCE
Resolution
Accuracy
Differential Nonlinearity
Gain Error (with internal RFB)(2)
DYNAMIC PERFORMANCE
Current Settling Time(3)
TA = +25°C
TMAX-TMIN(1)
UNITS TEST CONDITIONS/COMMENTS
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
10-Bit Monotonic, TMIN to TMAX
10-Bit Monotonic, TMIN to TMAX
12-Bit Monotonic, TMIN to TMAX
12-Bit Monotonic, TMIN to TMAX
D/A register loaded with FFFH.
Gain error is adjustable using
the circuits in Figures 2 and 3.
ppm/°C Typical value is 2ppm/°C
for VDD = +5
Propagation Delay(3) (from digital input
change to 90% of final analog output)
Glitch Energy
AC Feedback at IOUT 1
All
All
REFERENCE INPUT
Input Resistance (pin 19 to AGND)
All
7
25
7
25
7
25
7
25
kΩ(6)
kΩ
AC OUTPUTS
Output Capacitance(3): COUT 1
COUT 2
All
All
70
200
70
200
70
200
70
200
pF
pF
DB0-DB11 = 0V; WR, CS = 0V
DB0-DB11 = VDD; WR, CS = 0V
DIGITAL INPUTS
VIH (Input HIGH Voltage)
VIL (Input LOW Voltage)
IIN (Input Current)(7)
Input Capacitance(3): DB0-DB11
WR, CS
All
All
All
All
All
2.4
0.8
±1
5
20
2.4
0.8
±10
5
20
13.5
1.5
±1
5
20
13.5
1.5
±10
5
20
V(6)
V
µA
pF
pF
VIN = 0 or VDD
VIN = 0V
VIN = 0V
SWITCHING CHARACTERISTICS(8)
Chip Select to Write Setup Time, tCS
All
All
All
Data Setup Time, tDS
All
Data Hold Time, tDH
All
380
270
0
400
280
210
150
10
180
120
0
160
100
90
60
10
200
150
0
240
170
120
80
10
ns(6)
ns(5)
ns(6)
ns(6)
ns(5)
ns(6)
ns(5)
ns(6)
See Timing Diagram
Chip Select to Write Hold Time, tCH
Write Pulse Width, tWR
280
200
0
250
175
140
100
10
All
All
All
2
100
10
2
500
10
2
100
10
2
500
10
mA
µA
µA(5)
All Digital Inputs VIL or VIH
All Digital Inputs 0V or VDD
All Digital Inputs 0V or VDD
All
ns
Out1 Load = 100Ω. CEXT = 13pF(4)
nV-s(5) VREF = ACOM
mVp-p(5) VREF = ±10V, 10kHz Sine Wave
Input resistance TC = 300ppm/°C(5)
tCS ≥ tWR, tCH ≥ 0
POWER SUPPLY, IDD
NOTES: (1) Temperature ranges—J, K, L, GL: –40°C to +85°C. (2) This includes the effect of 5ppm max, gain TC. (3) Guaranteed but not tested. (4) DB0-DB11 = 0V
to VDD or VDD to 0V. (5) Typical. (6) Minimum. (7) Logic inputs are MOS gates. Typical input current (+25°C) is less than 1nA. (8) Sample tested at +25°C to ensure
compliance.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
DAC7545
2
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONNECTIONS
TA = +25°C, unless otherwise noted.
Top View
VDD to DGND ........................................................................... –0.3V, +17
Digital Input to DGND ............................................................... –0.3V, VDD
VRFB, VREF, to DGND ........................................................................ ±25V
VPIN 1 to DGND ......................................................................... –0.3V, VDD
AGND to DGND ........................................................................ –0.3V, VDD
Power Dissipation: Any Package to +75°C .................................... 450mW
Derates above +75°C by ................................ 6mW/°C
Operating Temperature:
Commercial J, K, L, GL .................................................. –40°C to +85°C
Storage Temperature ...................................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ................................................ +300°C
DIP/SOIC
OUT 1
1
20 RFB
AGND
2
19 VREF
DGND
3
18 VDD
(MSB) DB11
4
17 WR
DB10
5
DB9
6
15 DB0 (LSB)
DB8
7
14 DB1
DB7
8
13 DB2
DB6
9
12 DB3
DB5 10
11 DB4
NOTE: (1) Stresses above those listed above may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at
these or any other condition above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
DAC7545
16 CS
PACKAGE INFORMATION
Any integral circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
PRODUCT
PACKAGE
PACKAGE DRAWING
NUMBER(1)
DAC7545JP
DAC7545KP
DAC7545LP
DAC7545GLP
20-Pin PDIP
20-Pin PDIP
20-Pin PDIP
20-Pin PDIP
222
222
222
222
DAC7545JU
DAC7545KU
DAC7545LU
DAC7545GLU
20-Pin SOIC
20-Pin SOIC
20-Pin SOIC
20-Pin SOIC
221
221
221
221
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ORDERING INFORMATION
PRODUCT
PACKAGE
TEMPERATURE
RANGE
RELATIVE
ACCURACY (LSB)
GAIN ERROR (LSB)
VDD = +5V
DAC7545JP
DAC7545KP
DAC7545LP
DAC7545GLP
Plastic DIP
Plastic DIP
Plastic DIP
Plastic DIP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
±2
±1
±1/2
±1/2
±20
±10
±5
±2
DAC7545JU
DAC7545KU
DAC7545LU
DAC7545GLU
Plastic SOIC
Plastic SOIC
Plastic SOIC
Plastic SOIC
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
±2
±1
±1/2
±1/2
±20
±10
±5
±2
3
DAC7545
WRITE CYCLE TIMING DIAGRAM
tCS
CS
tCH
VDD
Mode Selection
0
tWR
WR
VDD
tDS
Data In
(DB0-DB11)
VIH
VIL
23
Data
Valid
tDH
Write Mode
Hold Mode
CS and WR low, DAC responds
to Data Bus (DB0-DB11) inputs.
Either CS or WR high, data bus
(DB0-DB11) is locked out; DAC
holds last data present when
WR or CS assumed high state.
0
VDD
0
NOTES: VDD = +5V, tR = tF = 20ns. VDD = +15V, tR = tF = 40ns. All inputs signal
rise and fall times measured from 10% to 90% of VDD. Timing measurement
reference level is (VIH + VIL)/2.
22
PAD
FUNCTION
PAD
FUNCTION
1
2
OUT 1
AGND
13
DB3
14
DB2
3
AGND
15
DB1 (LSB)
4
DGND
16
DB0
5
DB11
17
CS
6
DB10
18
WR
7
DB9
19
XYR
8
DB8
20
VDD
9
DB7
21
VREF
10
DB6
22
RFB
11
DB5
23
OUT1
12
DB4
Substrate Bias: Isolated. NC: No Connection
MECHANICAL INFORMATION
Die Size
Die Thickness
Min. Pad Size
Metalization
DAC7545 DIE TOPOGRAPHY
MILS (0.001")
MILLIMETERS
136 x 134 ±5
20 ±3
4x4
3.45 x 3.40 ±0.13
0.51 ±0.08
0.10 x 0.10
Aluminum
DISCUSSION
OF SPECIFICATIONS
Relative Accuracy
This term (also known as end point linearity) describes the
transfer function of analog output to digital input code.
Relative accuracy describes the deviation from a straight
line after zero and full scale have been adjusted.
Output Leakage Current
The current which appears at OUT 1 with the DAC loaded
with all zeros.
Multiplying Feedthrough Error
The AC output error due to capacitive feedthrough from
VREF to OUT 1 with the DAC loaded with all zeros. This test
is performed using a 10kHz sine wave.
Differential Nonlinearity
Differential nonlinearity is the deviation from an ideal 1LSB
change in the output, for adjacent input code changes. A
differential nonlinearity specification of 1LSB guarantees
monotonicity.
Output Current Settling Time
The time required for the output to settle within ±0.5LSB
of final value from a change in code of all zeros to all ones,
or all ones to all zeros.
Gain Error
Gain error is the difference in measure of full-scale output
versus the ideal DAC output. The ideal output for the
DAC7545 is –(4095/4096)(VREF). Gain error may be adjusted to zero using external trims as shown in the applications section.
DAC7545
4
Propagation Delay
The delay of the internal circuitry is measured as the time
from a digital code change to the point at which the
output reaches 90% of final value.
current than normal. Minimizing this transition time through
the linear region and insuring that the digital inputs are
operated as close to the rails as possible will minimize the
supply drain current.
Digital-to-Analog Glitch Impulse
The area of the glitch energy measured in nanovolt-seconds.
Key contributions to glitch energy are internal circuitry
timing differences and charge injected from digital
logic. The measurement is performed with VREF = GND and
an OPA600 as the output op amp and G1 (phase
compensation) = 0pF.
APPLICATIONS
UNIPOLAR OPERATION
Figure 2 shows the DAC7545 connected for unipolar operation. The high-grade DAC7545 is specified for a 1LSB gain
error, so gain adjust is typically not needed. However, the
resistors shown are for adjusting full-scale errors. The value
of R1 should be minimized to reduce the effects of mismatching temperature coefficients between the internal and
external resistors. A range of adjustment of 1.5 times the
desired range will be adequate. For example, for a
DAC7545JP, the gain error is specified to be ±25LSB. A
range of adjustment of ±37LSB will be adequate. The
equation below results in a value of 458Ω for the potentiometer (use 500Ω).
Monotonicity
Monotonicity assures that the analog output will increase
or stay the same for increasing digital input codes. The
DAC7545 is guaranteed monotonic to 12 bits, except the
J grade is specified to be 10-bit monotonic.
Power Supply Rejection
Power supply rejection is the measure of the sensitivity of
the output (full scale) to a change in the power supply
voltage.
R1 =
The addition of R1 will cause a negative gain error. To
compensate for this error, R2 must be added. The value of R2
should be one-third the value of R1.
CIRCUIT DESCRIPTION
Figure 1 shows a simplified schematic of the digital-toanalog converter portion of the DAC7545. The current from
the VREF pin is switched from OUT 1 to AGND by the
FET switch. This circuit architecture keeps the resistance at
the reference pin constant and equal to RLDR, so the reference
could be provided by either a voltage or current, AC or DC,
positive or negative polarity, and have a voltage range up to
±20V even with VDD = 5V. The RLDR is equal to “R” and is
typically 11kΩ.
R
VREF
R
R
RLADDER
(3 x Gain Error)
4096
The capacitor across the feedback resistor is used to compensate for the phase shift due to stray capacitances of the
circuit board, the DAC output capacitance, and op amp input
capacitance. Eliminating this capacitor will result in excessive ringing and an increase in glitch energy. This capacitor
should be as small as possible to minimize settling time.
The circuit of Figure 2 may be used with input voltages up
to ±20V as long as the output amplifier is biased to handle
the excursions. Table I represents the analog output for four
codes into the DAC for Figure 2.
R
R2
+5V
2R
2R
2R
2R
2R
RFB
VIN
OUT 1
VDD
VREF
R1
C1
33pF
RFB
OUT 1
DAC7545
AGND
DGND
VOUT
OPA604
AGND
DB11
(MSB)
DB10
DB9
DB0
(LSB)
DB0-DB11
FIGURE 1. Simplified DAC Circuit of the DAC7545.
FIGURE 2. Unipolar Binary Operation.
The output capacitance of the DAC7545 is code dependent
and varies from a minimum value (70pF) at code 000H to a
maximum (200pF) at code FFFH.
The input buffers are CMOS inverters, designed so that
when the DAC7545 is operated from a 5V supply (VDD), the
logic threshold is TTL-compatible. Being simple CMOS
inverters, there is a range of operation where the inverters
operate in the linear region and thus draw more supply
BINARY CODE
ANALOG OUTPUT
MSB
LSB
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
–VIN (4095/4096)
–VIN (2048/4096) = –1/2VIN
–VIN (1/4096)
0V
TABLE I. Unipolar Codes.
5
DAC7545
R2
R4
20kΩ
+5V
18
VDD
VIN
19
R1
C1
33pF
20
RFB
OPA604
or
1/2 OPA2604
VREF
DAC7545
DB11
VOUT
AGND
DB10-DB0
R5
20kΩ
R3
10kΩ
1
OUT 1
R6
5kΩ 10%
2
4
OPA604
or
1/2 OPA2604
11
U1
(See Text)
Analog Common
12
Data Input
FIGURE 3. Bipolar Operation (Two's Complement Code).
BIPOLAR OPERATION
Figure 3 and Table II illustrate the recommended circuit and
code relationship for bipolar operation. The D/A function
itself uses offset binary code. The inverter, U1, on the MSB
line converts two's complement input code to offset binary
code. If the inversion is done in software, U1 may be
omitted.
VOUT =
2
ANALOG OUTPUT
MSB
LSB
0111 1111 1111
0000 0000 0001
0000 0000 0000
1111 1111 1111
1000 0000 0000
+VIN (2047/2048)
+VIN (1/2048)
0V
–VIN (1/2048)
–VIN (2048/2048)
4
+
DB9
8
+ ••• +
DB0
4096
VIN
DB0-DB11
RFB
17
+5V
20
16
OUT 1
18
19
DAC7545
AGND
DGND
VOUT
NOTE: There must be
at least 1LSB loaded in
the DAC or the amp will
saturate due to the lack
of feedback.
OPA111
FIGURE 4. Digitally Controlled Gain Block.
TABLE II. Two's Complement Code Table for Circuit of
Figure 3.
connected to an external op amp with its noninverting input
connected to AGND. The op amp selected should have a
low input bias current and low VOS and VOS drift over
temperature. The op amp offset voltage should be less than
(25 x 10–6)(VREF) over operating conditions. Suitable op
amps are the Burr-Brown OPA37 and the OPA627 for fixed
reference applications and low bandwidth requirement. The
OPA37 has low VOS and will not require an offset trim. For
wide bandwidth, high slew rate, or fast settling applications,
the Burr-Brown OPA604 or 1/2 OPA2604 are recommended.
DIGITALLY CONTROLLED GAIN BLOCK
Figure 4 shows a circuit for digitally controlled gain block.
The feedback for the op amp is made up of the FET switch
and the R-2R ladder. The input resistor to the gain block is
the RFB of the DAC7545. Since the FET switch is in the
feedback loop, a “zero code” into the DAC will result in the
op amp having no feedback, and a saturated op amp output.
Unused digital inputs should be connected to VDD or to
DGND. This prevents noise form triggering the high impedance digital input. It is suggested that the unused digital
inputs also be given a path to ground or VDD through a 1MΩ
resistor to prevent the accumulation of static charge if the PC
card is unplugged from the system. In addition, in systems
where the AGND to DGND connection is on a backplane, it
is recommended that two diodes be connected in inverse
parallel between AGND and DGND.
APPLICATIONS HINTS
CMOS DACs, such as the DAC7545, exhibit a code-dependent out resistance. The effect of this is a code-dependent
differential nonlinearity at the amplifier output which
depends on the offset voltage, VOS, of the amplifier. Thus
linearity depends upon the potential of OUT 1 and AGND
being exactly equal to each other. Usually the DAC is
DAC7545
+
DB10
WR CS
R3, R4, and R5 must match within 0.01% and should be the
same type of resistors (preferably wire-wound or metal foil),
so that their temperature coefficients match. Mismatch of R3
value to R4 causes both offset and full-scale error. Mismatch
of R5 to R4 and R3 causes full-scale error.
DATA INPUT
–VIN
DB11
6
INTERFACING
TO MICROPROCESSORS
A15
A0
The DAC7545 can be directly interfaced to either an 8- or
16-bit microprocessor through its 12-bit wide data latch
using the CS and WR controls.
Address Bus
Address
Decode
CPU
An 8-bit processor interface is shown in Figure 5. It uses two
memory addresses, one for the lower 8 bits and one for the
upper 4 bits of data into the DAC via the latch.
Q0(1)
CS
CS
Q1(2)
4
Latch 4
DB11
DB8
DAC7545
WR
WR
WR
8
DB7
DB0
DB7
DB0
8-Bit Data Bus
NOTES: (1) Q0 = Decoded Address for DAC.
(2) Q1 = Decoded Address for Latch.
FIGURE 5. 8-Bit Processor Interface.
7
DAC7545