® DDC112 112 DDC For most current data sheet and other product information, visit www.burr-brown.com Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● MONOLITHIC CHARGE MEASUREMENT ADC ● DIGITAL FILTER NOISE REDUCTION: 3.2ppm, rms ● INTEGRAL LINEARITY: ±0.005% Reading ±0.5ppm FSR ● HIGH PRECISION, TRUE INTEGRATING FUNCTION ● PROGRAMMABLE FULL SCALE ● SINGLE SUPPLY ● CASCADABLE OUTPUT The DDC112 is a dual input, wide dynamic range, charge-digitizing analog-to-digital converter (ADC) with 20-bit resolution. Low level current output devices, such as photosensors, can be directly connected to its inputs. Charge integration is continuous as each input uses two integrators; while one is being digitized, the other is integrating. For each of its two inputs, the DDC112 combines current-to-voltage conversion, continuous integration, programmable full-scale range, A/D conversion, and digital filtering to achieve a precision, wide dynamic range digital result. In addition to the internal programmable full-scale ranges, external integrating capacitors allow an additional user-settable full-scale range of up to 1000pC. To provide single-supply operation, the internal ADC utilizes a differential input, with the positive input tied to VREF. When the integration capacitor is reset at the beginning of each integration cycle, the capacitor charges to VREF. This charge is removed in proportion to the input current. At the end of the integration cycle, the remaining voltage is compared to VREF. The high-speed serial shift register which holds the result of the last conversion can be configured to allow multiple DDC112 units to be cascaded, minimizing interconnections. The DDC112 is available in a SO-28 package and is offered in two performance grades. APPLICATIONS ● ● ● ● ● ● DIRECT PHOTOSENSOR DIGITIZATION CT SCANNER DAS INFRARED PYROMETER PRECISION PROCESS CONTROL LIQUID/GAS CHROMATOGRAPHY BLOOD ANALYSIS Protected by US Patent #5841310 AVDD CAP1A CAP1A AGND VREF DVDD DGND CHANNEL 1 DCLK IN1 CAP1B CAP1B CAP2A CAP2A Dual Switched Integrator ∆Σ Modulator Digital Filter DVALID DXMIT DOUT DIN CHANNEL 2 IN2 CAP2B CAP2B Digital Input/Output RANGE2 RANGE1 RANGE0 Control Dual Switched Integrator TEST CONV CLK International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1997 Burr-Brown Corporation PDS-1421D 1 DDC112 Printed in U.S.A. January, 2000 SPECIFICATIONS At TA = +25°C, AVDD = DVDD = +5V, DDC112U: TINT = 500µs, CLK = 10MHz, DDC112UK: TINT = 333.3µs, CLK = 15MHz, VREF = +4.096V, continuous mode operation, and internal integration capacitors, unless otherwise noted. DDC112U PARAMETER CONDITIONS ANALOG INPUTS External, Positive Full-Scale Range 0 Internal, Positive Full-Scale Range 1 Range 2 Range 3 Range 4 Range 5 Range 6 Range 7 Negative Full-Scale Input MAX Continuous Mode Non-continuous Mode CSENSOR(2) = 0pF, Range 5 (250pC) CSENSOR = 25pF, Range 5 (250pC) CSENSOR = 50pF, Range 5 (250pC) Integral Linearity Error(4) No Missing Codes Input Bias Current Range Error Range Error Match(5) Range Sensitivity to VREF Offset Error Offset Error Match(5) DC Bias Voltage(6) (Input VOS) Power Supply Rejection Ratio Internal Test Signal Internal Test Accuracy TA = +25°C Range 5 (250pC) All Ranges VREF = 4.096 ±0.1V Range 5, (250pC) 500 50 1 4.000 POWER SUPPLY REQUIREMENTS Power Supply Voltage Supply Current Analog Current Digital Current Total Power Dissipation IOH = –500µA IOL = 500µA 2 1,000,000 10 12 12 ±0.5 ±0.2 3 0.01 2 25 ±0.05 TINT = 500µs DIGITAL INPUT/OUTPUT Logic Levels VIH VIL VOH VOL Input Current, IIN Data Format(9) 50 52.5 100 105 150 157.5 200 210 250 262.5 300 315 350 367.5 of Positive FS ✻ ✻ ✻ ✻ ✻ ✻ ✻ 333.3 ✻ ✻ 4.0 –0.3 4.5 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ DVDD + 0.3 +0.8 ✻ ✻ ✻ AVDD = +5V DVDD = +5V –40 –60 pC ✻ ✻ ✻ ✻ ✻ ✻ ✻ pC pC pC pC pC pC pC pC 3 ✻ 15 15 kHz µs µs MHz MHz 7 ppm of FSR(3), rms ppm of FSR, rms ppm of FSR, rms ✻ 225 ✻ ✻ ✻ ±600 ✻ ✻ ±3(10) ±0.7(10) ✻ ✻ 50(10) Bits pA % of FSR % of FSR ppm of FSR ppm of FSR mV ppm of FSR/V pC % ppm of FSR/°C ppm of FSR/minute µV/°C pA/°C pA ppm/°C ppm/°C ✻ 275 V µA ✻ ✻ ✻ ✻ V V V V µA ✻ V 130 mA mA mW +70 ✻ °C °C ✻ 5.25 14.8 1.2 80 ✻ ±1 ✻ ✻ 25 ✻ ✻ Straight Binary 4.75 ✻ ✻ ✻ ✻ 4.200 0.4 +10 ✻ UNITS ✻ 0 4.096 150 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ MAX ✻ 1(10) 50(10) –10 AVDD and DVDD TYP ✻ ✻ ✻ 3.2 3.8 4.2 6.0 ±0.005% Reading ±0.5ppm FSR, max ±0.005% Reading ±0.5ppm FSR, typ ±0.025% Reading ±1.0ppm FSR, max 20 0.1 10 5 0.1 0.5 1:1 ±200 ±100 ±0.05 ±2 ±25 ±200 13 ±10 PERFORMANCE OVER TEMPERATURE Offset Drift Offset Drift Stability DC Bias Voltage Drift Applied to Sensor Input Input Bias Current Drift +25°C to +45°C Input Bias Current TA = +75°C Range Drift(7) Range 5 (250pC) Range Drift Match(5) Range 5 (250pC) REFERENCE Voltage Input Current(8) MIN 1000 47.5 95 142.5 190 237.5 285 332.5 –0.4% Differential Linearity Error TEMPERATURE RANGE Specified Performance Storage DDC112UK TYP CEXT = 250pF DYNAMIC CHARACTERISTICS Conversion Rate Integration Time, TINT Integration Time, TINT System Clock Input (CLK) Data Clock (DCLK) ACCURACY Noise, Low Level Current Input(1) MIN ✻ 15.2 1.8 85 100 +85 +100 0 ✻ NOTES: (1) Input is less than 1% of full scale. (2) CSENSOR is the capacitance seen at the DDC112 inputs from wiring, photodiode, etc. (3) FSR is Full-Scale Range. (4) A best-fit line is used in measuring linearity. (5) Matching between side A and side B, not input 1 to input 2. (6) Voltage produced by the DDC112 at its input which is applied to the sensor. (7) Range drift does not include external reference drift. (8) Input reference current decreases with increasing TINT (see text). (9) Data format is Straight Binary with a small offset (see text). (10) Guaranteed but not tested. ® DDC112 2 PIN CONFIGURATION PIN DESCRIPTIONS Top View SO PIN LABEL 1 IN1 DESCRIPTION Input 1: analog input for Integrators 1A and 1B. The integrator that is active is set by the CONV input. IN1 1 28 IN2 AGND 2 27 AGND 2 AGND Analog Ground. 3 CAP1B External Capacitor for Integrator 1B. 4 CAP1B External Capacitor for Integrator 1B. 5 CAP1A External Capacitor for Integrator 1A. External Capacitor for Integrator 1A. CAP1B 3 26 CAP2B CAP1B 4 25 CAP2B CAP1A 5 24 CAP2A 6 CAP1A CAP1A 6 23 CAP2A 7 AVDD Analog Supply, +5V nominal. 8 TEST Test Control Input. When HIGH, a test charge is applied to the A or B integrators on the next CONV transition. 9 CONV Controls which side of the integrator is connected to input. In continuous mode; CONV HIGH → side A is integrating, CONV LOW → side B is integrating. CONV must be synchronized with CLK (see text). AVDD 7 22 VREF DDC112 TEST 8 21 AGND CONV 9 20 RANGE2 (MSB) CLK 10 19 RANGE1 DCLK 11 18 RANGE0 (LSB) DXMIT 12 17 DVALID DIN 13 16 DOUT DVDD 14 15 DGND ABSOLUTE MAXIMUM RATINGS(1) AVDD to DVDD ....................................................................... –0.3V to +6V AVDD to AGND ..................................................................... –0.3V to +6V DVDD to DGND ..................................................................... –0.3V to +6V AGND to DGND ............................................................................... ±0.3V VREF Voltage to AGND ............................................ –0.3V to AVDD +0.3V Digital Input Voltage to DGND ................................ –0.3V to DVDD +0.3V Digital Output Voltage to DGND ............................. –0.3V to DVDD +0.3V Package Power Dissipation ............................................. (TJMAX – TA)/θJA Maximum Junction Temperature (TJMAX) ...................................... +150°C Thermal Resistance, θJA ............................................................. 150°C/W Lead Temperature (soldering, 10s) ............................................... +300°C NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. 10 CLK 11 DCLK System Clock Input, 10MHz nominal. Serial Data Clock Input. This input operates the serial I/O shift register. 12 DXMIT Serial Data Transmit Enable Input. When LOW, this input enables the internal serial shift register. 13 DIN Serial Digital Input. Used to cascade multiple DDC112s. 14 DVDD Digital Supply, +5V nominal. 15 DGND Digital Ground. 16 DOUT Serial Data Output, Hi-Z when DXMIT is HIGH. 17 DVALID Data Valid Output. A LOW value indicates valid data is available in the serial I/O register. 18 RANGE0 Range Control Input 0 (least significant bit). 19 RANGE1 Range Control Input 1. 20 RANGE2 Range Control Input 2 (most significant bit). 21 AGND 22 VREF 23 CAP2A External Capacitor for Integrator 2A. 24 CAP2A External Capacitor for Integrator 2A. 25 CAP2B External Capacitor for Integrator 2B. 26 CAP2B External Capacitor for Integrator 2B. 27 AGND 28 IN2 Analog Ground. External Reference Input, +4.096V nominal. Analog Ground. Input 2: analog input for Integrators 2A and 2B. The integrator that is active is set by the CONV input. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURRBROWN product for use in life support devices and/or systems. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR SPECIFICATION TEMPERATURE RANGE PACKAGE PACKAGE DRAWING NUMBER DDC112U ±0.025% Reading ±1.0ppm% FSR –40°C to +85°C SO-28 217 DDC112U Rails " " " " " DDC112U/1K Tape and Reel ±0.025% Reading ±1.0ppm% FSR 0°C to +70°C SO-28 217 DDC112UK Rails " " " " DDC112UK/1K Tape and Reel DDC112UK " ORDERING NUMBER(1) TRANSPORT MEDIA NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DDC112U/1K” will get a single 1000-piece Tape and Reel. ® 3 DDC112 TYPICAL PERFORMANCE CURVES At TA = +25°C, characterization done with Range 5 (250pC), TINT = 500µs, VREF = +4.096, AVDD = DVDD = +5V, and CLK = 10MHz, unless otherwise noted. NOISE vs CSENSOR Noise (ppm of FSR, rms) 50 Range 2 Range 0 (CEXT = 250pF) 40 Noise (ppm of FSR, rms) Range 1 60 NOISE vs TINT 6 70 Range 7 30 20 5 CSENSOR = 50pF 4 CSENSOR = 0pF 3 2 Range 5 1 10 0 0 0 200 400 600 800 0.1 1000 1 10 4.5 8 CSENSOR = 50pF Noise (ppm of FSR, rms) Noise (ppm of FSR, rms) 9 3.5 3 CSENSOR = 0pF 2.5 2 1.5 1 Range 5 0.5 Range 1 7 6 Range 2 5 Range 3 4 3 Range 7 2 CSENSOR = 0pF 1 0 0 10 20 30 40 50 60 70 80 90 10 100 –40 –15 10 Input Level (% of Full-Scale) RANGE DRIFT vs TEMPERATURE 60 85 IB vs TEMPERATURE 10 Ranges 1 - 7 (Internal Integration Capacitor) All Ranges 1000 1 500 IB (pA) Range Drift (ppm) 35 Temperature (°C) 2000 1500 1000 NOISE vs TEMPERATURE NOISE vs INPUT LEVEL 5 4 100 TINT (ms) CSENSOR (pF) 0 0.1 –500 –1000 –1500 0.01 –40 –15 10 35 60 85 25 Temperature (°C) 45 55 Temperature (°C) ® DDC112 35 4 65 75 85 TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, characterization done with Range 5 (250pC), TINT = 500µs, VREF = +4.096, AVDD = DVDD = +5V, and CLK = 10MHz, unless otherwise noted. OFFSET DRIFT vs TEMPERATURE INPUT VOS vs RANGE 36 100 35 50 34 VOS (µV) Offset Drift (ppm of FSR) All Ranges 0 33 32 –50 31 30 –100 25 35 45 55 65 75 85 1 2 3 4 5 6 7 Range Temperature (°C) DIGITAL SUPPLY CURRENT vs TEMPERATURE ANALOG SUPPLY CURRENT vs TEMPERATURE 1.4 18 16 1.2 1.0 12 Current (mA) Current (mA) 14 10 8 6 0.8 0.6 0.4 4 0.2 2 0 0 –40 –15 10 35 60 –40 85 –15 10 60 85 POWER SUPPLY REJECTION RATIO vs FREQUENCY CROSSTALK vs FREQUENCY 600 0 –20 500 PSRR (ppm of FSR/V) Separation (dB) 35 Temperature (°C) Temperature (°C) Separation Measured Between Inputs 1 and 2 –40 –60 –80 –100 400 300 200 100 –120 0 –140 0 100 200 300 400 0 500 25 50 75 100 Frequency (KHz) Frequency (Hz) ® 5 DDC112 THEORY OF OPERATION register. The DVALID output goes LOW when the shift register contains valid data. The basic operation of the DDC112 is illustrated in Figure 1. The device contains two identical input channels where each performs the function of current-to-voltage integration followed by a multiplexed analog-to-digital (A/D) conversion. Each input has two integrators so that the current-to-voltage integration can be continuous in time. The output of the four integrators are switched to one delta-sigma converter via a four input multiplexer. With the DDC112 in the continuous integration mode, the output of the integrators from one side of both of the inputs will be digitized while the other two integrators are in the integration mode as illustrated in the timing diagram in Figure 2. This integration and A/D conversion process is controlled by the system clock, CLK. With a 10MHz system clock, the integrator combined with the delta-sigma converter accomplishes a single 20-bit conversion in approximately 220µs. The results from side A and side B of each signal input are stored in a serial output shift The digital interface of the DDC112 provides the digital results via a synchronous serial interface consisting of a data clock (DCLK), a transmit enable pin (DXMIT), a valid data pin (DVALID), a serial data output pin (DOUT), and a serial data input pin (DIN). The DDC112 contains only one A/D converter, so the conversion process is interleaved between the two inputs, as shown in Figure 2. The integration and conversion process is fundamentally independent of the data retrieval process. Consequently, the CLK frequency and DCLK frequencies need not be the same. DIN is only used when multiple converters are cascaded and should be tied to DGND otherwise. Depending on TINT, CLK, and DCLK, it is possible to daisy chain over 100 converters. This greatly simplifies the interconnection and routing of the digital outputs in those cases where a large number of converters are needed. AVDD CAP1A CAP1A AGND VREF DVDD DGND Input 1 DCLK IN1 CAP1B CAP1B Dual Switched Integrator CAP2A CAP2A ∆Σ Modulator Digital Filter Input 2 IN2 CAP2B CAP2B DVALID DXMIT DOUT DIN Digital Input/Output RANGE2 RANGE1 RANGE0 Control Dual Switched Integrator TEST CONV CLK FIGURE 1. DDC112 Block Diagram. IN1, Integrator A Integrate Integrate IN1, Integrator B Integrate IN2, Integrator A Integrate Integrate Integrate IN2, Integrator B Conversion in Progress Integrate IN1B IN2B IN1A IN2A Integrate IN1B IN2B DVALID FIGURE 2. Basic Integration and Conversion Timing for the DDC112 (continuous mode). ® DDC112 6 IN1A IN2A DEVICE OPERATION Basic Integration Cycle The fundamental topology of the front end of the DDC112 is a classical analog integrator as shown in Figure 3. In this diagram, only Input 1 is shown. This representation of the input stage consists of an operational amplifier, a selectable feedback capacitor network (CF), and several switches that implement the integration cycle. The timing relationships of all of the switches shown in Figure 3 are illustrated in Figure 4. Figure 4 is used to conceptualize the operation of the integrator input stage of the DDC112 and should not be used as an exact timing tool for design. Block diagrams of the reset, integrate, converter and wait states of the integrator section of the DDC112 are shown in Figure 5. This internal switching network is controlled externally with the convert command (CONV), range selection pins (RANGE0RANGE2), and the system clock (CLK). For the best noise performance, CONV must be synchronized with the rising edge of CLK. It is recommended CONV toggle within ±10ns of the rising edge of CLK. CF (pF, typ) INPUT RANGE (pC, typ) 0 External 12.5 to 250 Up to 1000 0 1 12.5 –0.2 to 50 1 0 25 –0.4 to 100 0 1 1 37.5 –0.6 to 150 1 0 0 50 –0.8 to 200 1 0 1 62.5 –0.1 to 250 1 1 0 75 –1.2 to 300 1 1 1 87.5 –1.4 to 350 RANGE2 RANGE1 RANGE0 0 0 0 0 TABLE I. Range Selection of the DDC112. SRESET (see Figures 4 and 5a). This is done during the reset time. In this manner, the selected capacitor is charged to the reference voltage, VREF. Once the integration capacitor is charged, SREF1, and SRESET are switched so that VREF is no longer connected to the amplifier circuit while it waits to begin integrating (see Figure 5b). With the rising edge on CONV, SINTA closes which begins the integration of Channel A. This puts the integrator stage into its integrate mode (see Figure 5c). The non-inverting inputs of the integrators are internally referenced to ground. Consequently, the DDC112 analog ground should be as clean as possible. The range switches, along with the internal and external capacitors (CF) are shown in parallel between the inverting input and output of the operational amplifier. Table I shows the value of the integration capacitor (CF) for each range. At the beginning of a conversion, the switches SA/D, SINTA, SINTB, SREF1, SREF2, and SRESET are set (see Figure 4). Charge from the input signal is collected on the integration capacitor causing the voltage output of the amplifier to decrease. A falling edge CONV stops the integration by switching the input signal from side A to side B (SINTA and SINTB). Prior to the falling edge of CONV, the signal on side B was converted by the A/D converter and reset during the time that side A was integrating. With the falling edge of CONV, side B starts integrating the input signal. Now the output voltage of side A’s operational amplifier is presented to the input of the ∆Σ A/D converter (see Figure 5d). At the completion of an A/D conversion, the charge on the integration capacitor (C F) is reset with S REF1 and CAP1A CAP1A SREF1 VREF 50pF RANGE2 25pF RANGE1 12.5pF RANGE0 SREF2 SINTA Input Current Photodiode IN1 ESD Protection Diode SA/D1A SRESET To Converter Integrator A SINTB Integrator B (same as A) FIGURE 3. Basic Integrator Configuration for Input 1 Shown with a 250pC (CF = 62.5pF) Input Range. ® 7 DDC112 CONV CLK SINTA SINTB SREF1 SREF2 SRESET Integrate Convert Wait Wait Wait Reset Convert Wait Configuration of Integrator A Reset SA/D1A VREF Integrator A Voltage Output FIGURE 4. Basic Integrator Timing Diagram as Illustrated in Figure 3. SREF1 CF VREF SINT SREF2 CF IN SREF1 VREF To Converter SRESET SA/D SINT SREF2 IN To Converter SRESET SA/D a) Reset Configuration CF SREF1 b) Wait Configuration VREF SINT SREF2 CF IN SRESET SREF1 VREF To Converter SA/D SINT SREF2 IN SRESET c) Integrate Configuration d) Convert Configuration FIGURE 5. Diagrams for the Four Configurations of the Front End Integrators of the DDC112. ® DDC112 8 To Converter SA/D Determining the Integration Capacitor (CF) Value EXTERNAL CAPACITOR PINS ON THE DDC112 The value of the integrator’s feedback capacitor, the integration period, and the reference voltage determine the positive full-scale (+FS) value of the DDC112. The approximate positive full-scale value of the DDC112 is given by the following equations: 5 3 23 25 Q FS = (0.96) VREF • C F Side 1 1 2 2 A B A B Since the range accuracy depends on the characteristics of the integration capacitor, they must be carefully selected. An external integration capacitor should have low voltage coefficient, temperature coefficient, memory, and leakage current. The optimum selection depends on the requirements of the specific application. Suitable types include COG ceramic, polycarbonate, polystyrene, and silver mica. (0.96) VREF • C F TINT or CF = 6 4 24 26 TABLE II. External Capacitor Connections with Range Configuration of RANGE2-RANGE0 = 000. Q IN = I IN • TINT I FS = and and and and INTEGRATOR Channel I FS • TINT (0.96) VREF Voltage Reference The “0.96” factor allows the front end integraters to reach full scale without having to completely swing to ground. The negative full-scale (–FS) range is approximately 0.4% of the positive full-scale range. For example, Range 5 has a nominal +FS range of 250pC. The –FS range is then approximately –1pC. This relationship holds for external capacitors as well and is independent of VREF (for VREF within the allowable range, see the Specification table). The external voltage reference is used to reset the integration capacitors before an integration cycle begins. It is also used by the ∆Σ converter while the converter is measuring the voltage stored on the integrators after an integration cycle ends. During this sampling, the external reference must supply charge needed by the ∆Σ converter. For an integration time of 500µs, this charge translates to an average VREF current of approximately 150µA. The amount of charge needed by the ∆Σ converter is independent of the integration time, therefore, increasing the integration time lowers the average current. For example, an integration time of 1000µs lowers to average VREF current to 75µA. It is critical that VREF be stable during the different modes of operation shown in Figure 5. The ∆Σ converter measures the voltage on the integrator with respect to VREF. Since the integrator’s capacitors are initially reset to VREF, any droop in VREF from the time the capacitors are reset to the time when the converter measures the integrator’s output will introduce an offset. It is also important that VREF be stable over longer periods of time as changes in VREF correspond directly to changes in the full-scale range. Finally, VREF should introduce as little additional noise as possible. For reasons mentioned above, it is strongly recommended that the external reference source be buffered with an operational amplifier, as shown in Figure 6. In this circuit, the voltage reference is generated by a 4.096V reference. Integration Capacitors There are seven different capacitors available on chip for each side of each channel in the DDC112. These internal capacitors are trimmed in production to achieve the specified performance for range error of the DDC112. The range control pins (RANGE0-RANGE2) change the capacitor value for all four integrators. Consequently, both inputs and both sides of each input will always have the same full scale range unless external capacitors are used. External integration capacitors may be used instead of the internal capacitors values by setting RANGE2-RANGE0 = 000. The external capacitor pin connections are summarized in Table II. Usually, all four external capacitors are equal in value, however, it is possible to have differing pairs of external capacitors between Input 1 and Input 2 of the DDC112. Regardless of the selected value of the capacitor, it is strongly recommended that the capacitors for sides A and B be the same. +5V +5V 0.10µF 7 4.99kΩ 2 To VREF Pin 22 of the DDC112 6 10kΩ 3 1 OPA350 + + LM404-4.1 10µF 0.10µF 10µF 0.1µF 4 FIGURE 6. Recommended External Voltage Reference Circuit for Best Low Noise Operation with the DDC112. ® 9 DDC112 DDC112 Frequency Response The frequency response of the DDC112 is set by the front end integrators and is that of a traditional continuous time integrator, as shown in Figure 7. By adjusting TINT, the user can change the 3dB bandwidth and the location of the notches in the response. The frequency response of the ∆Σ converter that follows the front end integrator is of no consequence because the converter samples a held signal from the integrators. That is, the input to the ∆Σ converter is always a DC signal. Since the output of the front end integrators are sampled, aliasing can occur. Whenever the frequency of the input signal exceeds one-half of the sampling rate, the signal will “fold” back down to lower frequencies. Test Mode When TEST is used, pins IN1 and IN2 are grounded and “packets” of approximately 13pC charge are transferred to the integration capacitors of both Input 1 and Input 2. This fixed charge can be transferred to the integration capacitors either once during an integration cycle or multiple times. In the case where multiple packets are transferred during one integration period, the 13pC charge is additive. This mode can be used in both the continuous and non-continuous mode timing. The timing diagrams for test mode are shown in Figure 8. The top three lines in Figure 8 define the timing when one packet of 13pC is sent to the integration capacitors. The bottom three lines define the timing when multiple packets are sent to the integration capacitors. A low-pass filter to reduce noise connects it to an operational amplifier configured as a buffer. This amplifier should have a unity gain bandwidth greater than 4MHz, low noise, and input/output common-mode ranges that support VREF. Following the buffer are capacitors placed close to the DDC112’s VREF pin. Even though the circuit in Figure 6 might appear to be unstable due to the large output capacitors, it works well for most operational amplifiers. It is NOT recommended that series resistance be placed in the output lead to improve stability since this can cause droop in VREF which produces large offsets. 0 Gain (dB) –10 –20 –30 –40 –50 1 TINT 0.1 TINT 10 TINT 100 TINT Frequency FIGURE 7. Frequency Response of the DDC112. Test Mode Disabled Test Mode Enabled Action Integrate B Integrate A 13pC into B 13pC into A Test Mode Disabled 13pC into B 13pC into A Integrate B Integrate A CONV TEST t1 t2 Test Mode Enabled Test Mode Disabled Test Mode Disabled Action Integrate B Integrate A 13pC into B 26pC into A 39pC into B 52pC into A Integrate B Integrate A CONV t4 t5 t2 TEST t1 t4 t3 FIGURE 8. Timing Diagram of the Test Mode of the DDC112. CLK = 10MHz TYP CLK = 15MHz SYMBOL DESCRIPTION MIN t1 Setup Time for Test Mode Enable 100 MAX MIN 100 TYP MAX UNITS ns t2 Setup Time for Test Mode Disable 100 100 ns t3 Hold Time for Test Mode Enable 100 100 ns t4 From Rising Edge of TEST to the Edge of CONV while Test Mode Enabled 5.4 3.6 µs t5 Rising Edge to Rising Edge of TEST 5.4 3.6 µs TABLE III. Timing for the DDC112 in the Test Mode. ® DDC112 10 Continuous and Non-Continuous Operational Modes The state diagram of the DDC112 is shown in Figure 9. In all, there are 8 states. Table IV provides a brief explanation of each of the states. TEST and CONV work together to implement this feature. The test mode is entered when TEST is HIGH prior to a CONV edge. At that point, a CONV edge triggers the grounding of the analog inputs and the switching of 13pC packets of charge onto the integration capacitors. If TEST is kept HIGH through at least two conversions (i.e., a rise and fall of CONV), all four integrators will be charged with a 13pC packet. At the end of each conversion, the voltage at the output of the integrators is digitized as discussed in the “Continuous Mode” and “Non-Continuous Mode” section of this data sheet. The test mode is exited when TEST is LOW and a CONV edge occurs. Once the test mode is entered as described above, TEST can cycle as many times as desired. When this is done, additional 13pC packets are added on the rising edge of TEST to the existing charge on the integrator capacitors. Multiple charge packets can be added in this way as long as the TEST pin is not LOW when CONV toggles. STATE MODE DESCRIPTION 1 Ncont Complete m/r/az of side A, then side B (if previous state is state 4). Initial power-up state when CONV is initially held HIGH. 2 Ncont Prepare side A for integration. 3 Cont Integrate on side A. 4 Cont Integrate on side B; m/r/az on side A. 5 Cont Integrate on side A; m/r/az on side B. 6 Cont Integrate on side B. 7 Ncont Prepare side B for integration. 8 Ncont Complete m/r/az of side B, then side A (if previous state is state 5). Initial power-up state when CONV is initially held LOW. TABLE IV. State Descriptions. DIGITAL ISSUES The digital interface of the DDC112 provides the digital results via a synchronous serial interface consisting of a data clock (DCLK), a transmit enable pin (DXMIT), a valid data pin (DVALID), a serial data output pin (DOUT), and a serial data input pin (DIN). The DDC112 contains only one A/D converter, so the conversion process is interleaved between the two inputs (see Figure 2). The integration and conversion process is fundamentally independent of the data retrieval process. Consequently, the CLK frequency and DCLK frequencies need not be the same. DIN is used when multiple converters are cascaded. Cascading or “daisy chaining” greatly simplifies the interconnection and routing of the digital outputs in cases where a large number of converters are needed. Refer to “Cascading Multiple Converters” section of this data sheet for more detail. mbsy 1 2 CONV • mbsy Ncont Ncont CONV 3 Int A Cont CONV • mbsy CONV 4 Int B/Meas A Cont The conversion rate of the DDC112 is set by a combination of the integration time (determined by the user) and the speed of the A/D conversion process. The A/D conversion time is primarily a function of the system clock (CLK) speed. One A/D conversion cycle encompasses the conversion of two signals (one from each input of the DDC112) and reset time for each of the integrators involved in the two conversions. In most situations, the A/D conversion time is shorter than the integration time. If this condition exists, the DDC112 will operate in the continuous mode. When the DDC112 is in the continuous mode, the sensor output is continuously integrated by one of the two sides of each input. 5 CONV • mbsy CONV • mbsy Int A/Meas B Cont CONV 6 CONV • mbsy Int B Cont CONV 7 Ncont 8 Ncont CONV • mbsy mbsy FIGURE 9. State Diagram. In the event that the A/D conversion takes longer than the integration time, the DDC112 will switch into a non-continuous mode. In non-continuous mode, the A/D converter is not able to keep pace with the speed of the integration process. Consequently, the integration process is periodically halted until the digitizing process catches up. These two basic modes of operation for the DDC112—continuous and non-continuous modes—are described below. Four signals are used to control progression around the state diagram: CONV and mbsy and their complements. The state machine uses the level as opposed to the edges of CONV to control the progression. mbsy is an internally generated signal not available to the user. It is active whenever a measurement/reset/auto-zero (m/r/az) cycle is in progress. ® 11 DDC112 for Table V can be easily found for a given CLK. For example, if CLK = 10MHz, then a CLK period = 0.1µs. t6 in Table V would then be 479.4µs. During the cont mode, mbsy is not active when CONV toggles. The non-integrating side is always ready to begin integrating when the other side finishes its integration. Consequently, keeping track of the current status of CONV is all that is needed to know the current state. Cont mode operation corresponds to states 3-6. Two of the states, 3 and 6, only perform an integration (no m/r/az cycle). SYMBOL mbsy becomes important when operating in the ncont mode; states 1, 2, 7, and 8. Whenever CONV is toggled while mbsy is active, the DDC112 will enter or remain in either ncont state 1 (or 8). After mbsy goes inactive, state 2 (or 7) is entered. This state prepares the appropriate side for integration. As mentioned above, in the ncont states, the inputs to the DDC112 are grounded. DESCRIPTION VALUE (CLK periods) t6 Cont mode m/r/az cycle 4794 t7 Cont mode data ready 4212 (tINT > 4794) 4212 ±3 (tINT = 4794) t8 1st ncont mode data ready 4212 ±3 t9 2nd ncont mode data ready 4548 t10 Ncont mode m/r/az cycle 9108 t11 Prepare side for integration ≥ 240 TABLE V. Timing Specifications Generalized in CLK Periods. One interesting observation from the state diagram is that the integrations always alternate between sides A and B. This relationship holds for any CONV pattern and is independent of the mode. States 2 and 7 insure this relationship during the ncont mode. Figure 10 shows a few integration cycles beginning with initial power-up for a cont mode example. The top signal is CONV and is supplied by the user. The next line indicates the current state in the state diagram. The following two traces show when integrations and measurement cycles are underway. The internal signal mbsy is shown next. Finally, DVALID is given. As described in the data sheet, DVALID goes active LOW when data is ready to be retrieved from the DDC112. It stays LOW until DXMIT is taken LOW by the user. In Figure 10 and the following timing diagrams, it is assumed that DXMIT it taken LOW soon after DVALID goes LOW. The text below the DVALID pulse indicates the side of the data and arrows help match the data to the corresponding integration. The signals shown in Figures 10 through 19 are drawn at approximately the same scale. In Figure 10, the first state is ncont state 1. The DDC112 always powers up in the ncont mode. In this case, the first state is 1 because CONV is initially HIGH. After the first two states, cont mode operation is reached and the states begin toggling between 4 and 5. From now on, the input is being continuously integrated, either by side A or side B. When power is first applied to the DDC112, the beginning state is either 1 or 8, depending on the initial level of CONV. For CONV held HIGH at power-up, the beginning state is 1. Conversely, for CONV held LOW at power-up, the beginning state is 8. In general, there is a symmetry in the state diagram between states 1-8, 2-7, 3-6 and 4-5. Inverting CONV results in the states progressing through their symmetrical match. TIMING EXAMPLES Cont Mode A few timing diagrams will now be discussed to help illustrate the operation of the state machine. These are shown in Figures 10 through 19. Table V gives generalized timing specifications in units of CLK periods. Values in µs CONV State 1 2 Integration Status 3 4 5 4 Integrate A Integrate B Integrate A Integrate B m/r/az Status m/r/az A m/r/az B m/r/az A t6 mbsy DVALID t7 t=0 Power-Up SYMBOL Side A Data DESCRIPTION VALUE (CLK = 10MHz) t6 Cont mode m/r/az cycle 479.4µs t7 Cont mode data ready 421.2µs 421.2 ±0.3µs Side A Data VALUE (CLK = 15MHz) 316.4µs (TINT > 479.4µs) (TINT = 479.4µs) FIGURE 10. Continuous Mode Timing (CONV HIGH at power-up). ® DDC112 Side B Data 12 280.5µs 280.5 ±0.2µs (TINT > 316.4µs) (TINT = 316.4µs) The time needed for the m/r/az cycle, t6, is the same time that determines the boundary between the cont and ncont modes described earlier in the Overview section. DVALID goes LOW after CONV toggles in time t1, indicating that data is ready to be retrieved. As shown in Figure 10, there are two values for t7, depending on TINT. The reason for this will be discussed in the Special Considerations section. Figure 11 shows the result of inverting the logic level of CONV. The only difference is in the first three states. Afterwards, the states toggle between 4 and 5 just as in the previous example. Figure 12 shows the timing diagram of the internal operations occurring during continuous mode operation. CONV State 8 7 Integration Status 6 5 4 5 Integrate B Integrate A Integrate B Integrate A m/r/az Status m/r/az B m/r/az A m/r/az B t6 mbsy DVALID t7 t=0 Power-Up Side B Data Side A Data Side B Data FIGURE 11. Continuous Mode Timing (CONV LOW at power-up). End Integration Side B Start Integration Side A End Integration Side A Start Integration Side B TINT CONV TINT Side B Side A A/D Conversion Input 1 (Internal) End Integration Side A Start Integration Side B Side A t12 Side A A/D Conversion Input 2 (Internal) Side B t12 t13 t14 DVALID Side B Data Ready Side A Data Ready FIGURE 12. Timing Diagram of the Internal Operation in Continuous Mode of the DDC112. CLK = 10MHz SYMBOL TYP CLK = 15MHz DESCRIPTION MIN MAX MIN 1,000,000 333 TYP MAX UNITS TINT Integration Period (continuous mode) 500 t12 A/D Conversion Time (internally controlled) 202.2 134.66 1,000,000 µs µs t13 A/D Conversion Reset Time (internally controlled) 13.2 8.8 µs t14 Integrator and A/D Conversion Reset Time (internally controlled) 61.8 41.2 µs TABLE VI. Timing for the Internal Operation in the Continuous Mode. ® 13 DDC112 Ncont Mode time as in the cont mode. The second data will be ready in time t9 after the first data is ready. One result of the naming convention used in this application bulletin is that when the DDC112 is operating in the “ncont mode”, it passes through both “ncont mode states” and “cont mode states”. For example, in Figure 13, the state pattern is 3, 4, 1, 2, 3, 4, 1, 2, 3, 4...where 3 and 4 are cont mode states. “Ncont mode” by definition means that for some portion of the time, neither side A nor B is integrating. States that perform an integration are labeled “cont mode states” while those that do not are called “ncont mode states”. Since integrations are performed in the ncont mode, just not continuously, some cont mode states must be used in a ncont mode state pattern. Figure 13 illustrates operation in the ncont mode. The integrations come in pairs (i.e., sides A/B or sides B/A) followed by a time during which no integrations occur. During that time, the previous integrations are being measured, reset and auto-zeroed. Before the DDC112 can advance to states 3 or 6, both sides A and B must be finished with the m/r/az cycle which takes time t10. When the m/r/az cycles are completed, time t11 is needed to prepare the next side for integration. This time is required for the ncont mode because the m/r/az cycle of the ncont mode is slightly different from that of the cont mode. After the first integration ends, DVALID goes LOW in time t8. This is the same CONV State 3 4 1 2 3 4 1 2 t11 Integration Status Int A m/r/az Status Int B Int A m/r/az A Int B m/r/az A m/r/az B m/r/az B t10 mbsy t9 DVALID t8 Side A Data SYMBOL Side B Data Side A Data DESCRIPTION VALUE (CLK = 10MHz) VALUE (CLK = 15MHz) t8 1st ncont mode data ready 421.2 ±0.3µs 280.5 ±0.2µs t9 2nd ncont mode data ready 4548.0µs 3028.9µs t10 Ncont mode m/r/az cycle 910.8µs 601.1µs t11 Prepare side for integration ≥ 24.0µs ≥ 24.0µs FIGURE 13. Non-Continuous Mode Timing. ® DDC112 14 Side B Data Start Integration Side A Start Integration Side A End Integration Side A Start Integration Side B End Integration Side B Release State Wait State TINT t17 CONV TINT t16 A/D Conversion Input 1 t12 A/D Conversion Input 2 t12 t13 t15 DVALID Side A Data Ready Side B Data Ready FIGURE 14. Conversion Detail for the Internal Operation of the Non-Continuous Mode with Side A Integrated First. CLK = 10MHz SYMBOL DESCRIPTION MIN TINT Integration Time (non-continuous mode) 50 t12 A/D Conversion Time (internally controlled) 202.2 134.6 t13 A/D Conversion Reset Time (internally controlled) 13.2 8.8 µs t15 Integrator and A/D Conversion Reset Time (internally controlled) Total A/D Conversion and Rest Time (internally controlled) Release Time 37.8 25.2 µs 910.8 606.6 µs t16 t17 TYP CLK = 15MHz MAX MIN 1,000,000 50 24 TYP MAX UNITS 1,000,000 µs µs µs 24 TABLE VII. Internal Timing for the DDC112 in the Non-Continuous Mode. Start Integration Side B Start Integration Side B End Integration Side B Start Integration Side A End Integration Side A Release State Wait State CONV TINT TINT t17 t16 A/D Conversion Input 1 t12 A/D Conversion Input 2 t12 t13 t15 DVALID Side B Data Ready Side A Data Ready FIGURE 15. Internal Operation Timing Diagram of the Non-Continuous Mode with Side B Integrated First. ® 15 DDC112 Looking at the state diagram, one can see that the CONV pattern needed to generate a given state progression is not unique. Upon entering states 1 or 8, the DDC112 remains in those states until mbsy goes LOW, independent of CONV. As long as the m/r/az cycle is underway, the state machine ignores CONV (see Figure 9). The top two signals are different CONV patterns that produce the same state. This feature can be a little confusing at first, but it does allow flexibility in generating ncont mode CONV patterns. For example, the DDC112 Evaluation Fixture operates in the ncont mode by generating a square wave with pulse width < t6. Figure 17 illustrates operation in the ncont mode using a 50% duty cycle CONV signal with TINT = 1620 CLK periods. Care must be exercised when using a square wave to generate CONV. There are certain integration times that must be avoided since they produce very short intervals for state 2 (or state 7 if CONV is inverted). As seen in the state diagram, the state progresses from 2 to 3 as soon as CONV is HIGH. The state machine does not insure that the duration of state 2 is long enough to properly prepare the next side for integration (t11). This must be done by the user with proper timing of CONV. For example, if CONV is a square wave with TINT = 3042 CLK periods, state 2 will only be 18 CLK periods long, therefore, t11 will not be met. CONV1 CONV2 mbsy State 3 4 1 2 3 4 1 2 FIGURE 16. Equivalent CONV Signals in Non-Continuous Mode. CONV State Integration Status 3 4 Int A Int B 1 2 3 4 Int A Int B 1 mbsy DVALID Side A Data Side B Data FIGURE 17. Non-Continuous Mode Timing with a 50% Duty Cycle CONV Signal. ® DDC112 16 Side A Data Changing Between Modes Changing from the ncont to cont mode occurs when TINT is increased so that TINT is always ≥ t6 (see Figure 14). With a longer TINT, the m/r/az cycle has enough time to finish before the next integration begins and continuous integration of the input signal is possible. For the special case of the very first integration when changing to the cont mode, TINT can be < t6. This is allowed because there is no simultaneous m/r/az cycle on the side B during state 3—there is no need to wait for it to finish before ending the integration on side A. Changing from the cont to ncont mode occurs whenever TINT < t6. Figure 18 shows an example of this transition. In this figure, the cont mode is entered when the integration on side A is completed before the m/r/az cycle on side B is complete. The DDC112 completes the measurement on sides B and A during states 8 and 7 with the input signal shorted to ground. Ncont integration begins with state 6. CONV State 5 4 5 8 Continuous Integration Status m/r/az Status Integrate A Integrate B m/r/az B 7 6 5 Int B Int A Non-Continuous Int A m/r/az A m/r/az B m/r/az A m/r/az B mbsy FIGURE 18. Changing from Continuous Mode to Non-Continuous Mode. CONV State 3 4 1 2 Non-Continuous Integration Status m/r/az Status Int A 4 Continuous Int B m/r/az A 3 Integrate A m/r/az B Integrate B m/r/az A mbsy FIGURE 19. Changing from Non-Continuous Mode to Continuous Mode. ® 17 DDC112 For TINT ≤ t6, the internal slow clock, is not allowed to shut down and the synchronization never occurs. Therefore, the time between CONV toggling and DVALID indicating data is ready has uncertainty due to the random phase relationship between CONV and the slow clock. This variation is ±1/(2fSLOWCLOCK) or ±3/fCLK. The timing to the second DVALID in the ncont mode will not have a variation since it is triggered off the first data ready (t9) and both are derived from the slow clock. SPECIAL CONSIDERATIONS NCONT MODE INTEGRATION TIME The DDC112 uses a relatively fast clock. For CLK = 10MHz, this allows TINT to be adjusted in steps of 100ns since CONV should be synchronized to CLK. However, for the internal measurement, reset and auto-zero operations, a slower clock is more efficient. The DDC112 divides CLK by six and uses this slower clock with a period of 600ns to run the m/r/az cycle and data ready logic. Polling DVALID to determine when data is ready eliminates any concern about the variation in timing since the readback is automatically adjusted as needed. If the data readback is triggered off the toggling of CONV directly (instead of polling), then waiting the maximum value of t7 or t8 insures that data will always be ready before readback occurs. Because of the divider, it is possible for the integration time to be a non-integer number of slow clock periods. For example, if TINT = 5000 CLK periods (500µs for CLK = 10MHz), there will be 833 1/3 slow clocks in an integration period. This non-integer relationship between TINT and the slow clock period causes the number of rising and falling slow clock edges within an integration period to change from integration to integration. The digital coupling of these edges to the integrators will in turn change from integration to integration which produces noise. The change in the clock edges is not random, but will repeat every 3 integrations. The coupling noise on the integrators appears as a tone with a frequency equal to the rate at which the coupling repeats. Data Retrieval In the continuous and non-continuous modes of operation, the data from the last conversion is available for retrieval with the falling edge of DVALID (see Figure 22). The falling edge of DXMIT in combination with the data clock (DCLK) will initiate the serial transmission of the data from the DDC112. Typically, data is retrieved from the DDC112 as soon as DVALID falls and completed before the next CONV transition from HIGH to LOW or LOW to HIGH occurs. If this is not the case, care should be taken to stop activity on DCLK and consequently DOUT by at least 10µs around a CONV transition. If this caution is ignored it is possible that the integration that is being initiated by CONV will have additional noise introduced. To avoid this problem in cont mode, the internal slow clock is shut down after the m/r/az cycle is complete when it is no longer needed. It starts up again just after the next integration begins. Since the slow clock is always off when CONV toggles, the same number of slow clock edges fall within an integration period regardless of its length. Therefore, TINT ≥ 4794 CLK periods will not produce the coupling problem described above. The serial output data at DOUT is transmitted in Straight Binary Code per Table VIII. An output offset has been built into the DDC112 to allow for the measurement of input signals near and below zero. Board leakage up to ≈ –0.4% of the positive full scale can be tolerated before the digital output clips to all zeroes. For the ncont mode however, the slow clock must always be left running. The m/r/az cycle is not completed before an integration ends. It is then possible to have digital coupling to the integrators. The digital coupling noise depends heavily on the layout of the printed circuit board used for the DDC112. For solid grounds and power supplies with good bypassing, it is possible to greatly reduce the coupling. However, for guaranteeing the best performance in the ncont mode, the integration time should be chosen to be an integer multiple of 1/(2fSLOWCLOCK). For CLK = 10MHz, the integration time should be an integer multiple of 300ns— TINT = 100µs is not. A better choice would be TINT = 99µs. CODE INPUT SIGNAL 1111 1111 1111 1111 1111 FS 1111 1111 1111 1111 1110 FS – 1LSB 0000 0001 0000 0000 0001 +1LSB 0000 0001 0000 0000 0000 Zero 0000 0000 0000 0000 0000 –0.4% FS TABLE VIII. Straight Binary Code Table. DATA READY Cascading Multiple Converters The DVALID signal which indicates that data is ready is generated using the internal slow clock. The phase relationship between this clock and CLK is set when power is first applied and is random. Since CONV is synchronized with CLK, it will have a random phase relationship with respect to the slow clock. When TINT > t6, the slow clock will temporarily shut down as described above. This shutdown process synchronizes the internal clock with CONV so that the time between when CONV toggles to when DVALID goes LOW (t7 and t8) is fixed. Multiple DDC112 units can be connected in serial or parallel configurations, as illustrated in Figures 20 and 21. DOUT can be used with DIN to “daisy chain” several DDC112 devices together to minimize wiring. In this mode of operation, the serial data output is shifted through multiple DDC112s, as illustrated in Figure 20. RPULLUP prevents DIN from floating when DXMIT is HIGH. Care should be taken to keep the capacitive load on DOUT as low as possible when running CLK=15MHz. ® DDC112 18 Sensor “F” Sensor “E” Sensor “D” IN2 IN1 Sensor “C” IN2 IN1 DDC112 Sensor “B” DDC112 DCLK DIN DVALID “F” “E” DCLK DXMIT RP DOUT DIN 40 Bits IN2 IN1 DDC112 DCLK DXMIT Sensor “A” DVALID “D” “C” DXMIT RP DOUT DIN 40 Bits DVALID RP DOUT “B” “A” Data Retrieval Outputs 40 Bits Data Retrievel Inputs FIGURE 20. Daisy-Chained DDC112’s. DDC112 DIN DOUT DXMIT DDC112 Data Output DOUT DXMIT DIN DDC112 DOUT DXMIT DIN Enable FIGURE 21. DDC112 in Parallel Operation. CLK t18 DVALID t19 DXMIT t20 DCLK(1) t22 t21 DOUT Output Disabled t23 Input 2 Bit 1 Input 2 Bit 20 Input 1 Bit 1 Input 1 Bit 20 MSB LSB MSB LSB Output Disabled Output Enabled NOTE: (1) Disable DCLK (preferably hold LOW) when DXMIT is HIGH. FIGURE 22. Digital Interface Timing Diagram for Data Retrieval From a Single DDC112. SYMBOL DESCRIPTION MIN t18 t19 t20 t21 t22 t23 Propagation Delay from Rising Edge of CLK to DVALID LOW Propagation Delay from DXMIT LOW to DVALID HIGH Setup Time from DCLK LOW TO DXMIT LOW Propagation Delay from DXMIT LOW to Valid DOUT Hold Time that DOUT is Valid After Falling Edge of DCLK Propagation Delay from DXMIT HIGH to DOUT Disabled Propagaton Delay from Falling Edge of DCLK to Valid DOUT Propagation Delay from Falling Edge of DCLK to Valid DOUT 30 30 t22A(1) t22B(2) TYP MAX 20 30 5 30 25 30 UNITS ns ns ns ns ns ns ns ns NOTES: (1) Applies to DDC112UK only, with a maximum load of one DDC112UK DIN (4pF typical) with an additional load of (5pF 100kΩ). (2) Applies to DDC112U only, with a maximum load of one DDC112U DIN (4pF typical) with an additional load of (5pF 100kΩ). TABLE IX. Timing for the DDC112 Data Retrieval. ® 19 DDC112 CLK t18 t26 DVALID t14 DXMIT t20 DCLK(1) t22 t24 t25 DIN t22A, t22B t21 DOUT Output Disabled t23 Input A Bit 1 Input E Bit 20 Input F Bit 1 Input F Bit 20 MSB LSB MSB LSB Output Disabled Output Enabled NOTE: (1) Disable DCLK (preferably LOW) when DXMIT is HIGH. FIGURE 23. Timing Diagram When Using the DIN Function of the DDC112. CLK = 10MHz SYMBOL DESCRIPTION MIN TYP CLK = 15MHz MAX MIN TYP MAX UNITS t24 Set-Up Time From DIN to Rising Edge of DCLK 10 5 ns t25 Hold Time For DIN After Rising Edge of DCLK 10 10 ns t26 Hold Time for DXMIT HIGH Before Falling Edge of DVALID 2 1.33 µs TABLE X. Timing for the DDC112 Data Retrieval Using DIN. RETRIEVAL BEFORE CONV TOGGLES (CONTINUOUS MODE) This is the most straightforward method. Data retrieval begins soon after DVALID goes LO and finishes before CONV toggles, see Figure 24. For best performance, data retrieval must stop t28 before CONV toggles. This method is the most appropriate for longer integration times. The maximum time available for readback is TINT – t27 – t28. For DCLK and CLK = 10MHz, the maximum number of DDC112s that can be daisy-chained together is: RETRIEVAL AFTER CONV TOGGLES (CONTINUOUS MODE) For shorter integration times, more time is available if data retrieval begins after CONV toggles and ends before the new data is ready. Data retrieval must wait t29 after CONV toggles before beginning. Figure 25 shows an example of this. The maximum time available for retrieval is t27 – t29 – t26 (421.2µs – 10µs –2µs for CLK = 10MHz), regardless of TINT. The maximum number of DDC112s that can be daisy-chained together is: TINT – 431.2µs 40 τ DCLK 409.2µs 40 τ DCLK Where τDCLK is the period of the data clock. For example, if TINT = 100µs and DCLK = 10MHz, the maximum number of DDC112s is: For DCLK = 10MHz, the maximum number of DDC112s is 102. 1000µs – 431.2µs = 142.2 → 142 DDC112s ( 40)(100 ns) ® DDC112 20 CONV TINT TINT DVALID t27 t28 DXMIT DCLK ••• DOUT ••• ••• ••• Side B Data Side A Data CLK = 10MHz SYMBOL DESCRIPTION MIN t27 Cont Mode Data Ready t28 Data Retrieval Shutdown Before Edge of CONV TYP CLK = 15MHz MAX MIN 421.2 TYP MAX µs 280.5 10 UNITS µs 10 FIGURE 24. Readback Before CONV Toggles. TINT CONV TINT TINT DVALID t27 t29 t26 DXMIT DCLK DOUT ••• ••• ••• ••• ••• ••• Side A Data Side B Data Side A Data CLK = 10MHz SYMBOL DESCRIPTION MIN t26 Hold Time for DXMIT HIGH Before Falling Edge of DVALID 2 t27 Cont Mode Data Ready t29 Data Retrieval Start-Up Before Edge of CONV TYP CLK = 15MHz MAX MIN MAX UNITS µs 1.33 421.2 10 TYP 280.5 µs µs 10 FIGURE 25. Readback After CONV Toggles. ® 21 DDC112 RETRIEVAL BEFORE AND AFTER CONV TOGGLES (CONTINUOUS MODE) For the absolute maximum time for data retrieval, data can be retrieved before and after CONV toggles. Nearly all of TINT is available for data retrieval. Figure 26 illustrates how this is done by combining the two previous methods. You must pause the retrieval during CONV’s toggling to prevent digital noise, as discussed previously, and finish before the CONV next data is ready. The maximum number of DDC112s that can be daisy-chained together is: TINT – 20µs – 2µs 40 τ DCLK For TINT = 500µs and DCLK = 10MHz, the maximum number of DDC112s is 119. TINT TINT TINT t29 DVALID t26 t28 DXMIT DCLK ••• ••• ••• ••• ••• ••• DOUT ••• ••• ••• ••• ••• ••• Side B Data Side A Data CLK = 10MHz DESCRIPTION MIN t26 Hold Time for DXMIT HIGH Before Falling Edge of DVALID 2 1.33 µs t28 Data Retrieval Shutdown Before Edge of CONV 10 10 µs t29 Data Retrieval Start-Up After Edge of CONV 10 10 µs FIGURE 26. Readback Before and After CONV Toggles. ® DDC112 22 TYP CLK = 15MHz SYMBOL MAX MIN TYP MAX UNITS RETRIEVAL: NONCONTINUOUS MODE time is highly dependent on the pattern used to generate CONV. As with the continuous mode, data retrieval must halt before and after CONV toggles (t28, t29) and be completed before new data is ready (t26). Retrieving in noncontinuous mode is slightly different as compared with the continuous mode. As shown in Figure 27 and described in detail in Application Bulletin AB-131, DVALID goes LOW in time t30 after the first integration completes. If TINT is shorter than this time, all of t31 is available to retrieve data before the other side’s data is ready. For TINT > t30, the first integration’s data is ready before the second integration completes. Data retrieval must be delayed until the second integration completes leaving less time available for retrieval. The time available is t31 – (TINT – t30). The second integration’s data must be retrieved before the next round of integrations begin. This CONV POWER-UP SEQUENCING Prior to power-up, all digital and analog input pins must be LOW. At the time of power-up, these signal inputs can be biased to a voltage other than 0V, however, they should never exceed AVDD or DVDD. The level of CONV at powerup is used to determine which side (A or B) will be integrated first. Before integrations can begin though, CONV must toggle, as shown in Figure 28. TINT TINT TINT TINT DVALID t30 t31 DXMIT DCLK ••• ••• DOUT ••• ••• Side A Data Side B Data CLK = 10MHz SYMBOL DESCRIPTION MIN TYP CLK = 15MHz MAX MIN TYP MAX UNITS t30 1st Ncont Mode Data Ready (see AB-131) 421.2 ±0.3 280.5 ±0.2 µs t31 2nd Ncont Mode Data Ready (see AB-131) 454.8 302.9 µs FIGURE 27. Readback in Noncontinuous Mode. Release State Power-Up Initialization CONV (HIGH at power-up) t32 CONV (LOW at power-up) Start Integration t33 Integrate Side A Integrate Side B Power Supplies FIGURE 28. Timing Diagram at Power-Up of the DDC112. SYMBOL DESCRIPTION MIN t32 t33 Power-On Initialization Period From Release Edge to Integration Start 50 50 TYP MAX UNITS µs µs TABLE XI. Timing for the DDC112 Power-Up Sequence. ® 23 DDC112 LAYOUT should be kept as far from the analog input signals as possible on the PC board. Power Supplies and Grounding Input shielding practices should be taken into consideration when designing the circuit layout for the DDC112. The inputs to the DDC112 are high impedance and extremely sensitive to extraneous noise. Leakage currents between the PCB traces can exceed the input bias current of the DDC112 if shielding is not implemented. Figure 30 illustrates an acceptable approach to this problem. A PC ground plane is placed around the inputs of the DDC112 (pins 1 and 28). This shield helps minimize coupled noise into the input pins. Additionally, the pins that are used for the external integration capacitors (pins 3, 4, 5, 6, 23, 24, 25 and 26) should be guarded by a ground plane when the external capacitors are used. Both AVDD and DVDD should be as quiet as possible. It is particularly important to eliminate noise from AVDD that is non-synchronous with the DDC112 operation. Figure 29 illustrates two acceptable ways to supply power to the DDC112. The first case shows two separate +5V supplies for AVDD and DVDD. In this case, each +5V supply of the DDC112 should be bypassed with 10µF solid tantalum capacitors and 0.1µF ceramic capacitors. The second case shows the DVDD power supply derived from the AVDD supply with a < 10Ω isolation resistor. In both cases, the 0.1µF capacitors should be placed as close to the DDC112 package as possible. Shielding Analog Signal Paths The approach above reduces leakage affects by surrounding these sensitive pins with a low impedance analog ground. Leakage currents from other portions of the circuit will flow harmlessly to the low impedance analog ground rather than into the analog input stage of the DDC112. As with any precision circuit, careful printed circuit layout will ensure the best performance. It is essential to make short, direct interconnections and avoid stray wiring capacitance—particularly at the analog input pins. Digital signals IN1 IN2 Analog Ground VS+ 7 10µF AVDD Analog Ground 0.1µF DDC112 VDD+ Shield external caps when used 14 DVDD 10µF 0.1µF Separate +5V Supplies Analog Power VS+ 7 10µF AVDD 0.1µF DDC112 < 10Ω 14 DV DD 0.1µF 1 28 2 27 3 26 4 25 5 24 6 23 7 DDC112 Analog Ground Shield external caps when used 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 Analog Ground One +5V Supply Digital I/O and Digital Power FIGURE 30. Recommended Shield for DDC112 Layout Design. FIGURE 29. Power Supply Connection Options. ® DDC112 Digital I/O and Digital Power 24