® DF1704 49% 704 FPO DF1 Stereo, 24-Bit, 96kHz 8X Oversampling Digital Interpolation Filter DIGITAL-TO-ANALOG CONVERTER TM FEATURES DESCRIPTION ● COMPANION DIGITAL FILTER FOR THE PCM1704 24-BIT AUDIO DAC The DF1704 is a high performance, stereo, 8X oversampling digital interpolation filter designed for high-end consumer and professional audio applications. The DF1704 supports 24-bit, 96kHz operation and features user-programmable functions, including selectable filter response, de-emphasis, attenuation, and input/output data formats. ● HIGH PERFORMANCE FILTER: Stopband Attenuation: –115dB Passband Ripple: ±0.00005dB ● AUDIO INTERFACE: Input Data Formats: Standard, LeftJustified, and I2S Input Word Length: 16, 20, or 24 Bits Output Word Length: 16, 18, 20, or 24 Bits Sampling Frequency: 32kHz to 96kHz The DF1704 is the ideal companion for Burr-Brown’s PCM1704 24-bit audio digital-to-analog converter. This combination allows for construction of very high performance audio systems and components. (OW1) (OW0) (IW1) ● SMALL 28-LEAD SSOP PACKAGE (IW0) ● PROGRAMMABLE FUNCTIONS: Hardware or Software Control Modes Sharp or Slow Roll-Off Filter Response Soft Mute Digital De-Emphasis Independent Left/Right Digital Attenuation ● +5V SINGLE-SUPPLY OPERATION (I2S) ● SYSTEM CLOCK: 256fS, 384fS, 512fS, 768fS ● ON-CHIP CRYSTAL OSCILLATOR BCKO BCKIN LRCIN DIN Serial Input I/F 8X Oversampling Digital Filter with Function Controller WCKO Output I/F DOL MD/CKO DOR MC/LRIP ML/RESV MODE (MUTE) Mode Control I/F SCK RST (DEM) Crystal/OSC (SF0) (SF1) (SRO) XTI XTO Power Supply CLKO VDD VSS International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1998 Burr-Brown Corporation PDS-1458B Printed in U.S.A. December, 1998 SPECIFICATIONS All specifications at +25°C, VDD = +5V, unless otherwise noted. DF1704E PARAMETER CONDITIONS MIN RESOLUTION TYP MAX 24 INPUT DATA FORMAT Audio Data Interface Format Audio Data Bit Length Audio Data Format Sampling Frequency (fS) System Clock Frequency CLKO AC CHARACTERISTICS Rise Time (tR) Fall Time (tF) Duty Cycle DIGITAL FILTER PERFORMANCE Filter Characteristics 1 (Sharp Roll-Off) Passband Stopband Passband Ripple Stopband Attenuation Filter Characteristics 2 (Sharp Roll-Off) Passband Ripple Stopband Passband Ripple Stopband Attenuation Delay Time De-Emphasis Error POWER SUPPLY REQUIREMENTS Voltage Range Supply Current: IDD Power Dissipation Bits Standard /Left-Justified /I2S 16/20/24 Selectable MSB-First, Two’s Binary Comp 32 96 kHz 256/384/512/768fS OUTPUT DATA FORMAT Audio Data Interface Format Audio Data Bit Length Audio Data Format DIGITAL INPUT/OUTPUT Input Logic Level: VIH VIL Output Logic Level: VOH VOL UNITS Right-Justified 16/20/24 Selectable MSB-First, Binary Two’s Complement 2.0 0.8 IOH = 2mA IOL = 4mA 4.5 0.5 20% to 80% VDD, 10pF 80% to 20% VDD, 10pF 10pF Load 4 3 37 ±0.00005dB –3dB V V V V ns ns % 0.454fS 0.493fS 0.546fS Stopband = 0.546fS ±0.00005 –115 ±0.0001dB –3dB dB dB 0.254fS 0.460fS 0.732fS Stopband = 0.748fS ±0.0001 45.125/fS 4.5 VDD ±0.003 dB dB sec dB 5.5 30 150 VDC mA mW +85 +100 °C °C –100 5 20 100 TEMPERATURE RANGE Operation Storage –25 –55 ® DF1704 2 PIN CONFIGURATION PIN ASSIGNMENTS PIN DIN 1 28 NAME I/O DESCRIPTION 1 DIN IN Serial Audio Data Input(3) LRCIN 2 BCKIN IN Bit Clock Input for Serial Audio Data(3) I2S IW0 IN IN Input Audio Data Format Selection(2, 4) Input Audio Data Word Selection(2, 4) BCKIN 2 27 SRO 3 4 I2 S 3 26 BCKO 5 IW1 IN Input Audio Data Word Selection(2, 4) 6 XTI IN Oscillator Input /External Clock Input 7 XTO OUT 8 VSS — IW0 4 25 WCKO IW1 5 24 DOL XTI 6 23 DOR XTO 7 22 VDD DF1704E Oscillator Output Digital Ground 9 CLKO OUT 10 MODE IN Mode Control Selection (H: Software, L: Hardware)(1) Buffered System Clock Output 11 MD/CKO IN Control Data Input/Clock Output Frequency Select(1, 5) Control Data Clock/Polarity of LRCK Select (1, 5) VSS 8 21 NC 12 MC/LRIP IN CLKO 9 20 OW1 13 ML/RESV IN Control Data Latch/Reserved (1, 5) RST IN Reset. When this pin is LOW, the digital filter is held in reset.(1) MODE 10 19 OW0 14 MD/CKO 11 18 SF1 15 MUTE IN Mute Control(1, 4) 16 DEM IN De-Emphasis Control(2, 4) MC/LRIP 12 17 SF0 17 SF0 IN Sampling Rate Select for De-emphasis(2, 4) ML/RESV 13 16 DEM 18 SF1 IN Sampling Rate Select for De-emphasis(2, 4) MUTE 19 OW0 IN Output Audio Data Word and Format Select(2, 4) 20 OW1 IN Output Audio Data Word and Format Select(2, 4) 21 NC — No Connection 22 VDD — Digital Power, +5V 23 DOR OUT Rch, Serial Audio Data Output 24 DOL OUT Lch, Serial Audio Data Output 25 WCKO OUT Word Clock for Serial Audio Data Output 26 BCKO OUT Bit Clock for Serial Audio Data Output RST 14 15 NC: No Connection PACKAGE INFORMATION PRODUCT DF1704E PACKAGE PACKAGE DRAWING NUMBER(1) 28-Lead SSOP 324 27 SRO IN Filter Response Select (2, 4) 28 LRCIN IN L/R Clock Input (fS) for Serial Audio Data(3) NOTES: (1) Pins 10-15; Schmitt-Trigger input with pull-up resistor. (2) Pins 3-5, 16-20, 27; Schmitt-Trigger input with pull-down resister. (3) Pins 1, 2, 28; Schmitt-Trigger input. (4) Pins 3-5, 15-20, 27; these pins are invalid when MODE (pin 10) is HIGH. (5) Pins 11-13; these pins have different functions corresponding to MODE (pin 10), (HIGH/LOW). NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY Supply Voltage (VDD , VCC1, VCC2R, VCC 2L) .................................... +6.5V Supply Voltage Differences ................................................................. ±0.1 GND Voltage Differences .................................................................. ±0.1V Digital Input Voltage ................................................. –0.3V to (VDD + 0.3V) Input Current (any pins except power supplies) ............................. ±10mA Power Dissipation .......................................................................... 300mW Operating Temperature Range ......................................... –25°C to +85°C Storage Temperature ...................................................... –55°C to +125°C Lead Temperature (soldering, 5s) ................................................. +260°C Package Temperature (reflow, 10s) .............................................. +235°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 DF1704 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER DIGITAL FILTER (DE-EMPHASIS OFF, fS = 44.1kHz) PASSBAND RIPPLE (Sharp Roll Off) 0.0001 0 0.00008 –20 0.00006 –40 Attenuation (dB) Attenuation (dB) FREQUENCY RESPONSE (Sharp Roll Off) 20 –60 –80 –100 –120 –140 0.00004 0.00002 0 –0.00002 –0.00004 –160 –0.00006 –180 –0.00008 –0.0001 –200 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 0.1 0.15 0.2 Frequency (fS) 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (fS) TRANSITION CHARACTERISTIC (Slow Roll Off) FREQUENCY RESPONSE (Slow Roll Off) 0 0 –20 –60 Attenuation (dB) Attenuation (dB) –40 –80 –100 –120 –140 –5 –10 –160 –180 –15 –200 0 0.5 1 1.5 2 2.5 3 3.5 0 4 0.1 0.2 0.3 0.4 0.5 0.6 0.7 12 14 Frequency (fS) Frequency (fS) DE-EMPHASIS AND DE-EMPHASIS ERROR DE-EMPHASIS (fS = 32kHz) 0 DE-EMPHASIS ERROR (fS = 32kHz) 0.01 0.008 0.006 –2 Error (dB) Level (dB) 0.004 –4 –6 0.002 0 –0.002 –0.004 –0.006 –8 –0.008 –0.01 –10 0 2 4 6 8 10 12 0 14 ® DF1704 2 4 6 8 Frequency (fS) Frequency ( fS) 4 10 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER DE-EMPHASIS (fS = 44.1kHz) 0 DE-EMPHASIS ERROR (fS = 44.1kHz) 0.01 0.008 –2 0.006 –4 Error (dB) Level (dB) 0.004 –6 0.002 0 –0.002 –0.004 –0.006 –8 –0.008 –0.01 –10 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 Frequency (fS) DE-EMPHASIS (fS = 48kHz) 0 10 12 14 16 18 20 Frequency (fS) DE-EMPHASIS ERROR (fS = 48kHz) 0.01 0.008 0.006 –2 Error (dB) Level (dB) 0.004 –4 –6 0.002 0 –0.002 –0.004 –0.006 –8 –0.008 –0.01 –10 0 2 4 6 8 10 12 14 16 18 20 22 0 Frequency (fS) 2 4 6 8 10 12 14 16 18 20 22 Frequency (fS) ® 5 DF1704 SYSTEM CLOCK REQUIREMENTS During the power-on reset period (1024 system clocks), the DF1704 outputs are forced LOW. For an external forced reset, the outputs are forced LOW during the initialization period (1024 system clocks), which occurs after the LOWto-HIGH transition of the RST pin as shown in Figure 3. The system clock of the DF1704 can be supplied by either an external clock signal at XTI (pin 6), or by the on-chip crystal oscillator. The system clock rate must run at 256fS, 384fS, 512fS, or 768fS, where fS is the audio sampling rate. It should be noted that a 768fS system clock cannot be used when fS = 96kHz. In addition, the on-chip crystal oscillator is limited to a maximum frequency of 24.576MHz. Table I shows the typical system clock frequencies for selected sample rates. 2.6V VDD 2.2V 1.8V The DF1704 includes a system clock detection circuit that determines the system clock rate in use. The circuit compares the system clock input (XTI) frequency with the LRCIN input rate to determine the system clock multiplier. Ideally, LRCIN and BCKIN should be derived from the system clock to ensure proper synchronization. If the phase difference between the system clock and LRCIN is larger than ±6 bit clock (BCKIN) periods, the synchronization of the system and LRCIN clocks will be performed automatically by the DF1704. Reset Reset Removal Internal Reset 1024 system clocks System Clock FIGURE 2. Internal Power-On Reset Timing. Timing requirements for the system clock input are shown in Figure 1. tRST ≥ 20ns tRST RST Reset tSCKH Reset Removal Internal Reset “H” 2.0V “L” 0.8V XTI 1024 system (XTI) clocks System Clock tSCKL System Clock Pulse Width HIGH System Clock Pulse Width LOW :tSCKIH :tSCKIL FIGURE 3. External Forces Reset Timing. :7ns min(1) :7ns min(1) AUDIO INPUT INTERFACE The audio input interface is comprised of BCKIN (pin 2), LRCIN (pin 28), and DIN (pin 1). NOTE: (1) For fS = 96kHz and SCK = 256fS, tSCKIH = 14ns (min) tSCKIL = 14ns (min) For fS ≠ 96kHz and SCK = 256fS, tSCKIH = 20ns (min) tSCKIL = 20ns (min) BCKIN is the input bit clock, which is used to clock data applied at DIN into the DF1704’s input serial interface. Input data at DIN is clocked into the DF1704 on the rising edge of BCKIN. The left/right clock, LRCIN, is used as a word latch for the audio input data. FIGURE 1. System Clock Timing. RESET The DF1704 has both an internal power-on reset circuit and a reset pin, RST (pin 14), for providing an external reset signal. The internal power-on reset is performed automatically when power is applied to the DF1704, as shown in Figure 2. The RST pin can be used to synchronize the DF1704 with a system reset signal, as shown in Figure 3. BCKIN can run at 32fS, 48fS, or 64fS, where fS is the audio sample frequency. LRCIN is run at the fS rate. Figures 4 (a) through 4 (c) show the input data formats, which are selected by hardware or software controls. Figure 5 shows the audio input interface timing requirements. SYSTEM CLOCK FREQUENCY (MHz) SAMPLING RATE FREQUENCY (fS) 256fS 384fS 512fS 768fS 32kHz 8.1920 12.2880 16.3840 24.5760 44.1kHz 11.2896 16.9340 22.5792 33.8688(1) 48kHz 12.2880 18.4320 24.5760 36.8640(1) 96kHz 24.5760(3) 36.8640(1) 49.1520(1) See Notes 1, 2 NOTES: (1) Maximum crystal oscillator frequency is 24.576MHz and cannot be used for these combinations. (2) 768fS system clock cannot be used with 96kHz sampling rate. (3) Use external system clock applied at XTI. TABLE I. Typical System Clock Frequencies. ® DF1704 6 (a) Standard Format (Sony Format); Lch = “H”, Rch = “L” 1/fS Lch Rch LRCIN BCKIN AUDIO DATA WORD = 16-BIT DIN 14 15 16 1 MSB AUDIO DATA WORD = 20-BIT DIN 18 19 20 1 MSB 22 23 24 1 1 15 16 2 LSB 2 AUDIO DATA WORD = 24-BIT DIN 15 16 2 19 20 1 2 19 20 23 24 1 2 23 24 LSB 2 MSB LSB MSB LSB (b) Left-Justified Format; Lch = “H”, Rch = “L” 1/fS Lch Rch LRCIN BCKIN AUDIO DATA WORD = 24-BIT DIN 1 2 22 3 MSB 23 24 1 2 LSB 22 3 MSB 23 24 1 2 3 1 2 1 2 LSB (c) I2S Data Format (Philips Format); Lch = “L”, Rch = “H” 1/fS Lch LRCIN Rch BCKIN AUDIO DATA WORD = 16-BIT DIN 1 MSB AUDIO DATA WORD = 24-BIT DIN 15 16 2 1 1 15 16 2 MSB LSB 23 24 2 MSB 1 LSB LSB 23 24 2 MSB LSB FIGURE 4. Audio Data Input Formats. LRCKIN 1.4V tBCH tBCL tLB BCKIN 1.4V tBL tBCY 1.4V DIN tDS tDH BCKIN Pulse Cycle Time tBCY 100ns (min) BCKIN Pulse Width HIGH tBCH 50ns (min) BCKIN Pulse Width LOW tBCL 50ns (min) BCKIN Rising Edge to LRCIN Edge tBL 30ns (min) LRCIN Edge to BCKIN Rising Edge tLB 30ns (min) DIN Set-up Time tDS 30ns (min) DIN Hold Time tDH 30ns (min) FIGURE 5. Audio Input Interface Timing. ® 7 DF1704 AUDIO OUTPUT INTERFACE The output data format used by the DF1704 for DOL and DOR is Binary Two’s Complement, MSB-first, right-justified audio data. Figures 6(a) and 6(b) show the output data formats for the DF1704. Figure 7 shows the audio output timing. The audio output interface includes BCKO (pin 26), WCKO (pin 25), DOL (pin 24), and DOR (pin 23). BCKO is the output bit clock and is used to clock data into an audio D/A converter, such as the PCM1704. DOL and DOR are the left and right audio data outputs. WCKO is the output word clock and is used to latch audio data words into an audio D/A converter. MODE CONTROL The DF1704 may be configured using either software or hardware control. The selection is made using the MODE input (pin 10). WCKO runs at a fixed rate of 8fS (8X oversampling) for all system clock rates. BCKO is fixed at 256fS for system clock rates of 256fS or 512fS. MODE SETTING MODE CONTROL SELECTION MODE = H MODE = L Software Mode Hardware Mode BCKO is fixed at 192fS for system clock rates of 384fS or 768fS. TABLE II. MODE Selection. (a) SYSTEM CLOCK: 256/512fS 1/8fS WCKO BCKO AUDIO DATA WORD = 16-BIT DOR 14 15 16 DOL 1 15 16 2 MSB AUDIO DATA WORD = 18-BIT DOR 16 17 18 DOL 1 LSB 17 18 2 MSB AUDIO DATA WORD = 20-BIT DOR 18 19 20 DOL 1 LSB 19 20 2 MSB AUDIO DATA WORD = 24-BIT DOR 22 23 24 DOL 1 LSB 23 24 2 MSB LSB (b) SYSTEM CLOCK: 384/768fS 1/8fS WCKO BCKO AUDIO DATA WORD = 16-BIT DOR 14 15 16 DOL 1 MSB AUDIO DATA WORD = 18-BIT DOR 16 17 18 DOL 1 1 LSB 19 20 2 MSB 1 LSB 23 24 2 MSB LSB FIGURE 6. Audio Output Data Format. ® DF1704 LSB 17 18 2 MSB AUDIO DATA WORD = 20-BIT DOR 18 19 20 DOL AUDIO DATA WORD = 24-BIT DOR 22 23 24 DOL 15 16 2 8 1 2 tWCKP WCKO 0.5VDD tBCKH tCKWK tBCKL 0.5VDD BCKO tBCKP tCKDO 0.5VDD DOL, R min typ max BCKO Period tBCKP BCKO Pulse Width High(4) tBCKH 20ns 100ns BCKO Pulse Width Low(4) tBCKL 20ns 100ns Delay Time BCKO Falling Edge to WCKO Valid tCKWK –5ns WCKO Period tWCKP Delay Time BCKO Falling Edge to DOL, R Valid tCKDO Rising Time of All Signals tR 7ns Falling Time of All Signals tF 7ns 1/256 fS or 1/192 fS 5ns 1/8 fS –5ns 5ns NOTES: (1) Timing measurement reference level is (VIH /VIL)/2. (2) Rising and falling time is measured from 10% to 90% of IN/OUT signals’ swing. (3) Load capacitance of all signals are 20pF. (4) Exceptions: fS = 96kHz and SCK = 256fS, tBCKH = 14ns (min) tBCKL = 14ns (min) FIGURE 7. Audio Output Data Format. Pins I2S, IW0, and IW1 are used to select the audio data input format and word length. Programmable Functions The DF1704 includes a number of programmable features, with most being accessible from either Hardware or Software mode. Table III summarizes the user programmable functions for both modes of operation. SOFTWARE (MODE = H) HARDWARE (MODE = L) RESET DEFAULT (Software Mode) Input Data Format Selection O O Standard Format Input Word Length Selection O O 16 Bits FUNCTION Output Word Length Selection O O 16 Bits LRCIN Polarity Selection O O Left/Right = High/Low Digital De-Emphasis O O OFF Soft Mute O O OFF Digital Attenuation O X 0dB, Independent L/R Sample Rate for De-Emphasis Function O O 44.1 kHz Filter Roll-Off Selection O O Sharp Roll-Off Selected CLKO Output Frequency Selection O O Same As XTI Input Pins OW0 and OW1 are used to select the output data word length. The DEM pin is used to enable and disable the digital deemphasis function. De-emphasis is only available for 32kHz, 44.1kHz, and 48kHz sample rates. Pins SF0 and SF1 are used to select the sample rate for the de-emphasis function. The SRO pin is used to select the digital filter response, either sharp or slow roll-off. The MUTE pin is used to enable or disable the soft mute function. The CKO pin is used to select the clock frequency seen at the CLKO pin, either XTI or XTI ÷ 2. The LRIP pin is used to select the polarity used for the audio input left/right clock, LRCIN. Finally, the RESV pin is not used by the current DF1704 design, but is reserved for future use. Legend: O = User Programmable, X = Not Available. TABLE III. User-Programmable Functions for Software and Hardware Mode. Software Mode Controls With MODE = H, the DF1704 may be configured by programming four internal registers in software mode. ML (pin 13), MC (pin 12), and MD (pin 11) make up the 3-wire software control port, and may be controlled using DSP or microcontroller general purpose I/O pins, or a serial port. Table V provides an overview of the internal registers, labeled MODE0 through MODE3. Hardware Mode Controls With MODE = L, the DF1704 may be configured by utilizing several user-programmable pins. The following is a brief summary of the pin functions. Table IV provides more details on setting the hardware mode controls. ® 9 DF1704 PIN NAME PIN NUMBER DESCRIPTION REGISTER NAME BIT NAME DESCRIPTION MODE0 AL[7:0] LDL A[1:0] res Attenuation Data for the Left Channel Attenuation Load Control for the Left Channel Register Address Reserved MODE1 AR[7:0] LDL A[1:0] res Attenuation Data for the Right Channel Attenuation Load Control for the Right Channel Register Address Reserved MODE2 MUT DEM IW[1:0] OW[1:0] A[1:0] res Soft Mute Control Digital De-Emphasis Control Input Data Format and Word Length Output Data Word Length Register Address Reserved MODE3 I2S LRP ATC SRO CKO SF[1:0] A[1:0] res Input Data Format (I2S or Standard/Left-Justified) LRCIN Polarity Attenuator Control, Dependent or Independent Digital Filter Roll-Off Selection (sharp or slow) CLKO Frequency Selection (XTI or XTI ÷ 2) Sample Rate Selection for De-Emphasis Function Register Address Reserved RESV 13 Reserved, Not Used LRIP 12 LRCIN Polarity LRIP = H: LRCIN= H = Left Channel, LRCIN= L = Right Channel LRIP = L: LRCIN= L = Left Channel, LRCIN = H = Right Channel CKO 11 CLKO Output Frequency CKO = H: CLKO Frequency = XTI/2 CKO = L: CLKO Frequency = XTI MUTE 15 Soft Mute Control: H = Mute Off, L = Mute On I2S IW0 IW1 3 4 5 Input Data Format Controls I2S L L L L H H IW1 L L H H L L IW0 L H L H L H INPUT FORMAT 16-Bit, Standard, MSB-First, Right-Justified 20-Bit, Standard, MSB-First, Right-Justified 24-Bit, Standard, MSB-First, Right-Justified 24-Bit, MSB-First, Left-Justified 16-Bit, I2S 24-Bit, I2S SRO 27 Digital Filter Roll-Off: H = Slow, L = Sharp OW0 OW1 19 20 Output Data Word Length Controls OW1 OW0 L L L H H L H H SF0 SF1 DEM 17 18 16 OUTPUT FORMAT 16-Bit, MSB-First 18-Bit, MSB-First 20-Bit, MSB-First 24-Bit, MSB-First NOTE: All reserved bits should be programmed to 0. TABLE V. Internal Register Mapping. Sample Rate Selection for the Digital De-Emphasis Control Register Addressing SF1 L L H H A[1:0], bits B10 and B9 of the 16-bit control data word, are used to indicate the register address to be written to by the current control port write cycle. Table VI shows how to address the internal registers using bits A[1:0] of registers MODE0 through MODE3. SF0 L H L H SAMPLING RATE 44.1kHz Reserved, Not Used 48kHz 32kHz Digital De-Emphasis: H = On, L = Off TABLE IV. Hardware Mode Controls. Figures 8 through 10 show more details regarding the control port data format and timing requirements. The data format for the control port is 16-bit, MSB-first, with Bit B15 being the MSB. A1 A0 REGISTER SELECTED 0 0 MODE0 0 1 MODE1 1 0 MODE2 1 1 MODE3 TABLE VI. Internal Register Addressing. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 MODE0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 MODE1 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 MODE2 res res res res res A1 A0 res res OW1 OW0 IW1 IW0 res DEM MUT MODE3 res res res res res A1 A0 res SF1 SF0 CKO res SRO ATC LRP I 2S FIGURE 8. Internal Mode Control Registers. ML MC MD B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 FIGURE 9. Software Interface Format. ® DF1704 10 tMLL tMHH ML(1) 1.4V tMCH tMLH tMCL tMLS 1.4V MC(2) tMCY LSB MD tMDS 1.4V tMDH MC Pulse Cycle Time tMCY 100ns (min) MC Pulse Width LOW tMCL 40ns (min) MC Pulse Width HIGH tMCH 40ns (min) MD Hold Time tMDH 40ns (min) MD Set-Up Time tMDS 40ns (min) ML Low Level Time tMLL 40ns + 1SYSCLK(3) (min) ML High Level Time tMHH 40ns + 1SYSCLK(3) (min) ML Hold Time(2) tMLH 40ns (min) ML Set-Up Time(3) tMLS 40ns (min) NOTES: (1) ML rising edge to the next MC rising edge. (2) MC rising edge for LSB to ML rising edge. (3) SYSCK: System Clock Cycle. FIGURE 10. Software Interface Timing Requirements. MODE0 Register MODE1 Register The MODE0 register is used to set the attenuation data for the Left output channel, or DOL (pin 24). The MODE1 register is used to set the attenuation data for the Right output channel, or DOR (pin 23). When ATC = 1 (Bit B2 of Register MODE3 = 1), the Left channel attenuation data AL[7:0] is used for both the Left and Right channel attenuators. When ATC = 1 (Bit B2 of Register MODE3 = 1), the Left channel attenuation data AL[7:0] of register MODE0 is used for both the Left and Right channel attenuators. When ATC = 0, (Bit B2 of Register MODE3 = 0), Left channel attenuation data is taken from AL[7:0] of register MODE0, and Right channel attenuation data is taken from AR[7:0] of register MODE1. When ATC = 0, (Bit B2 of Register MODE3 = 0), Left channel attenuation data is taken from AL[7:0] of register MODE0, and Right channel attenuation data is taken from AR[7:0] of register MODE1. AL[7:0] AR[7:0] LDL Left Channel Attenuator Data, where AL7 is the MSB and AL0 is the LSB. Attenuation Level is given by: Right Channel Attenuator Data, where AR7 is the MSB and AR0 is the LSB. Attenuation Level is given by: ATTEN = 0.5 • (DATA – 255)dB ATTEN = 0.5 • (DATA – 255)dB For For For For For For For For DATA DATA DATA DATA = = = = FFh, ATTEN = –0dB FEh, ATTEN = –0.5dB 01h, ATTEN = –127.5dB 00h, ATTEN = infinity = Mute Left Channel Attenuation Data Load Control. This bit is used to simultaneously set attenuation levels of both the Left and Right channels. LDR DATA DATA DATA DATA = = = = FFh, ATTEN = –0dB FEh, ATTEN = –0.5dB 01h, ATTEN = –127.5dB 00h, ATTEN = infinity = Mute Right Channel Attenuation Data Load Control. This bit is used to simultaneously set attenuation levels of both the Left and Right channels. When LDR = 1, the Right channel output level is set by the data in AR[7:0], or by the data in bits AL[7:0] of register MODE0. The Left channel output level is set to the most recently programmed data in bits AL[7:0] of register MODE0. When LDL = 1, the Left channel output level is set by the data in AL[7:0]. The Right channel output level is set by the data in AL[7:0], or the most recently programmed data in bits AR[7:0] of register MODE1. When LDL = 0, the Left channel output data remains at its previously programmed level. When LDR = 0, the Right channel output data remains at its previously programmed level. ® 11 DF1704 MODE2 Register ATC The MODE2 register is used to program various functions: MUT Soft Mute Function. When MUT = 0, Soft Mute is ON for both Left and Right channels. When MUT = 1, Soft Mute is OFF for both Left and Right channels. DEM When ATC = 0, the Left and Right channel attenuator data is independent. When ATC = 1, the Left and Right channel attenuators use common data. Digital De-Emphasis Function. When DEM = 0, de-emphasis is OFF. When DEM = 1, de-emphasis is ON. IW[1:0] OW[1:0] SRO I2 S IW1 IW0 Description 0 0 0 16-Bit Data, Standard Format (MSB-First, Right-Justified) 0 0 1 20-Bit Data, Standard Format 0 1 0 24-Bit Data, Standard Format 0 1 1 24-Bit Data, MSB-First, Left-Justified 1 0 0 16-Bit Data, I2S Format 1 0 1 24-Bit Data, I2S format 1 1 0 Reserved 1 1 1 Reserved CKO SF[1:0] Output Data Word Length. SF1 SF0 Description 0 0 1 1 44.1 kHz Reserved 48 kHz 32 kHz 0 1 0 1 PCB LAYOUT GUIDELINES OW1 OW0 Description 0 0 1 1 16-Bit 18-Bit 20-Bit 24-Bit Data, Data, Data, Data, In order to obtain the specified performance from the DF1704 and its associated D/A converters, proper printed circuit board layout is essential. Figure 11 shows two approaches for obtaining the best audio performance. MSB-First MSB-First MSB-First MSB-First Figure 11(a) shows a standard, mixed signal layout scheme. The board is divided into digital and analog sections, each with its own ground. The ground areas should be put on a split-plane, separate from the routing and power layers. The DF1704 and all digital circuitry should be placed over the digital section, while the audio DACs and analog circuitry should be located over the analog section of the board. A common connection between the digital and analog grounds is required and is done at a single point as shown. Input Data Format. When I2S = 1, the I2S formats are enabled. LRCIN Polarity Selection. For Figure 11(a), digital signals should be routed from the DF1704 to the audio DACs using short, direct connections to reduce the amount of radiated high-frequency energy. If necessary, series resistors may be placed in the clock and data signal paths to reduce or eliminate any overshoot or undershoot present on these signals. A value of 50Ω to 100Ω is recommended as a starting point, but the designer should experiment with the resistor values in order to obtain the best results. When LRP = 0, Left channel is HIGH and Right channel is LOW. When LRP = 1, Left channel is LOW and Right channel is HIGH. ® DF1704 Sampling Frequency Selection for the De-Emphasis Function. APPLICATIONS INFORMATION When I2S = 0, standard or left-justified formats are enabled. LRP CLKO Output Frequency Selection. When CKO = 0, the CLKO frequency is the same as the clock at the XTI input. When CKO =1, the CLKO frequency is half of the XTI input clock frequency. MODE3 Register The MODE3 register is used to program various functions. I2 S Digital Filter Roll-Off Selection. When SRO = 0, sharp roll-off is selected. When SRO = 1, slow roll-off is selected. Input Data Format and Word Length. 0 1 0 1 Attenuator Control. This bit is used to determine whether the Left and Right channel attenuators operate with independent data, or use common data (the Left channel data in bits AL[7:0] of register MODE0). 12 BASIC CIRCUIT CONNECTIONS Figure 11(b) shows an improved method for high performance, mixed signal board layout. This method adds digital isolation between the DF1704 and the audio DACs, and provides complete isolation between the digital and analog sections of the board. The Burr-Brown ISO150 dual digital coupler provides excellent isolation, and operates at speeds up to 80Mbps. Figures 12 and 13 show basic circuit connections for the DF1704. Figure 12 shows connections for Hardware mode controls, while Figure 13 shows connections for Software mode controls. Notice the placement of C1 and C2 in both figures, as they are physically close to the DF1704. TYPICAL APPLICATIONS The DF1704 will typically be used in high performance audio equipment, in conjunction with high performance audio D/A converters. Figure 14 shows a typical application circuit example, employing the DF1704, a digital audio receiver, and two PCM1704 24-bit, 96kHz audio DACs. POWER SUPPLIES AND BYPASSING The DF1704 requires a single +5V power supply for operation. The power supply should be bypassed by a 10µF and 0.1µF parallel capacitor combination. The capacitors should be placed as close as possible to VDD (pin 22). Aluminum electrolytics or tantalum capacitors can be used for the 10µF value, while ceramics may be used for the 0.1µF value. ® 13 DF1704 (a) Layout Without Isolation Digital Power Supplies Common Ground Connection Analog Power Supplies WCKO BCKO DAC DOL DOR DF1704 DAC Digital Section Analog Section Split Ground Plane (b) Layout With Isolation Digital Power Supplies Analog Power Supplies WCKO BCKO ISO150 DAC DOL DOR DF1704 DAC ISO150 Digital Section Analog Section = DGND Split Ground Plane FIGURE 11. PCB Layout Model. ® DF1704 14 = AGND DF1704 1 DIN 2 BCKIN 3 I2S BCKO 26 4 IW0 WCKO 25 5 IW1 DOL 24 6 XTI DOR 23 7 XTO VDD 22 8 VSS NC 21 9 CLKO OW1 20 10 MODE OW0 19 Audio Data and Clock Source 22pF XTAL LRCIN 28 SRO 27 22pF (optional) 11 MD/CKO SF1 18 12 MC/LRIP SF0 17 13 ML/RESV DEM 16 14 RST Digital Logic or Manual Controls D/A Converters or Digital Couplers + C1 0.1µF C2 10µF +5V MUTE 15 7 7 = DGND NOTE: Do not allow pins 3-5, 11-20, and 27 to float. These pins should be manually connected to VDD or DGND (hardwired, switch, jumper) or actively driven by logic. FIGURE 12. Basic Circuit Connections, Hardware Control. DF1704 Audio Data and Clock Source 22pF XTAL 1 DIN 2 BCKIN 3 I2S BCKO 26 4 IWO WCKO 25 5 IW1 DOL 24 6 XTI DOR 23 7 XTO VDD 22 8 VSS NC 21 9 CLKO OW1 20 10 MODE OW0 19 LRCIN 28 SRO 27 22pF (optional) +5V Controller or Logic 11 MD SF1 18 12 MC SF0 17 13 ML DEM 16 14 RST D/A Converters or Digital Couplers C1 0.1µF + +5V C2 10µF MUTE 15 = DGND FIGURE 13. Basic Circuit Connection, Software Control. ® 15 DF1704 DIGITAL SECTION WORD CLOCK ANALOG SECTION DF1704 Digital Audio Input Digital Audio Receiver DATA 1 +5V Micro Controller or Logic BCKIN SRO 27 WCLK 3 I2S BCKO 26 DATA 4 IWO WCKO 25 5 IW1 DOL 24 6 XTI DOR 23 7 XTO VDD 22 8 VSS 9 CLKO OW1 20 10 MODE OW0 19 11 MD SF1 18 12 MC SF0 17 13 ML Post Filter Left Channel Out I/V Post Filter Right Channel Out PCM1704 DATA DEM 16 MUTE 15 10µF + 0.1µF = DGND +5V FIGURE 14. DF1704 Typical Application Circuit. ® DF1704 I/V BCLK WCLK System Reset D/A Converter NC 21 14 RST +5V PCM1704 LRCIN 28 2 SYSTEM CLOCK Host Interface DIN BCLK BIT CLOCK 16 D/A Converter