INA110 ® Fast-Settling FET-Input INSTRUMENTATION AMPLIFIER FEATURES APPLICATIONS ● ● ● ● ● ● ● MULTIPLEXED INPUT DATA ACQUISITION SYSTEM ● FAST DIFFERENTIAL PULSE AMPLIFIER ● HIGH SPEED GAIN BLOCK ● AMPLIFICATION OF HIGH IMPEDANCE SOURCES LOW BIAS CURRENT: 50pA max FAST SETTLING: 4µs to 0.01% HIGH CMR: 106dB min; 90dB at 10kHz INTERNAL GAINS: 1, 10, 100, 200, 500 VERY LOW GAIN DRIFT: 10 to 50ppm/°C LOW OFFSET DRIFT: 2µV/°C ● LOW COST ● PINOUT SIMILAR TO AD524 AND AD624 DESCRIPTION The INA110 is a versatile monolithic FET-input instrumentation amplifier. Its current-feedback circuit topology and laser trimmed input stage provide excellent dynamic performance and accuracy. The INA110 settles in 4µs to 0.01%, making it ideal for high speed or multiplexed-input data acquisition systems. Internal gain-set resistors are provided for gains of 1, 10, 100, 200, and 500V/V. Inputs are protected for differential and common-mode voltages up to ±VCC. Its very high input impedance and low input bias current make the INA110 ideal for applications requiring input filters or input protection circuitry. 1 –In © 1986 Burr-Brown Corporation 13 4.44kΩ 10kΩ X 10 10kΩ 10 A1 12 404Ω 16 201Ω 11 80.2Ω Sense X 100 (1) 20kΩ X 200 9 A3 X 500 Output 20kΩ 3 RG 10kΩ 10kΩ 6 A2 Ref 2 +In The INA110 is available in 16-pin plastic and ceramic DIPs, and in the SOL-16 surface-mount package. Military, industrial and commercial temperature range grades are available. International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • INA110 FET Input FET Input 4 Input Offset Adjust 5 8 7 +VCC –VCC 14 15 Output Offset Adjust NOTE: (1) Connect to RG for desired gain. • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 PDS-645E Printed in U.S.A. September, 1993 SPECIFICATIONS ELECTRICAL At +25°C, ±VCC = 15VDC, and RL = 2kΩ, unless otherwise specified. INA110AG PARAMETER CONDITIONS GAIN Range of Gain Gain Equation(1) Gain Error, DC: G = 1 G = 10 G = 100 G = 200 G = 500 Gain Temp. Coefficient: G = 1 G = 10 G = 100 G = 200 G = 500 Nonlinearity, DC: G = 1 G = 10 G = 100 G = 200 G = 500 OUTPUT Voltage, RL = 2kΩ Current Short-Circuit Current Capacitive Load MIN TYP 1 * 0.002 0.01 0.02 0.04 0.1 ±3 ±4 ±6 ±10 ±25 ±0.001 ±0.002 ±0.004 ±0.006 ±0.01 Over Temperature Over Temperature ±10 ±5 Stability INA110BG, SG MIN 800 * * G = 1 + [40k/(RG + 50Ω)] * 0.02 0.005 0.05 0.01 0.1 0.02 0.2 0.05 0.5 * ±10 ±2 ±10 ±3 ±20 ±5 ±30 ±10 ±50 ±0.0005 ±0.005 ±0.001 ±0.005 ±0.002 ±0.01 ±0.003 ±0.01 ±0.005 ±0.02 0.04 0.1 0.2 0.4 1 ±20 ±20 ±40 ±60 ±100 ±0.01 ±0.01 ±0.02 ±0.02 ±0.04 ±12.7 ±25 ±25 5000 * * TYP INA110KP, KU MAX MAX * * * * MIN TYP * * * * * * * * * * * * * * * * * * * MAX UNITS * V/V V/V % % % % % ppm/°C ppm/°C ppm/°C ppm/°C ppm/°C % of FS % of FS % of FS % of FS % of FS * * * * * * * * * * * * * * V mA mA pF VOLTAGE(2) INPUT OFFSET Initial Offset: G, P ±(100 + ±(500 + 1000/G) 5000/G) ±(50 + 600/G) ±(250 + 3000/G) * ±(200 + ±(1000 + 2000/G) 5000/G) * U vs Temperature VCC = ±6V to ±18V vs Supply BIAS CURRENT Initial Bias Current Initial Offset Current Impedance: Differential Common-Mode VOLTAGE RANGE Range, Linear Response CMR with 1kΩ Source Imbalance: G=1 G = 10 G = 100 G = 200 G = 500 Each Input VIN Diff. = 0V(3) DC DC DC DC DC ±(2 + 20/G) ±(4 + 60/G) ±(5 + 100/G) ±(30 + 300/G) ±(1 + 10/G) ±(2 + 30/G) ±(2 + 50/G) ±(10 + 180/G) 20 2 5x1012||6 2x1012||1 100 50 10 1 * * 50 25 ±10 ±12 70 87 100 100 100 90 104 110 110 110 80 96 106 106 106 100 112 116 116 116 * µV µV µV/°C * * µV/V * * * * * * pA pA Ω || pF Ω || pF * * V * * * * * * * * * * dB dB dB dB dB INPUT NOISE(4) Voltage, fO = 10kHz fB = 0.1Hz to 10Hz Current, fO = 10kHz 10 1 1.8 * * * * * * nV/√Hz µVp-p fA/√Hz OUTPUT NOISE(4) Voltage, fO = 10kHz fB = 0.1Hz to 10Hz 65 8 * * * * nV/√Hz µVp-p 2.5 2.5 470 240 100 * * * * * * * * * * MHz MHz kHz kHz kHz * * * * * * * * * * * * * * DYNAMIC RESPONSE Small Signal: G = 1 G = 10 G = 100 G = 200 G = 500 Full Power Slew Rate Settling Time: 0.1%, G = 1 G = 10 G = 100 G = 200 G = 500 –3dB VOUT = ±10V, G = 2 to 100 G = 2 to 100 VO = 20V Step 190 12 270 17 * * 4 2 3 5 11 ® INA110 2 * * kHz V/µs µs µs µs µs µs SPECIFICATIONS (CONT) ELECTRICAL At +25°C, ±VCC 15VDC, and RL = 2KΩ, unless otherwise specified. INA110AG PARAMETER CONDITIONS DYNAMIC RESPONSE (CONT) Settling Time: 0.01%,G = 1 G = 10 G = 100 G = 200 G = 500 Recovery(5) MIN TYP MAX 5 3 4 7 16 1 12.5 7.5 7.5 12.5 25 VO = 20V Step 50% Overdrive POWER SUPPLY Rated Voltage Voltage Range Quiescent Current ±6 ±15 MIN INA110KP, KU TYP MAX * * * * * * * * * * * MIN TYP * –25 +85 –55 –65 +125 +150 * –55 * * ±3 * 100 MAX * * * * * +125 * * 0 +70 –25 –40 +85 +85 * * UNITS µs µs µs µs µs µs * * * * * * * ±18 ±4.5 VO = 0V TEMPERATURE RANGE Specification: A, B, K S Operation Storage θJA INA110BG, SG * * * V V mA °C °C °C °C °C/W * Same as INA110AG. NOTES: (1) Gains other than 1, 10, 100, 200, and 500 can be set by adding an external resistor, RG, between pin 3 and pins 11, 12 and 16. Gain accuracy is a function of RG and the internal resistors which have a ±20% tolerance with 20ppm/°C drift. (2) Adjustable to zero. (3) For differential input voltage other than zero, see Typical Performance Curves. (4) VNOISE RTI = √VN2 INPUT + (VN OUTPUT/Gain)2. (5) Time required for output to return from saturation to linear operation following the removal of an input overdrive voltage. PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Top View Supply Voltage .................................................................................. ±18V Input Voltage Range .......................................................................... ±VCC Operating Temperature Range: G ................................. –55°C to +125°C P, U ............................... –25°C to +85°C Storage Temperature Range: G .................................... –65°C to +150°C P, U .................................. –40°C to +85°C Lead Temperature (soldering, 10s): G, P ..................................... +300°C (soldering, 3s): U ........................................... +260°C Output Short Circuit Duration ............................... Continuous to Common DIP/SOIC –In 1 16 x200 +In 2 15 Output Offset Adj. RG 3 14 Output Offset Adj. Input Offset Adj. 4 13 x10 Input Offset Adj. 5 12 x100 Reference 6 11 x500 –VCC 7 10 Output Sense +VCC 8 9 Output PACKAGE INFORMATION MODEL INA110AG INA110BG INA110SG INA110KP INA110KU PACKAGE PACKAGE DRAWING NUMBER(1) 16-Pin Ceramic DIP 16-Pin Ceramic DIP 16-Pin Ceramic DIP 16-Pin Plastic DIP SOL-16 SOIC 109 109 109 180 211 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION MODEL INA110AG INA110BG INA110SG INA110KP INA110KU PACKAGE TEMPERATURE RANGE 16-Pin Ceramic DIP 16-Pin Ceramic DIP 16-Pin Ceramic DIP 16-Pin Plastic DIP SOL-16 SOIC –25°C to +85°C –25°C to +85°C –55°C to +125°C 0°C to +70°C 0°C to +70°C The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 INA110 DICE INFORMATION 15 14 13 12 11 10 16 9 1 8 2 7 3A 3B FUNCTION 1 2 3A,3B 4 5 6 7 8 9 10 11 12 13 14 15 16 –In +In RG (connect both) Input Offset Adjust Input Offset Adjust Reference –VCC +VCC Output Output Sense x500 x100 x10 Output Offset Adjust Output Offset Adjust x200 Pads 3A and 3B must be connected. Substrate Bias: Internally connected to –VCC power supply. 5 4 PAD 6 7 MECHANICAL INFORMATION INA110 DIE TOPOGRAPHY Die Size Die Thickness Min. Pad Size MILS (0.001") MILLIMETERS 139 x 89 ±5 20 ±3 4x4 3.53 x 2.26 ±0.13 0.51 ±0.08 0.10 x 0.10 Backing Gold TYPICAL PERFORMANCE CURVES At TA = +25°C, and ±VCC = 15VDC, unless otherwise noted. OUTPUT SWING vs SUPPLY ±16 ±12 ±13 Output Voltage (V) Input Voltage Range (V) INPUT VOLTAGE RANGE vs SUPPLY ±15 ±9 RL = 2kΩ ±10 ±7 ±6 ±4 ±3 ±6 ±12 ±9 ±15 ±6 ±18 ±9 OUTPUT SWING vs LOAD RESISTANCE ±15 ±18 BIAS CURRENT vs SUPPLY ±16 25 Input Bias Current (pA) Output Voltage (V) ±12 Power Supply Voltage (V) Power Supply Voltage (V) ±12 ±8 ±4 0 20 15 10 5 0 0 400 800 1.2k 1.6k ±6 2M ® INA110 ±9 ±12 Power Supply Voltage (V) Load Resistance (Ω) 4 ±15 ±18 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, ±VCC = 15VDC, unless otherwise noted. GAIN vs FREQUENCY BIAS CURRENT vs TEMPERATURE 1k 100nA G = 500 G = 200 G = 100 100 Gain (V/V) Input Bias Current 10nA 1pA 100pA G = 10 10 10pA G=1 1 1pA –55 –25 5 35 65 95 10 125 100 1k 10k 10M 120 G = 500 Power Supply Rejection (dB) G = 500 Common-Mode Rejection (dB) 1M POWER SUPPLY REJECTION vs FREQUENCY CMR vs FREQUENCY 120 100 G = 200 80 G = 100 60 G = 10 40 G=1 20 100 G = 200 80 G = 100 60 G = 10 40 G=1 20 0 0 1 10 100 1k 10k 100k 1 1M LARGE SIGNAL TRANSIENT RESPONSE (G = 100) Output Voltage (V) 0 –10 10 100 1k 10k 100k 1M SMALL SIGNAL TRANSIENT RESPONSE (G = 100) 10 0 10 Frequency (Hz) Frequency (Hz) Output Voltage (V) 100k Frequency (Hz) Temperature (°C) 20 100 0 –100 0 Time (µs) 10 20 Time (µs) ® 5 INA110 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, ±VCC = 15VDC, unless otherwise noted. SETTLING TIME vs GAIN (0.01%, 20V Step) OUTPUT NOISE VOLTAGE vs FREQUENCY 1000 Output Noise Voltage (nV/√Hz) Settling Time (µs) 20 15 10 5 500 200 100 50 20 0 10 1 10 100 1k 1 100 1k Frequency (Hz) INPUT NOISE VOLTAGE vs FREQUENCY COMMON-MODE VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE 10k 12 100 Common-Mode Voltage (V) 50 20 10 5 9 6 3 2 0 1 1 10 100 1k 0 10k 3 6 WARM-UP DRIFT vs TIME 50 40 30 20 10 0 0 1 3 2 Time (minutes) ® INA110 9 Differential Input Voltage x Gain (V) = VO Frequency (Hz) Change In Input Offset Voltage (µV) Input Noise Voltage (nV/√Hz) 10 Gain (V/V) 6 4 5 12 DISCUSSION OF PERFORMANCE INA110’s input (RTI) is the offset of the input stage plus the offset of the output stage divided by the gain of the input stage. This allows specification of offset independent of gain. A simplified diagram of the INA110 is shown on the first page. The design consists of the classical three operational amplifier configuration using current-feedback type op amps with precision FET buffers on the input. The result is an instrumentation amplifier with premium performance not normally found in integrated circuits. +VCC –VCC Input Offset Adjust 100kΩ 100kΩ The input section (A1 and A2) incorporates high performance, low bias current, and low drift amplifier circuitry. The amplifiers are connected in the noninverting configuration to provide high input impedance (1012Ω). Laser-trimming is used to achieve low offset voltage. Input cascoding assures low bias current and high CMR. Thin-film resistors on the integrated circuit provide excellent gain accuracy and temperature stability. 4 ∆VIN 10 10 9 VOUT FIGURE 2. Offset Adjustment Circuit. For systems using computer autozeroing techniques, neither offset nor offset drift are of concern. In many other applications, the factory-trimmed offset gives excellent results. When greater accuracy is desired, one adjustment is usually sufficient. In high gains (>100) adjust only the input offset, and in low gains the output offset. For higher precision in all gains, both can be adjusted by first selecting high gain and adjusting input offset and then low gain and adjusting output offset. The offset adjustment will, however, add to the drift by approximately 0.33µV/°C per 100µV of input offset voltage that is adjusted. Therefore, care should be taken when considering use of adjustment. Output offsetting can be accomplished as shown in Figure 3 by applying a voltage to the reference (pin 6) through a buffer. This limits the resistance in series with pin 6 to minimize CMR error. Be certain to keep this resistance low. Note that the offset error can be adjusted at this reference point with no appreciable degradation in offset drift. Sense INA110 15 INA110 6 Figure 1 shows the proper connections for power supply and signal. Supplies should be decoupled with 1µF tantalum capacitors as close to the amplifier as possible. To avoid gain and CMR errors introduced by the external circuit, connect grounds as indicated, being sure to minimize ground resistance. Resistance in series with the reference (pin 6) will degrade CMR. To maintain stability, avoid capacitance from the output to the gain set, offset adjust, and input pins. ∆VIN 14 2 BASIC POWER SUPPLY AND SIGNAL CONNECTIONS 1 13 12 16 11 3 2 5 1 The output section (A3) is connected in a unity-gain difference amplifier configuration. Precision matching of the four 10kΩ resistors, especially over temperature and time, assures high common-mode rejection. x10 x100 x200 x500 Output Offset Adjust 9 VOUT 6 RL 8 7 1 1µF 10 VOUT = ∆VIN G ∆VIN +VCC –VCC INA110 2 9 VOUT +VCC 6 R1 1µF OPA177 VOFFSETTING FIGURE 1. Basic Circuit Connection. VOFFSETTING R2 –VCC R3 VOUT = VOFFSETTING + ∆VIN G. With ±VCC = 15V, R1 = 100kΩ, R2 = 1MΩ. R3 = 10kΩ, VOFFSETTING = ±150mV. OFFSET ADJUSTMENT Figure 2 shows the offset adjustment circuit for the INA110. Both the offset of the input stage and output stage can be adjusted separately. Notice that the offset referred to the FIGURE 3. Output Offsetting. ® 7 INA110 are eliminated since they are inside the feedback loop. Proper connection is shown in Figure 1. When more current is to be supplied, a power booster can be placed within the feedback loop as shown in Figure 5. Buffer errors are minimized by the loop gain of the output amplifier. GAIN SELECTION Gain selection is accomplished by connecting the appropriate pins together on the INA110. Table I shows possible gains from the internal resistors. Keep the connections as short as possible to maintain accuracy. CONNECT PIN 3 TO PIN GAIN GAIN ACCURACY (%) The following gains have guaranteed accuracy: 1 none 0.02 10 13 0.05 100 12 0.1 200 16 0.2 500 11 0.5 The following gains have typical accuracy as shown: 300 12, 16 0.25 600 11, 12 0.25 700 11, 16 2 800 11, 12, 16 2 GAIN DRIFT (ppm/°C) R1 1 10 10 20 30 50 10 ∆VIN INA110 R2 VOUT 9 6 2 Output Stage Gain 10 40 40 80 R3 (R2 || 20kΩ) + R1 + R3 = R2 || 20kΩ FIGURE 4. Gain Adjustment of Output Stage Using H Pad Attenuator. TABLE I. Internal Gain Connections. Gains other than 1, 10, 100, 200, and 500 can be set by adding an external resistor, RG, between pin 3 and pins 12, 16, and 11. Gain accuracy is a function of RG and the internal resistors which have a ±20% tolerance with 20ppm/°C drift. The equation for choosing RG is shown below. 40k RG = – 50Ω G –1 Sense 1 10 ∆VIN INA110 2 9 VOUT 3553 6 RL IL = 100mA Gain can also be changed in the output stage by adding resistance to the feedback loop shown in Figure 4. This is useful for increasing the total gain or reducing the input stage gain to prevent saturation of input amplifiers. FIGURE 5. Current Boosting the Output. LOW BIAS CURRENT OF FET INPUT ELIMINATES DC ERRORS Because the INA110 has FET inputs, bias currents drawn through input source resistors have a negligible effect on DC accuracy. The picoamp levels produce no more than microvolts through megohm sources. Thus, input filtering and input series protection are readily achievable. The output gain can be changed as shown in Table II. Matching of R1 and R3 is required to maintain high CMR. R2 sets the gain with no effect on CMR. OUTPUT STAGE GAIN R1 AND R3 R2 2 5 10 1.2kΩ 1kΩ 1.5kΩ 2.74kΩ 511Ω 340Ω A return path for the input bias currents must always be provided to prevent charging of stray capacitance. Otherwise, the output can wander and saturate. A 1MΩ to 10MΩ resistor from the input to common will return floating sources such as transformers, thermocouples, and AC-coupled inputs (see Applications section). TABLE II. Output Stage Gain Control. COMMON-MODE INPUT RANGE It is important not to exceed the input amplifiers’ dynamic range (see Typical Performance Curves). The differential input signal and its associated common-mode voltage should not cause the output of A1 and A2 (input amplifiers) to exceed approximately ±10V with ±15V supplies or nonlinear operation will result. Such large common-mode voltages, when the INA110 is in high gain, can cause saturation of the input stage even though the differential input is very small. This can be avoided by reducing the input stage gain and increasing the output stage gain with an H pad attenuator (see Figure 4). DYNAMIC PERFORMANCE The INA110 is a fast-settling FET input instrumentation amplifier. Therefore, careful attention to minimize stray capacitance is necessary to achieve specified performance. High source resistance will interact with input capacitance to reduce the overall bandwidth. Also, to maintain stability, avoid capacitance from the output to the gain set, offset adjust, and input pins. OUTPUT SENSE An output sense has been provided to allow greater accuracy in connecting the load. By attaching this feedback point to the load at the load site, IR drops due to load currents that Applications with balanced-source impedance will provide the best performance. In some applications, mismatched source impedances may be required. If the impedance in the ® INA110 8 negative input exceeds that in the positive input, stray capacitance from the output will create a net negative feedback and improve the circuit stability. If the impedance in the positive input is greater, the feedback due to stray capacitance will be positive and instability may result. The degree of positive feedback depends upon source impedance imbalance, operating gain, and board layout. The addition of a small bypass capacitor of 5pF to 50pF directly between the inputs of the IA will generally eliminate any positive feedback. CMR errors due to the input impedance mismatch will also be reduced by the capacitor. Another distinct advantage of the INA110 is the high frequency CMR response. High frequency noise and sharp common-mode transients will be rejected. To preserve AC CMR, be sure to minimize stray capacitance on the input lines. Matching the RCs in the two inputs will help to maintain high AC CMR. APPLICATIONS In addition to general purpose uses, the INA110 is designed to accurately handle two important and demanding applications: (1) inputs with high source impedances such as capacitance/crystal/photodetector sensors and low-pass filters and series-input protection devices, and (2) rapidscanning data acquisition systems requiring fast settling time. Because the user has access to the output sense, current sources can also be constructed using a minimum of external components. Figures 6 through 19 show application circuits. The INA110 is designed for fast settling with easy gain selection. It has especially excellent settling in high gain. It can also be used in fast-settling unity-gain applications. As with all such amplifiers, the INA110 does exhibit significant gain peaking when set to a gain of 1. It is, however, unconditionally stable. The gain peaking can be cancelled by band-limiting the negative input to 400kHz with a simple external RC circuit for applications requiring flat response. CMR is not affected by the addition of the 400kHz RC in a gain of 1. +15V 1 8 X200 16 3 10 INA110 VOUT 6 2 Transducer 9 7 –15V FIGURE 6. Transformer-Coupled Amplifier. +15V +15V 1 X100 12 3 Thermocouple Transducer or Other Floating Source 2 1MΩ 1 8 10 INA110 9 VOUT X200 ∆VIN 6 16 3 7 2 –15V 8 10 INA110 9 VOUT 6 7 –15V 100Ω OPA121 FIGURE 7. Floating Source Instrumentation Amplifier. Divider minimizes degredation of CMR due to distributed capacitance on the input lines. FIGURE 8. Instrumentation Amplifier with Shield Driver. ® 9 INA110 VREF +15V 75kΩ(1) 1 8 X500 11 300Ω 1µF(1) 3 10 INA110 (1) 75kΩ 2 9 VOUT 6 7 –15V FET input allows low-pass filtering with minimal effect on DC accuracy. NOTE: (1) Larger resistors and a smaller capacitor can be used. FIGURE 9. Bridge Amplifier with 1Hz Low-Pass Input Filter. +15V +15V 1µF 10MΩ X100 12 3 100mVp-p 10 INA110 10MΩ 9 In 1 In 2 VOUT 6 2 1µF 1 8 8 7 B-B MPC800 1 1 In 15 In 16 X10 8 13 3 10 INA110 9 VOUT SHC5320 6 2 7 –15V –15V FIGURE 12. Rapid-Scanning-Rate Data Acquisition Channel with 5µs Settling to 0.01%. FIGURE 10. AC-Coupled Differential Amplifier for Frequencies Greater Than 0.016Hz. +15V +15V X10 X100 X200 X500 ∆VIN 1 13 12 16 11 3 2 Decoder/ Latch/Driver 1 8 X10 13 8 10 9 3 VOUT VIN 6 5.34MΩ(1) 7 5.34MΩ(1) 10 INA110 2 1000pF –15V 9 6 7 –15V 2.67MΩ(1) A0 A1 A2 500pF NOTE: Use manual switch or low resistance relay. Layout is critical (see section on Dynamic Performance). FIGURE 13. 60Hz Input Notch Filter. ® INA110 500pF NOTE: (1) For 50Hz use 3.16MΩ and 6.37MΩ. 2kΩ potentiometer sets Q. FIGURE 11. Programmable-Gain Instrumentation Amplifier (Precision Noninverting or Inverting Buffer with Gain). 10 VOUT 2kΩ +15V R1 +15V D1 V1 D2 –15V +15V ∆VIN R2 V2 V1 1 X200 8 16 3 D3 10 INA110 ∆VIN 9 V2 X100 3 D4 990kΩ –15V 10 INA110 9 VOUT 6 2 10kΩ For lower voltage, lower resistor noise: R1 = R2 = 20kΩ, D1 – D4 = FDH300 (1nA leakage) 8 12 10kΩ 7 –15V Overall G = 1 1 VOUT 6 2 +15V 990kΩ 7 –15V For higher voltage, higher resistor noise: R1 = R2 = 100kΩ, D1 – D4 = 2N4117A (1pA leakage) Common-mode range = ±1000V. CMR is dependent on ratio matching of external input resistors. Matching of RCs on inputs will affect CMR, but can be optimized by trimming R1 or R2. FIGURE 14. Input-Protected Instrumentation Amplifier. FIGURE 15. High Common-Mode Voltage Differential Amplifier. –15V +15V +15V 13 1 8 X10 13 ∆VIN 3 RG 10 INA110 6 7 8 9 6 2 16 15 PGA102 VOUT 2 7 1 3 4 –15V CODE GAIN TYPICAL 0.01% SETTLING TIME 00 01 10 10 100 1000 6µs 6µs 12µs X10 X100 PGA Gain Select FIGURE 16. Digitally-Controlled Fast-Settling Programmable Gain Instrumentation Amplifier. +15V +15V ∆VIN X10 X100 X200 X500 RG 1 13 12 16 11 3 2 +15V 8 X10 X100 X200 X500 RG R 10 INA110 9 2N2222A 6 7 –15V 1kΩ 1 13 12 16 11 3 2 8 10 INA110 9 6 7 + ∆VOUT – –15V R IOUT RL ∆VIN IOUT = (∆VIN) (G) (1/10k + 1/R) For 0mA to 20mA output, R = 50.25Ω with (∆VIN) (G) = 1V FIGURE 17. Differential Input FET Buffered Current Source. X10 X100 X200 X500 RG 1 13 12 16 11 3 2 8 10 INA110 9 6 7 FIGURE 18. Differential Input/Differential Output Amplifier. ® 11 INA110