® ISO103 ISO 103 Low-Cost, Internally Powered ISOLATION AMPLIFIER FEATURES APPLICATIONS ● SIGNAL AND POWER IN ONE DOUBLE-WIDE (0.6") SIDE-BRAZED PACKAGE ● 5600Vpk TEST VOLTAGE ● 1500Vrms CONTINUOUS AC BARRIER RATING ● WIDE INPUT SIGNAL RANGE: –10V to +10V ● WIDE BANDWIDTH: 20kHz Small Signal, 20kHz Full Power ● BUILT-IN ISOLATED POWER: ±10V to ±18V Input, ±50mA Output ● MULTICHANNEL SYNCHRONIZATION CAPABILITY (TTL) ● BOARD AREA ONLY 0.72in.2 (4.6cm2) ● MULTICHANNEL ISOLATED DATA ACQUISITION ● ISOLATED 4-20mA LOOP RECEIVER AND POWER ● POWER SUPPLY AND MOTOR CONTROL ● GROUND LOOP ELIMINATION +VC V IN –VC Com 1 Gnd 1 Sense Duty Cycle Modulator Duty Cycle Demodulator Com 2 –VCC2 Sync* +VCC2 Sync +VCC1 Ps Gnd Rectifiers Filters V OUT Oscillator Driver –VCC1 Enable Gnd 2 *Ground if not used DESCRIPTION The ISO103 isolation amplifier provides both signal and power across an isolation barrier. The ceramic non-hermetic hybrid package with side-brazed pins contains a transformer-coupled DC/DC converter and a capacitor-coupled signal channel. Extra power is available on the isolated input side for external input conditioning circuitry. The converter is protected from shorts to ground with an internal current limit, and the soft-start feature limits the initial currents from the power source. Multiple-channel synchronization can be accomplished by applying a TTL clock signal to paralleled Sync pins. The Enable con- trol is used to turn off transformer drive while keeping the signal channel demodulator active. This feature provides a convenient way to reduce quiescent current for low power applications. The wide barrier pin spacing and internal insulation allow for the generous 1500Vrms continuous rating. Reliability is assured by 100% barrier breakdown testing that conforms to UL1244 test methods. Low barrier capacitance minimizes AC leakage currents. These specifications and built-in features make the ISO103 easy to use, as well as providing for compact PC board layouts. International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1989 Burr-Brown Corporation PDS-1004E Printed in U.S.A. August, 1999 SPECIFICATIONS ELECTRICAL At TA = +25°C and VCC2 = ±15V, ±15mA output current unless otherwise noted. ISO103 PARAMETER ISOLATION Rated Continuous Voltage(1) AC, 60Hz DC Test Breakdown, 100% AC, 60Hz Isolation-Mode Rejection Barrier Impedance Leakage Current GAIN Nominal Initial Error Gain vs Temperature Nonlinearity INPUT OFFSET VOLTAGE Initial Offset vs Temperature vs Power Supplies vs Output Supply Load SIGNAL INPUT Voltage Range Resistance CONDITIONS MIN TMIN to TMAX TMIN to TMAX 10s 1500Vrms, 60Hz 2121VDC 1500 2121 5657 240Vrms, 60Hz VO = –10V to 10V VO = –5V to 5V 1 ±0.12 ±60 ±0.026 ±0.009 VCC2 = ±10V to ±18V IO = 0 to ±50mA ±20 ±300 0.9 ±0.3 SIGNAL OUTPUT Voltage Range Current Drive Ripple Voltage, 800kHz Carrier Ripple Current Rated Output Voltage Output Load Regulation Line Regulation Output Voltage vs Temperature Voltage Balance Error, ±VCC1 Voltage Ripple (800kHz) Output Capacitive Load Sync Frequency TEMPERATURE RANGE Specification Operating Storage TYP MAX UNITS ✻ ✻ ✻ ✻ ✻ Vrms VDC Vpk dB dB Ω || pF µA 2 ±0.3 ±100 ±0.075 ✻ ±0.08 ±20 ±0.018 ✻ ±0.15 ±50 ±0.050 ±0.025 V/V % FSR ppm/°C % FSR %FSR ±60 ±500 ✻ ✻ ✻ ✻ ✻ ✻ mV µV/°C mV/V mV/mA ±15 200 ✻ ✻ ✻ V kΩ ±10 ±5 ±12.5 ±15 25 5 1000 4 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V mA mVp-p mVp-p pF µV/√Hz ✻ ✻ ✻ kHz V/µs µs 400Ω/4.7nF (See Figure 4) 20 1.5 75 0.1%, –10/10V IO = ±15mA IO = 0mA No Filter CIN = 1µF Load = 15mA 50mA Balanced Load 100mA Single-Ended Loads Balanced Load MIN ±10 Capacitive Load Drive Voltage Noise POWER SUPPLIES Rated Voltage, VCC2 Voltage Range Input Current ISO103B MAX ✻ ✻ ✻ 130 160 1012 || 9 1 Output Voltage in Range FREQUENCY RESPONSE Small Signal Bandwidth Slew Rate Settling Time TYP ±10 ±14.25 10 10 ±15 +90/–4.5 +60/–4.5 60 3 ±15 No External Capacitors CEXT = 1µF 0.3 1.12 2.5 0.05 50 5 Sync-Pin Grounded (2) 1.6 ✻ ±18 ±15.75 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ 1 –25 –25 –25 ✻ ✻ ✻ ✻ +85 +85 +125 ✻ ✻ ✻ ✻ ✻ ✻ V V mA mA mAp-p mAp-p V V V %/mA V/V mV/°C % mVp-p mVp-p µF MHz °C °C °C ✻ Specifications same as ISO103. NOTE: (1) Conforms to UL1244 test methods. 100% tested at 1500Vrms for 1 minute. (2) If using external synchronization with a TTL-level clock, frequency should be between 1.2MHz and 2MHz with a duty-cycle greater than 25%. ® ISO103 2 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Supply Without Damage .................................................................... ±18V VIN, Sense Voltage ............................................................................. ±50V Com 1 to Gnd 1 or Com 2 to Gnd 2 .............................................. ±200mV Enable, Sync ........................................................................... 0V to +VCC2 Continuous Isolation Voltage ..................................................... 1500Vrms VISO, dv/dt ..................................................................................... 20kV/µs Junction Temperature ...................................................................... 150°C Storage Temperature ...................................................... –25°C to +125°C Lead Temperature,10s .................................................................... 300°C Output Short to Gnd 2 Duration ............................................... Continuous ±VCC1 to Gnd 1 Duration .......................................................... Continuous +VC 1 24 Ps Gnd +VCC1 2 23 Gnd 1 –VCC1 3 22 VIN –VCC1 4 ELECTROSTATIC DISCHARGE SENSITIVITY Any integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. 21 Com 1 Com 2 9 16 –VCC2 VOUT 10 15 Sync* Sense 11 14 +VCC2 Gnd 2 12 13 Enable *Operation requires this pin be grounded or driven with TTL levels. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) ISO103 24-Pin DIP 231 SPECIFIED TEMPERATURE RANGE –25°C to +85°C PACKAGE MARKING ORDERING NUMBER(2) TRANSPORT MEDIA NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “ISO103/2K5” will get a single 2500piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 ISO103 TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC2 = ±15VDC, ±15mA output current, unless otherwise noted. IMR/LEAKAGE vs FREQUENCY RECOMMENDED RANGE OF ISOLATION VOLTAGE Non-Specified Signal Operation 2100V at 75kHz 100 Operational Region 10 IMR 1m 100µ 120 Leakage at 240Vrms 110 10µ 100 1µ 90 1 100 1k 10k 100k 1M 10 10M DISTORTION vs FREQUENCY 3 0 1 –3 Gain (dB) 3 VO = 2Vp-p 0.1 VO = 20Vp-p 0.03 0.01 20 100 1k 1k 10k 100n 100k GAIN/PHASE vs FREQUENCY 10 0.3 100 Isolation Voltage Frequency (Hz) Isolation Voltage Frequency (Hz) THD+N (%) Leakage at 1500Vrms 130 45 PHASE –6 90 –9 135 –12 180 –15 100 10k 20k 0 GAIN Frequency (Hz) 1k 10k Phase Shift (°) 2.1k 1k Isolation-Mode Rejection (dB) Maximum Isolation Voltage (Vpk) Barrier Voltage Rating Barrier Leakage Current (Arms) 10m 140 10k 100k Small Signal Frequency (Hz) ISOLATED POWER SUPPLY LOAD REGULATION AND EFFICIENCY LARGE SIGNAL TRANSIENT RESPONSE 20 17 60 10 0 –10 16 45 Output Voltage Balanced Loads 15 30 Output Voltage Single-Ended Loads 14 15 13 –20 0 50 100 0 0 0 Time (µs) 10 20 20 40 30 60 ±V CC1 Supply Output Current (mA) ® ISO103 4 40 80 Efficiency (%) ±V CC1 Output Voltage (V) Output Voltage (V) Balanced Load Efficiency TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VCC2 = ±15VDC, ±15mA output current, unless otherwise noted. ISOLATION POWER SUPPLY VOLTAGE vs TEMPERATURE ISOLATED POWER SUPPLY LINE REGULATION 19 2 18 17 ±15mA Load 1 ∆ V CC2 (%) 15 14 1.12V/V 13 0 12 –1 11 10 9 –2 10 11 12 13 14 15 16 17 18 19 –25 0 25 +V CC2 (V) 50 75 100 Temperature (°C) ISOLATED SUPPLY VOLTAGE AND V OS vs SYNC FREQUENCY 250 5 VCC1 125 2.5 VOS 0 0 ∆ V CC1 (mV) 9 ∆ V OS (mV) +V CC1 (V) 16 –125 –2.5 –250 –5 1 1.5 2 2.5 Sync Frequency (MHz) ® 5 ISO103 The ISO103 isolation amplifier contains a transformercoupled DC/DC converter that is powered from the output side of the isolation amplifier. All power supply pins (1, 2, 3, 4, 14, and 16) of the ISO103 have an internal 0.1µF capacitor to ground. L1 is used to slow down fast changes in the input current to the DC/DC converter. C1 is used to help regulate the voltage ripple caused by the current demands of the converter. L1, C1, and C2 are optional, however, recommended for low noise applications. The DC/DC converter creates an unregulated ±15V output to ±VCC1. If the ISO103 is the only device using the DC/DC converter for power, pins 1 and 2 and pins 3 and 4 can be connected directly without CO or LO in the circuit. If an external capacitor is used in this configuration, it should not exceed 1µF. This configuration is possible because the isolation amplifier and the DC/DC converter are synchronized internally. If additional devices are powered by the DC/DC converter of the ISO103, the application may require that the ripple voltage of the ISO103 converter be attenuated. In which case, LO and CO should be added to the circuit. The inductor is used to attenuate the ripple current and a higher value capacitor can be used to reduce the ripple voltage even further. THEORY OF OPERATION The block diagram on the front page shows the isolation amplifier’s synchronized signal and power configuration, which eliminate beat frequency interference. A proprietary 800kHz oscillator chip, power MOSFET transformer drivers, patented square core wirebonded transformer, and single chip diode bridge provide power to the input side of the isolation amplifier as well as external loads. The signal channel capacitively couples a duty-cycle encoded signal across the ceramic high-voltage barrier built into the package. A proprietary transmitter-receiver pair of integrated circuits, laser trimmed at wafer level, and coupled through a pair of matched “fringe” capacitors, result in a simple, reliable design. SIGNAL AND POWER CONNECTIONS Figure 1 shows the proper power supply and signal connections. All power supply pins should be bypassed as shown with the π filter for +VCC2, an option recommended if more than ±15mA are drawn from the isolated supply. Separate rectifier output pins (±VCC1) and amplifier supply input pins (±VC) allow additional ripple filtering and/or regulation. The separate input and output common pins and output sense are low current inputs tied to the signal source ground, output ground, and output load, respectively, to minimize errors due to IR drop in long conductors. Otherwise, connect Com 1 to Gnd 1, Com 2 to Gnd 2, and Sense to VOUT at the ISO103 socket. The enable pin may be left open if the ISO103 is continuously operated. If not, a TTL low level will disable the internal DC/DC converter. The Sync input must be grounded for unsynchronized operation while a 1.2MHz to 2MHz TTL clock signal provides synchronization of multiple units. OPTIONAL GAIN AND OFFSET ADJUSTMENTS Rated gain accuracy and offset performance can be achieved with no external adjustments, but the circuit of Figure 2a may be used to provide a gain trim of ±0.5% for the values shown; greater range may be provided by increasing the size of R1 and R2. Every 2kΩ increase in R1 will give an additional 1% adjustment range, with R2 ≥ 2R1. If safety or convenience dictate location of the adjustment potentiometer on the other side of the barrier from the position shown in Figure 2a, the position of R1 and R2 may be reversed. Isolation Barrier –VCC2 +VCC2 VIN Com C1 L I (3) C2 1µF 1µF + 24 23 PS Gnd 1 Gnd *Optional Filtering: For LO 0 ≤ LO < 10µH CO < 1µF For LO LO ≥ 10µH, < 10Ω CO ≤ 10µF 22 VIN 21 Com 1 16 –VCC2 15 Sync 14 13 +VCC2 Enable (2) 10µF Tantalum (1) ISO103 +VC +VCC1 1 2 –VCC1 3 CO 4 Com 2 9 VOUT Sense Gnd 2 10 CO L O* + –VC 11 12 Sense VOUT L O* Com 2 Supply Outputs Com Return – FIGURE 1. Signal and Power Connections. ® ISO103 NOTES: (1) Enable = pin open or TTL high. (2) Ground sync if not used. (3) π filter reduces ripple current; L1 = 10µH, <10Ω. 6 RL Gains greater than 1 may be obtained by using the circuit of Figure 2b. Note that the effect of input referred errors will be multiplied at the output in proportion to the increase in gain. Also, the small-signal bandwidth will be decreased in inverse proportion to the increase in gain. In most instances, a precision gain block at the input of the isolation amplifier will provide better overall performance. Sense 22 11 400Ω VIN VOUT 10 21 9 4.7nF 2kΩ 1kΩ FIGURE 4. Ripple Reduction. R2 22 11 R1 VOUT VIN MULTICHANNEL SYNCHRONIZATION Synchronization of multiple ISO103s can be accomplished by connecting pin 15 of each device to an external TTL level oscillator, as shown in Figure 7. The PWS750-1 oscillator is convenient because its nominal synchronizing output frequency is 1.6MHz, resulting in a 800kHz carrier in the ISO103 (its nominal unsynchronized value). The open collector output typically switches 7.5mA to a 0.2V low level so that the external pull-up resistor can be chosen for different pull-up voltages as shown in Figure 7. The number of channels synchronized by one PWS750-1 is determined by the total capacitance of the sync voltage conductors. They must be less than 1000pF to ensure TTL level switching at 800kHz. At higher frequencies the capacitance must be proportionally lower. Customers can supply their own TTL level synchronization logic provided the frequency is between 1.2MHz and 2MHz, and the duty cycle is greater than 25%. Multichannel synchronization with reduced power dissipation for applications requiring less than ±15mA from VCC1 is accomplished by driving both the Sync input pin (15) and Enable pin (13) with the TTL oscillator as shown in Figure 5. 10 9 21 FIGURE 2a. Gain Adjust. Sense 22 11 VIN VOUT 10 R1 9 21 R2 Gain = 1 + ( R1 R2 + R1 200k ) FIGURE 2b. Gain Setting. Figure 3 shows a method for trimming VOS of the ISO103. This circuit may be applied to either Signal Com (input or output) as desired for safety or convenience. With the values shown, ±15V supplies and unity gain, the circuit will provide ±150mV adjustment range and 0.25mV resolution with a typical trim potentiometer. The output will have some sensitivity to power supply variations. For a ±100mV trim, power supply sensitivity is 8mV/V at the output. FIGURE 3. VOS Adjust. ISOLATION BARRIER VOLTAGE The typical performance of the ISO103 under conditions of barrier voltage stress is indicated in the first two performance curves—Recommended Range of Isolation Voltage and IMR/ Leakage vs Frequency. At low barrier modulation levels, errors can be determined by the IMRR characteristic. At higher barrier voltages, typical performance is obtained as long as the dv/dt across the barrier is below the shaded area in the first curve. Otherwise, the signal channel will be interrupted, causing the output to distort, and/or shift DC level. This condition is temporary, with normal operation resuming as soon as the transient subsides. Permanent damage to the integrated circuits occurs only if transients exceed 20kV/µs. Even in this extreme case, the barrier integrity is assured. OPTIONAL OUTPUT FILTER Figure 4 shows an optional output ripple filter that reduces the 800kHz ripple voltage to <5mVp-p without compromising DC performance. The small signal bandwidth is extended above 30kHz as a result of this compensation. HIGH VOLTAGE TESTING The ISO103 was designed to reliably operate with 1500Vrms continuous isolation barrier voltage. To confirm barrier integrity, a two-step breakdown test is performed on 100% of the units. First, a 5600V peak, 60Hz barrier potential is +VCC1 or +VCC2 1M Ω 100k Ω 10k Ω Signal Com 1 or Signal Com 2 –VCC1 or –VCC2 ® 7 ISO103 applied for 10s to verify that the dielectric strength of the insulation is above this level. Following this exposure, a 1500Vrms, 60Hz potential is applied for one minute to conform to UL1244. Life-test results show reliable operation under continuous rated voltage and maximum operating temperature conditions. +VCC2 I Q (Reduced) 15 14 13 TTL Osc. ISO103 External Load <15mA 1 2 3 4 + 12 – FIGURE 5. Reduced Power Dissipation. i O (mA) = 0.4221RT – 46.4 98.5Ω 16 2N2222A TO-18 0.01µF 1µF 10 11 12 15 RCV 14 2 420 5 3 7 4 PT100 RTD 1µF 750Ω 11 10 8 3 – 12 5 XTR101 9 6 + +15V + 1/2 W 119.4Ω 1mA 1mA + 22 24 23 21 1 14 ISO 3 0.01µF 2 4 103 16 10 11 12 9 VOUT 15 4 1µF 2.5kΩ 1µF –15V – iO VO 20mA 5V 4 T 50 50 FIGURE 6. Isolated 4-20mA Instrument Loop. ® ISO103 T 0 150°C 8 150°C –VCC2 +VCC2 VIN1 24 23 22 21 16 15 14 ISO Channel 1 103 Sync 1.6MHz 12 14 11 PWS750-1 3 1 2 3 9 10 4 7 11 12 R + – R= VIN2 24 23 22 21 16 7.5 kΩ 15 14 ISO Channel 2 VCC2 NOTES: (1) PWS750-1 can sync > 20 ISO103. (2) Bypass supplies as shown in Figure 1. 103 VOUT1 1 2 3 4 9 10 11 12 + – VOUT2 Additional Channels FIGURE 7. Synchronized-Multichannel Isolation. ® 9 ISO103