® OPA3 OPA3680 680 OPA3 680 For most current data sheet and other product information, visit www.burr-brown.com Triple, Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER With Disable TM FEATURES APPLICATIONS ● ● ● ● ● ● ● ● ● ● ● ● ● ● WIDEBAND +5V OPERATION: 220MHz (G = +2) HIGH OUTPUT CURRENT: 150mA OUTPUT VOLTAGE SWING: ±4.0V HIGH SLEW RATE: 1800V/µs LOW SUPPLY CURRENT: 6.4mA/ch LOW DISABLED CURRENT: 300µA/ch ENABLE/DISABLE TIME: 25ns/100ns VIDEO LINE DRIVING xDSL LINE DRIVER HIGH-SPEED IMAGING CHANNELS ADC BUFFERS PORTABLE INSTRUMENTS TRANSIMPEDANCE AMPLIFIERS ACTIVE FILTERS DESCRIPTION current than competing products. System power may be reduced further using the optional disable control pin. Leaving this disable pin open, or holding it high, will operate the OPA3680 normal. If pulled low, the OPA3680 supply current drops to less than 300µA/ch while the output goes into a high impedance state. This feature may be used for either power savings or to implement video MUX applications. The OPA3680 represents a major step forward in unity gain stable, voltage-feedback op amps. A new internal architecture provides slew rate and full power bandwidth previously found only in wideband current-feedback op amps. A new output stage architecture delivers high currents with a minimal headroom requirement. These give exceptional single-supply operation. Using a single +5V supply, the OPA3680 can deliver a 1V to 4V output swing with over 80mA drive current and 150MHz bandwidth. This combination of features makes the OPA3680 an ideal RGB line driver or single-supply ADC input driver. The OPA3680’s low 6.4mA/ch supply current is precisely trimmed at 25°C. This trim, along with low temperature drift, guarantees lower maximum supply OPA3680 RELATED PRODUCTS Voltage Feedback Current Feedback Fixed Gain SINGLES DUALS TRIPLES OPA680 OPA681 OPA682 OPA2680 OPA2681 OPA2682 OPA3680 OPA3681 OPA3682 1pF 49.9Ω VIN 1pF 249Ω 249Ω 249Ω 249Ω VOUT 1/3 OPA3680 49.9Ω R 75.0Ω 49.9Ω 1/3 OPA3680 C 330pF R 75.0Ω 49.9Ω 1/3 OPA3680 C 330pF Buffered Analog Delay Line (100ns) International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1998 Burr-Brown Corporation PDS-1434C Printed in U.S.A. October, 1999 SPECIFICATIONS: VS = ±5V RF = 250Ω, RL = 100Ω, and G = +2, (Figure 1 for AC performance only), RF = 25Ω for G = +1, unless otherwise noted. OPA3680E, U TYP PARAMETER AC PERFORMANCE (Figure 1) Small-Signal Bandwidth Gain Bandwidth Product Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise/Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd Harmonic 3rd Harmonic Crosstalk Input Voltage Noise Input Current Noise Differential Gain Differential Phase DC PERFORMANCE(4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Average Bias Current Drift (magnitude) Input Offset Current Average Offset Current Drift INPUT Common-Mode Input Range (CMIR)(5) Common-Mode Rejection Ratio (CMRR) Input Impedance Differential-Mode Common-Mode OUTPUT Voltage Output Swing Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance DISABLE Power-Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current GUARANTEED +25°C(2) 0°C to 70°C(3) –40°C to +85°C(3) 210 20 200 200 20 200 190 20 200 1400 1200 900 CONDITIONS +25°C G = +1, VO = 0.5Vp-p, RF = 25Ω G = +2, VO = 0.5Vp-p G = +10, VO = 0.5Vp-p G ≥ 10 G = +2, VO < 0.5Vp-p VO < 0.5Vp-p G = +2, VO = 5Vp-p G = +2, 4V Step G = +2, VO = 0.5V Step G = +2, VO = 4V Step G = +2, VO = 0 ≥ 2V Step G = +2, VO = 0 ≥ 2V Step G = +2, f = 5MHz, VO = 2Vp-p RL = 100Ω RL ≥ 500Ω RL = 100Ω RL ≥ 500Ω Input Referred, f = 5MHz, All Hostile f > 1MHz f > 1MHz G = +2, NTSC, VO = 1.4Vp, RL = 150 G = +2, NTSC, VO = 1.4Vp, RL = 150 400 220 30 300 30 4 175 1800 1.4 2.8 12 8 VO = 0V, RL = 100Ω VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V 58 ±1.0 ±5.0 +8 +15 ±0.1 ±0.8 ±3.5 59 ±3.4 VCM = ±1.0V –80 –90 –77 –90 –58 4.8 2.5 0.05 0.03 ±4.0 ±3.9 +190 –150 0.03 Disable Low VDIS = 0V, Each Channel G = +2, RL = 150Ω G = +2, RL = 150Ω VDIS = 0V MHz MHz MHz MHz MHz dB MHz V/µs ns ns ns ns typ min min min typ typ typ min max max typ typ C B B B C C C B B B C C dBc dBc dBc dBc dBc nV/√Hz pA/√Hz % deg typ typ typ typ typ max max typ typ C C C C C B B C C 5.9 3.0 6.1 3.6 54 52 ±5.5 ±10 +20 –70 ±1.2 ±1 50 ±6.5 ±10 +35 –150 ±1.5 ±1.5 dB mV µV/°C µA nA/°C µA nA/°C min max max max max max max A A B A B A B ±3.3 53 ±3.2 53 V dB min min A A kΩ || pF MΩ || pF typ typ C C ±3.6 ±3.3 +80 –80 V V mA mA min min min min typ A A A A C typ typ typ typ typ typ typ min max max C C C C C C C A A A 56 ±3.8 ±3.7 +160 –135 ±3.7 ±3.6 +140 –130 3.5 1.7 160 3.6 1.6 160 3.7 1.5 160 µA ns ns dB pF mV mV V V µA ±6 ±6 7.0 6.0 58 ±6 7.2 5.3 58 V V mA mA dB typ max max min min C A A A A –40 to +85 °C typ C 100 100 °C/W °C/W typ typ C C –300 100 25 70 4 ±50 ±20 3.3 1.8 100 G = +2, 5MHz MIN/ TEST MAX LEVEL(1) 5.3 2.8 190 || 0.6 3.2 || 0.9 No Load 100Ω Load VO = 0 VO = 0 G = +2, f = 100kHz UNITS POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Range Max Quiescent Current Min Quiescent Current Power Supply Rejection Ratio (+PSRR) ±5 VS = ±5V, Each Channel VS = ±5V, Each Channel Input Referred 6.4 6.4 65 THERMAL CHARACTERISTICS Specified Operating Range U, E Package Thermal Resistance, θJA U SO-16 E SSOP-16 6.8 6.0 60 NOTES: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature = ambient for 25°C guaranteed specifications. (3) Junction temperature = ambient at low temperature limit: junction temperature = Ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMR specification at ±CMIR limits. ® OPA3680 2 SPECIFICATIONS: VS = +5V RF = 250Ω, RL = 100Ω to VS /2, G = +2, (Figure 2 for AC performance only), RF = 25Ω for G = +1, unless otherwise noted. OPA3680E, U TYP Gain Bandwidth Product Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise Time Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd Harmonic 3rd Harmonic Input Voltage Noise Input Current Noise Differential Gain Differential Phase +25°C(2) 0°C to 70°C(3) –40°C to +85°C(3) 160 20 200 160 19 190 140 18 180 700 670 550 CONDITIONS +25°C G = +1, VO < 0.5Vp-p G = +2, VO < 0.5Vp-p G = +10, VO < 0.5Vp-p G ≥ 10 G = +2, VO < 0.5Vp-p VO < 0.5Vp-p G = +2, VO = 2Vp-p G = +2, 2V Step G = +2, VO = 0.5V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 5MHz, VO = 2Vp-p RL = 100Ω RL ≥ 500Ω RL = 100Ω RL ≥ 500Ω f > 1MHz f > 1MHz G = +2, NTSC, VO = 1.4Vp, RL = 150 to VS /2 G = +2, NTSC, VO = 1.4Vp, RL = 150 to VS /2 300 220 25 250 20 5 175 1000 1.6 2.0 12 8 VO = 0V, RL = 100Ω VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V 58 ±1.0 ±6.5 +8 +16 ±0.1 ±0.7 1.5 3.5 59 1.6 3.4 56 PARAMETER AC PERFORMANCE (Figure 2) Small-Signal Bandwidth GUARANTEED DC PERFORMANCE(4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Average Bias Current Drift (magnitude) Input Offset Current Average Offset Current Drift INPUT Least Positive Input Voltage(5) Most Positive Input Voltage(5) Common-Mode Rejection Ratio (CMRR) Input Impedance Differential-Mode Common-Mode OUTPUT Most Positive Output Voltage Least Positive Output Voltage Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance DISABLE Power-Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current POWER SUPPLY Specified Single Supply Operating Voltage Maximum Single Supply Operating Voltage Max Quiescent Current Min Quiescent Current Power Supply Rejection Ratio (+PSRR) VCM = 2.5V –70 –80 –71 –84 5 2.5 0.06 0.03 Disable Low VDIS = 0V, Each Channel G = +2, 5MHz G = +2, RL = 150Ω, VIN = VS/2 G = +2, RLP = 150Ω, VIN = VS/2 VDIS = 0V C B C B C C C B C C C C dBc dBc dBc dBc nV/√Hz pA/√Hz % deg typ typ typ typ max max typ typ C C C C B B C C 54 52 ±7.5 –10 +21 –52 ±1.0 ±0.5 50 ±9.0 –12 +37 –80 ±1.2 ±1.0 dB mV µV/°C µA nA/°C µA nA/°C min max max max max max max A A B A B A B 1.7 3.3 53 1.8 3.2 52 V V dB min max min A A A kΩ || pF MΩ || pF typ typ C C V V V V mA mA min min min min min min typ A A A A A A C µA ns ns dB pF mV mV V V µA typ typ typ typ typ typ typ min max typ C C C C C C C A A C V V mA mA dB typ max max min typ C A A A C –40 to +85 °C typ C 100 100 °C/W °C/W typ typ C C –250 100 25 65 4 ±50 ±20 3.3 1.8 100 5.1 5.1 55 TEMPERATURE RANGE Specification: U, E Thermal Resistance, θJA U SO-16 E SSOP-16 typ min min min typ typ typ min typ typ typ typ 6.2 3.4 3.8 3.7 1.2 1.3 +110 –80 3.6 3.5 1.4 1.5 +110 –70 3.5 3.4 1.5 1.7 +60 –50 3.5 1.7 3.6 1.6 3.7 1.5 12 6.0 4.0 12 6.0 4.0 12 6.0 3.8 5 VS = +5V, Each Channel VS = +5V, Each Channel Input Referred MHz MHz MHz MHz MHz dB MHz V/µs ns ns ns ns 6 3.5 4 3.9 1 1.1 +150 –110 0.03 G = +2, f = 100kHz MIN/ TEST MAX LEVEL(1) 5.5 3 92 || 1.4 2.2 || 1.5 No Load RL = 100Ω, 2.5V No Load RL = 100Ω, 2.5V UNITS NOTES: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature = ambient for 25°C guaranteed specifications. (3) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMR specification at ±CMIR limits. ® 3 OPA3680 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Power Supply ............................................................................... ±6.5VDC Internal Power Dissipation ................................ See Thermal Information Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range: U, E ................................ –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C Junction Temperature (TJ ) ........................................................... +175°C Top View SSOP-16/SO-16 OPA3680 ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. –IN A 1 16 DIS A +IN A 2 15 +VS DIS B 3 14 OUT A –IN B 4 13 –VS +IN B 5 12 OUT B DIS C 6 11 +VS –IN C 7 10 OUT C +IN C 8 9 –VS PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER OPA3680E SSOP-16 Surface Mount 322 –40°C to +85°C " " " " OPA3680U SO-16 Surface Mount 265 " " " TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA OPA3680E OPA3680E/250 Tape and Reel " OPA3680E/2K5 Tape and Reel –40°C to +85°C OPA3680U OPA3680U Rails " " OPA3680U/2K5 Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “OPA3680E/2K5” will get a single 2500-piece Tape and Reel. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® OPA3680 4 TYPICAL PERFORMANCE CURVES: VS = ±5V At TA = +25°C, G = +2, RF = 250Ω, and RL = 100Ω, unless otherwise noted. See Figure 1. SMALL-SIGNAL FREQUENCY RESPONSE 6 VO = 0.5Vp-p VO = 1Vp-p 12 0 VO = 2Vp-p 9 G = +2 –3 –6 –9 G = +5 –12 –15 6 Gain (3dB/div) Normalized Gain (3dB/div) 3 LARGE-SIGNAL FREQUENCY RESPONSE 15 G = +1 RF = 25Ω 3 VO = 7Vp-p 0 –3 VO = 4Vp-p –6 G = +10 –18 –9 –21 –12 –24 –15 0.5 10 100 0.5 500 10 Frequency (MHz) SMALL-SIGNAL PULSE RESPONSE LARGE-SIGNAL PULSE RESPONSE G = +2 VO = 5Vp-p +3 Output Voltage (1V/div) Output Voltage (100mV/div) G = +2 VO = 0.5Vp-p 300 200 100 0 –100 –200 +2 +1 0 –1 –2 –3 –300 –4 –400 Time (5ns/div) Time (5ns/div) LARGE-SIGNAL DISABLE/ENABLE RESPONSE 4.0 2.0 0 Output Voltage VO (0.4V/div) 2.0 1.6 0.8 G = +2 VIN = +1V –45 –50 Feedthrough (5dB/div) VDIS VDIS (2V/div) DISABLED FEEDTHROUGH vs FREQUENCY 6.0 0 500 +4 400 0.4 100 Frequency (MHz) VDIS = 0 –55 –60 –65 –70 Forward Reverse –75 –80 –85 –90 –95 1 Time (50ns/div) 10 100 Frequency (MHz) ® 5 OPA3680 TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.) At TA = +25°C, G = +2, RF = 250Ω, and RL = 100Ω, unless otherwise noted. See Figure 1. HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs NON-INVERTING GAIN –50 –50 VO = 2Vp-p f = 5MHz Harmonic Distortion (dBc) Harmonic Distortion (dBc) f = 5MHz –60 –70 3rd Harmonic –80 2nd Harmonic –90 –60 2nd Harmonic –70 3rd Harmonic –80 –90 0.1 1 5 1 Gain Magnitude (V/V) HARMONIC DISTORTION vs INVERTING GAIN HARMONIC DISTORTION vs FREQUENCY –50 –50 VO = 2Vp-p f = 5MHz VO = 2Vp-p –60 2nd Harmonic –70 3rd Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) 10 Output Voltage (Vp-p) –80 –60 –70 3rd Harmonic –80 2nd Harmonic –90 –90 1 10 0.1 Frequency (MHz) HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs SUPPLY VOLTAGE 10 20 11 12 –50 –50 VO = 2Vp-p f0 = 5MHz Harmonic Distortion (dBc) Harmonic Distortion (dBc) 1 Gain Magnitude (V/V) –60 –70 3rd Harmonic –80 2nd Harmonic VO = 2Vp-p f0 = 5MHz –60 –70 3rd Harmonic –80 2nd Harmonic –90 –90 10 100 5 1000 ® OPA3680 6 7 8 9 10 Total Supply Voltage (V) RL (Ω) 6 TYPICAL PERFORMANCE CURVES: VS = ±5V At TA = +25°C, G = +2, RF = 250Ω, and RL = 100Ω, unless otherwise noted. See Figure 1. INPUT VOLTAGE AND CURRENT NOISE DENSITY TWO-TONE, 3rd-ORDER SPURIOUS LEVEL 100 –40 10 Voltage Noise 3rd-Order Spurious Level (dBc) Voltage Noise (nV/√Hz) Current Noise (pA/√Hz) 50MHz 4.8nV/√Hz Current Noise 2.5pA/√Hz –50 –60 20MHz –70 10MHz –80 Load Power at matched 50Ω load 1 –90 100 1k 10k 100k 1M 10M –8 –6 –4 Frequency (Hz) RECOMMENDED RS vs CAPACITIVE LOAD 2 4 6 8 10 Gain-to-Capacitive Load (3dB/div) 12 30 25 20 15 10 5 0 10pF/22.2Ω Signal Gain = +2 Noise Gain = +3 9 100pF/20Ω 6 3 0 VIN 250Ω –3 –6 250Ω –9 –12 22pF/32.4Ω RS 1/3 OPA3680 VO CL 1kΩ 250Ω –15 47pF/26.7Ω 1kΩ is optional –18 10 0 100 100MHz 200MHz Frequency (20MHz/div) Capacitive Load (pF) OPEN-LOOP GAIN AND PHASE CMRR AND PSRR vs FREQUENCY 70 90 60 0 –30 Open-Loop Phase 80 –PSRR 70 +PSRR 50 –60 Open-Loop Gain 40 –90 30 –120 20 –150 10 –180 20 0 –210 10 –10 –240 0 –20 60 CMRR 50 40 30 10k 100k 1M 10M –270 10k 100M Frequency (Hz) 100k 1M 10M 100M 1G Frequency (Hz) ® 7 OPA3680 Open-Loop Phase (degrees) 100 Open-Loop Gain (dB) Power Supply Rejection Ratio (dB) Common-Mode Rejection Ratio (dB) 0 FREQUENCY RESPONSE vs CAPACITIVE LOAD 35 RS (Ω) –2 Single-Tone Load Power (dBm) TYPICAL PERFORMANCE CURVES: VS = ±5V (Cont.) At TA = +25°C, G = +2, RF = 250Ω, and RL = 100Ω, unless otherwise noted. See Figure 1. TYPICAL DC DRIFT OVER TEMPERATURE COMPOSITE VIDEO dG/dP 0.2 15 +5V Video In 250Ω OPA3680 0.15 75Ω 0.125 Optional 1.3kΩ Pulldown 250Ω dφ dG 0.1 250Ω 0.075 –5V 0.05 dG dφ 0.025 0 10 IB 5 VIO 0 IOS –5 –10 –15 1 2 3 4 –40 –20 0 Number of 150Ω Loads OUTPUT VOLTAGE AND CURRENT LIMITATIONS 5 One Channel Only 1 0 Output Current (50mA/div) VO (Volts) 2 25Ω Load Line 50Ω Load Line –1 100Ω Load Line –2 –3 80 100 120 140 30 Sourcing Output Current Sinking Output Current 150 22.5 Quiescent Supply Current 100 15 50 7.5 1W Internal Power Limit Output Current Limit –4 60 SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 1W Internal Power Limit 3 40 200 Output Current Limited 4 20 Ambient Temperature (°C) –5 0 –300 –200 –100 0 100 200 0 –40 300 –20 0 20 40 60 80 100 120 140 Ambient Temperature (°C) IO (mA) ALL HOSTILE CROSSTALK CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY 10 –20 200Ω –30 –40 ZO 1 Crosstalk (dB) Output Impedance (Ω) +5V 1/3 OPA3680 –5V 250Ω 250Ω 0.1 –50 –60 –70 –80 –90 0.01 –100 10k 100k 1M 10M 100M 0.3 Frequency (Hz) 10 Frequency (MHz) ® OPA3680 1 8 100 300 Supply Current (7.5mA/div) dG/dφ (%/degrees) With 1.3kΩ Pulldown Video Loads 1/3 Input Offset Voltage (mV) Input Bias and Offset Current (µA) No Pulldown DIS 0.175 TYPICAL PERFORMANCE CURVES: VS = +5V At TA = +25°C, G = +2, RF = 250Ω, and RL = 100Ω to VS/2, unless otherwise noted. See Figure 2. SMALL-SIGNAL FREQUENCY RESPONSE 6 VO = 0.5Vp-p VO = 0.5Vp-p 9 0 VO = 1Vp-p 6 G = +2 –3 Gain (3dB/div) Normalized Gain (3dB/div) 3 LARGE-SIGNAL FREQUENCY RESPONSE 12 G = +1 RF = 25Ω –6 –9 G = +5 –12 –15 3 VO = 2Vp-p 0 –3 VO = 3Vp-p –6 –9 G = +10 –18 –12 –21 –15 –24 –18 0.5 10 100 500 0.5 10 Frequency (MHz) SMALL-SIGNAL PULSE RESPONSE 4.1 G = +2 VO = 0.5Vp-p 2.8 Output Voltage (400mV/div) Output Voltage (100mV/div) 500 LARGE-SIGNAL PULSE RESPONSE 2.9 2.7 2.6 2.5 2.4 2.3 2.2 G = +2 VO = 2Vp-p 3.7 3.3 2.9 2.5 2.1 1.7 1.3 2.1 0.9 Time (5ns/div) Time (5ns/div) RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 70 12 Gain-to-Capacitive Load (3dB/div) Noise Gain = 3.2 60 50 RS (Ω) 100 Frequency (MHz) 40 30 20 10 0 CL = 47pF Signal Gain = +2 Noise Gain = 3.2 9 CL = 10pF CL = 22pF 6 CL = 100pF 3 +5V 0 –3 0.1µF 714Ω VI –6 58Ω 714Ω 250Ω 1/3 OPA3680 RS VO CL –9 250Ω –12 250Ω –15 0.1µF –18 1 10 100 0 Capacitive Load (pF) 100MHz 200MHz Frequency (20MHz/div) ® 9 OPA3680 TYPICAL PERFORMANCE CURVES: VS = +5V (Cont.) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω to VS/2, unless otherwise noted. See Figure 2. TWO-TONE, 3rd-ORDER SPURIOUS LEVEL 3rd-Order Spurious Level (dBc) –40 50MHz –50 –60 20MHz –70 10MHz –80 Load Power at Matched 50Ω Load –90 –14 –12 –10 –8 –6 PO (dBm) ® OPA3680 10 –4 –2 0 APPLICATIONS INFORMATION matches the 125Ω source resistance seen at the inverting input (see the DC Accuracy and Offset Control section). In addition to the usual power supply decoupling capacitors to ground, a 0.1µF capacitor is included between the two power supply pins. In practical PC board layouts, this optionaladded capacitor will typically improve the 2nd harmonic distortion performance by 3dB to 6dB. WIDEBAND VOLTAGE FEEDBACK OPERATION The OPA3680 provides an exceptional combination of high output power capability with a wideband, unity gain stable voltage feedback op amp using a new high slew rate input stage. Typical differential input stages used for voltage feedback op amps are designed to steer a fixed-bias current to the compensation capacitor, setting a limit to the achievable slew rate. The OPA3680 uses a new input stage which places the transconductance element between two input buffers, using their output currents as the forward signal. As the error voltage increases across the two inputs, an increasing current is delivered to the compensation capacitor. This provides very high slew rate (1800V/µs) while consuming relatively low quiescent current (6.4mA). This exceptional full power performance comes at the price of a slightly higher input noise voltage than alternative architectures. The 4.8nV/√Hz input voltage noise for the OPA3680 is exceptionally low for this type of input stage. Figure 2 shows the AC-coupled, gain of +2, single supply circuit configuration which is the basis of the +5V Specifications and Typical Performance Curves. Though not a “railto-rail” design, the OPA3680 requires minimal input and output voltage headroom compared to other very wideband voltage feedback op amps. It will deliver a 3Vp-p output swing on a single +5V supply with >150MHz bandwidth. The key requirement of broadband single-supply operation is to maintain input and output signal swings within the useable voltage ranges at both the input and the output. The circuit of Figure 2 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 402Ω resistors). The input signal is then AC-coupled into the midpoint voltage bias. The input voltage can swing to within 1.5V of either supply pin, giving a 2Vp-p input signal range centered between the supply pins. The input impedance matching resistor (68Ω) used for testing is adjusted to give a 50Ω input load when the parallel combination of the biasing divider network is included. Again, an additional resistor (50Ω in this case) is included directly in series with the non-inverting input. This minimum recommended value provides part of the DC source resistance matching for the non-inverting input bias current. It is also used to form a simple parasitic pole to roll off the frequency response at very high frequencies (>500MHz) using the input parasitic capacitance to form a bandlimiting pole. The gain resistor (RG) is ACcoupled, giving the circuit a DC gain of +1, which puts the input DC bias voltage (2.5V) at the output as well. The Figure 1 shows the DC-coupled, gain of +2, dual power supply circuit configuration used as the basis of the ±5V Specifications and Typical Performance Curves. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the specifications are taken directly at the input and output pins, while output powers (dBm) are at the matched 50Ω load. For the circuit of Figure 1, the total effective load will be 100Ω || 498Ω. The disable control line is typically left open to guarantee normal amplifier operation. Two optional components are included in Figure 1. An additional resistor (100Ω) is included in series with the non-inverting input. Combined with the 25Ω DC source resistance looking back towards the signal generator, this gives an input bias current cancelling resistance that 0.1µF +5V +VS 6.8µF + +5V +VS 0.1µF 50Ω Source 50Ω 6.8µF 402Ω 100Ω VI + DIS VO 1/3 OPA3680 0.1µF 50Ω 0.1µF 50Ω Load VI 68Ω 50Ω 402Ω DIS 1/3 OPA3680 VO 100Ω VS/2 RF 249Ω RF 249Ω RG 249Ω RG 249Ω –VS –5V + 6.8µF 0.1µF 0.1µF FIGURE 2. AC-Coupled, G = +2, Single Supply, Specification and Test Circuit. FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit. ® 11 OPA3680 INSTRUMENTATION DIFFERENTIAL AMPLIFIER output voltage can swing to within 1V of either supply pin while delivering >100mA output current. A demanding 100Ω load to a midpoint bias is used in this characterization circuit. The new output stage circuit used in the OPA3680 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown in the ±5V supply, Harmonic Distortion vs Supply Voltage plot. Figure 4 shows an instrumentation differential amplifier based on the OPA3680. This application benefits from the OPA3680’s DC precision, common-mode rejection, high impedance input and low current noise. The resistors on the last (difference) amplifier were selected to keep the loads equal on the input stage op amps. The matched loads and a careful PC board layout can improve 2nd harmonic distortion at higher frequencies. ANALOG DELAY LINE The diagram on the front page of this data sheet shows an analog delay line using the OPA3680. The first op amp buffers the delay line from the source, and can be used to establish the DC operating point if single +5V supply operation is desired. The last two sections provide an analog delay function given by Equation 1: Delay = 2τ , for each section 1 + (2 πfτ)2 V1 124Ω (1) 1/3 OPA3680 499Ω 249Ω where, f represents the frequency components of interest in the input signal. For input frequencies below 0.39/2πτ = 2.5MHz the delay will be within 15% of the desired value (2τ). The circuit on the front page gives a delay of 50ns per stage for a total delay of 100ns. Excellent pulse fidelity will be retained as long as the first 5 harmonics are delayed equally. For the circuit shown on the front page, the 5th harmonic should be ≤ 2.5MHz/5, which will support a square wave up to 500kHz, with good pulse response. The input rise and fall times also need to be ≥ 0.30/2.5MHz = 120ns in order to keep the spectral energy within this 2.5MHz limit. Quicker rise or fall times will cause propagation delay errors and excessive pre-shoot. 1/3 OPA3680 249Ω = 2 (V1 – V2) FIGURE 4. Instrumentation Amplifier. BUFFERED 2 x 1 MULTIPLEXER Using two of the three channels in an OPA3680 to select one of two possible input signals, then using the 3rd to isolate the summing point and drive the load, will give a very flexible, wideband, multiplexing capability. Figure 5 shows one example of this where the two input stages have been set up for a gain of +2. Summing the two output signals together at the output stage buffer’s non-inverting input through 400Ω resistors allows excellent isolation between the two channels to be maintained. When one channel is operating, the other will see an attenuated version of the active channel’s signal on its inverting node. In this circuit, that signal is attenuated by 20dB at this inactive inverting input—this will keep the swing low enough on the off channel to avoid parasitic turn on at that input stage. The desired signal is attenuated by 0.6V/V due to this resistor divider, then recovered by the gain set in the output stage. The 1pF capacitors limit the noise, while maintaining good pulse response. If desired, these two capacitors may be removed for circuits that produce less delay. 800 600 Output 400 Input 200 106ns One modification to this circuit would give a high speed switched gain. The same signal would be fed into both inputs and each amplifier would be set to a different gain. –200 –400 –600 –800 Time (200ns/div) FIGURE 3. Analog Delay Line’s Pulse Response. ® OPA3680 249Ω VOUT V2 Shorter delays may be implemented at higher frequencies by adjusting R and C. To maintain bias current cancellation, it is best to simply reduce C without changing R. 0 124Ω 249Ω τ = RC Input and Output Voltage (200mV/div) 1/3 OPA3680 12 +5V 2kΩ VDIS +5V +5V 49.9Ω Video1 DIS 1/3 OPA3680 75Ω 402Ω DIS 75Ω 1/3 OPA3680 –5V 100Ω –5V 100Ω 249Ω 100Ω 100Ω 374Ω +5V 402Ω 1/3 OPA3680 49.9Ω Video2 DIS 75Ω –5V 2kΩ FIGURE 5. Buffered 2-to-1 MUX. TRIPLE ADC DRIVER 124Ω V1 249Ω Figure 6 shows the OPA3680 driving a triple ADC. Most ADC’s are defined for single +5V operation. The OPA3680 can be adapted to single +5V as well using the techniques described for Figure 2. The signal flowthrough pinout for the OPA3680 allows a higher signal fidelity through higher frequencies due to the simplified PC layout requirements. 24.9Ω 1/3 OPA3680 100pF 249Ω 124Ω V2 24.9Ω 1/3 OPA3680 249Ω WIDEBAND INTEGRATOR Triple ADC 100pF 249Ω The three unity-gain stable, voltage-feedback amplifiers in the OPA3680 may be used to develop an exceptional integrator function, as shown in Figure 7. This circuit effectively multiplies the open-loop gain using two of the amplifiers and uses the 3rd to provide an input impedance buffering and low output impedance over broad frequencies required for proper operation. The interstage attenuator (resistive divider into the last stage non-inverting input) shown in Figure 6 is critical to maintaining stability. This circuit can deliver a 90° phase shift over a 5-decade frequency span. 124Ω V3 24.9Ω 1/3 OPA3680 249Ω 100pF 249Ω FIGURE 6. Triple ADC Driver. C 50Ω VIN 50Ω 1/3 OPA3680 R 1/3 OPA3680 150Ω 1/3 OPA3680 VOUT 75Ω 25Ω 50Ω FIGURE 7. Wideband Integrator. ® 13 OPA3680 R QPR C R/δ R R C R VIN VOUT 49.9Ω 1/3 OPA3680 1/3 OPA3680 1/3 OPA3680 49.9Ω 49.9Ω QPR/χ QPR/β αC RISO FIGURE 8. State Variable Filter. DESIGN-IN TOOLS STATE VARIABLE FILTER Figure 8 shows a state variable filter using the OPA3680. This active filter is quite useful for high Q filter responses, and will produce lowpass, highpass, bandpass, notch and allpass functions. The filter response is: VOUT = – VIN ωP = sω P (β – χ) + ω 2P (δ) QP sω P + ω 2P s2 + QP DEMONSTRATION BOARDS PC boards are available to assist in the initial evaluation of circuit performance using the OPA3680. They are available free as an unpopulated PC board delivered with descriptive documentation. The summary information for the boards is shown below: s 2 (α ) + (2) 1 RC The desired filter frequency response is achieved by the correct selection of the feed-forward components at the input. 16-Lead SSOP SO-16 DEM-OPA368xE DEM-OPA368xU MKT-354 MKT-364 MACROMODELS Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for Video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA680 is available through either the Burr-Brown Internet web page (http://www.burr-brown.com). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion, temperature performance or dG/dφ characteristics. These models do not attempt to distinguish between the package types in their small-signal AC performance. (3) where, fGBP is the OPA3680’s gain bandwidth product (300MHz). ® OPA3680 PACKAGE OPA3680E OPA3680U LITERATURE REQUEST NUMBER Contact the Burr-Brown Applications support line (1-800-548-6132) to request this board (ask for the desired literature number). The resistor RISO isolates the last op amp and the input driver from capacitive loading problems when α > 0. To ensure good performance, make sure that: fGBP , QP > 1 ω P 20Q P ≤ 2 π fGBP QP ≤ 1 , 20 PRODUCT BOARD PART NUMBER 14 OPERATING SUGGESTIONS tions. For example, by using a 250Ω feedback resistor along with a 250Ω resistor across the two op amp inputs, the voltage follower response will be similar to the gain of +2 response of Figure 2. Further reducing the value of the resistor across the op amp inputs will further dampen the frequency response due to increased noise gain. OPTIMIZING RESISTOR VALUES Since the OPA3680 is a unity-gain stable, voltage-feedback op amp, a wide range of resistor values may be used for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. For a non-inverting unity gain follower application, the feedback connection should be made with a 25Ω resistor, not a direct short. This will isolate the inverting input capacitance from the output pin and improve the frequency response flatness. Usually, for G > 1 applications, the feedback resistor value should be between 100Ω and 1.5kΩ. Below 100Ω, the feedback network will present additional output loading which can degrade the harmonic distortion performance of the OPA3680. Above 1.5kΩ, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor may cause unintentional band-limiting in the amplifier response. The OPA3680 exhibits minimal bandwidth reduction going to single supply (+5V) operation as compared with ±5V. This is because the internal bias control circuitry retains nearly constant quiescent current as the total supply voltage between the supply pins is changed. INVERTING AMPLIFIER OPERATION Since the OPA3680 is a general purpose, wideband voltage feedback op amp, all of the familiar op amp application circuits are available to the designer. Inverting operation is one of the more common requirements and offers several performance benefits. Figure 9 shows a typical inverting configuration where the I/O impedances and signal gain from Figure 1 are retained in an inverting circuit configuration. A good rule of thumb is to target the parallel combination of RF and RG (Figure 1) to be less than approximately 125Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the feedback network and thus, a zero in the forward response. Assuming a 3pF total parasitic on the inverting node, holding RF || RG < 125Ω will keep this pole above 400MHz. By itself, this constraint implies that the feedback resistor RF can increase to several kΩ at high gains. This is acceptable as long as the pole formed by RF and any parasitic capacitance appearing in parallel with it is kept out of the frequency range of interest. +5V + 0.1µF 6.8µF 0.1µF DIS RB 95.6Ω BANDWIDTH VS GAIN: NON-INVERTING OPERATION Voltage-feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the Gain Bandwidth Product (GBP) shown in the specifications. Ideally, dividing GBP by the non-inverting signal gain (also called the Noise Gain, or NG) will predict the closed-loop bandwidth. In practice, this only holds true when the phase margin approaches 90°, as it does in high gain configurations. At low gains (increased feedback factors), most amplifiers will exhibit a more complex response with lower phase margin. The OPA3680 is compensated to give a slightly peaked response in a noninverting gain of 2 (Figure 1). This results in a typical gain of +2 bandwidth of 220MHz, far exceeding that predicted by dividing the 300MHz GBP by 2. Increasing the gain will cause the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +10, the 30MHz bandwidth shown in the Typical Specifications agrees with that predicted using the simple formula and the typical GBP of 300MHz. 50Ω Source 1/3 OPA3680 RO 50Ω 50Ω Load RF 250Ω RG 124Ω RM 84.5Ω 0.1µF + 6.8µF –5V FIGURE 9. Gain of –2 Example Circuit. In the inverting configuration, three key design consideration must be noted. The first is that the gain resistor (RG) becomes part of the signal channel input impedance. If input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted pair, long PC board trace or other transmission line conductor), RG may be set equal to the required termination value and RF adjusted to give the desired gain. This is the simplest approach and results in optimum bandwidth and noise performance. However, at low inverting gains, the resultant feedback resistor value can present a significant load to the amplifier output. For an inverting gain of 2, setting RG to 50Ω for input matching eliminates the need for RM but requires a 100Ω feedback resistor. This has the interesting Frequency response in a gain of +2 may be modified to achieve exceptional flatness simply by increasing the noise gain to 2.5. One way to do this, without affecting the +2 signal gain, is to add a 453Ω resistor across the two inputs in the circuit of Figure 1. A similar technique may be used to reduce peaking in unity gain (voltage follower) applica- ® 15 OPA3680 advantage that the noise gain becomes equal to 2 for a 50Ω source impedance—the same as the non-inverting circuits considered above. However, the amplifier output will now see the 100Ω feedback resistor in parallel with the external load. In general, the feedback resistor should be limited to the 100Ω to 1.5kΩ range. In this case, it is preferable to increase both the RF and RG values as shown in Figure 9 and then achieve the input matching impedance with a third resistor (RM) to ground. The total input impedance becomes the parallel combination of RG and RM. drive capabilities, noting that the graph is bounded by a “Safe Operating Area” of 1W maximum internal power dissipation for a single channel. Superimposing resistor load lines onto the plot shows that the OPA3680 can drive ±2.5V into 25Ω or ±3.5V into 50Ω without exceeding the output capabilities or the 1W dissipation limit. A 100Ω load line (the standard test circuit load) shows the full ±3.9V output swing capability, as shown in the typical specifications. The minimum specified output voltage and current specifications over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the guaranteed tables. As the output transistors deliver power, their junction temperatures will increase, decreasing their VBE’s (increasing the available output voltage swing) and increasing their current gains (increasing the available output current). In steady-state operation, the available output voltage and current will always be greater than that shown in the over-temperature specifications since the output stage junction temperatures will be higher than the minimum specified operating ambient. The second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and hence influences the bandwidth. For the example in Figure 9, the RM value combines in parallel with the external 50Ω source impedance, yielding an effective driving impedance of 50Ω || 84.5Ω = 31.4Ω. This impedance is added in series with RG for calculating the noise gain (NG). The resultant NG is 2.6 for Figure 9, as opposed to only 2 if RM could be eliminated as discussed above. The bandwidth will therefore be slightly lower for the gain of –2 circuit of Figure 9 than for the gain of +2 circuit of Figure 1. To maintain maximum output stage linearity, no output short-circuit protection is provided. This will not normally be a problem since most applications include a series matching resistor at the output that will limit the internal power dissipation if the output side of this resistor is shorted to ground. However, shorting the output pin directly to the adjacent positive power supply pins will, in most cases, destroy the amplifier. If additional short-circuit protection is required, consider a small series resistor in the power supply leads. Under heavy output loads, this will reduce the available output voltage swing. A 5Ω series resistor in each power supply lead will limit the internal power dissipation to less than 1W for an output short circuit while decreasing the available output voltage swing only 0.5V for up to 100mA desired load currents. Always place the 0.1µF power supply decoupling capacitors after these supply current limiting resistors directly on the supply pins. The third important consideration in inverting amplifier design is setting the bias current cancellation resistor on the non-inverting input (RB). If this resistor is set equal to the total DC resistance looking out of the inverting node, the output DC error, due to the input bias currents, will be reduced to (Input Offset Current) • RF. If the 50Ω source impedance is DC-coupled in Figure 9, the total resistance to ground on the inverting input will be 155Ω. Combining this in parallel with the feedback resistor gives the RB = 95.6Ω used in this example. To reduce the additional high frequency noise introduced by this resistor, it is sometimes bypassed with a capacitor. As long as RB < 350Ω, the capacitor is not required since the total noise contribution of all other terms will be less than that of the op amp’s input noise voltage. As a minimum, the OPA3680 requires an RB value of 50Ω to damp out parasitic-induced peaking—a direct short to ground on the non-inverting input runs the risk of a very high frequency instability in the input stage. DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an A/D converter—including additional external capacitance which may be recommended to improve A/D linearity. A high speed, high open-loop gain amplifier like the OPA3680 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier’s open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop OUTPUT CURRENT AND VOLTAGE The OPA3680 provides output voltage and current capabilities that are unsurpassed in a low cost monolithic op amp. Under no-load conditions at +25°C, the output voltage typically swings closer than 1V to either supply rail; the guaranteed swing limit is within 1.2V of either rail. Into a 15Ω load (the minimum tested load), it is guaranteed to deliver more than ±135mA. The specifications described above, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage • current, or V-I product, which is more relevant to circuit operation. Refer to the “Output Voltage and Current Limitations” plot in the Typical Performance Curves. The X and Y axes of this graph show the zero-voltage output current limit and the zerocurrent output voltage limit, respectively. The four quadrants give a more detailed view of the OPA3680’s output ® OPA3680 16 The distortion plots show which changes in operation will improve distortion. Increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network; in the non-inverting configuration (Figure 1) this is sum of RF + RG, while in the inverting configuration (Figure 9), it is just RF. Also, providing an additional supply decoupling capacitor (0.1µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Performance Curves show the recommended RS versus capacitive load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA3680. Long PC board traces, unmatched cables, and connections to multiple devices can easily exceed this value. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA3680 output pin (see Board Layout Guidelines). In most op amps, increasing the output voltage swing increases intermodulation distortion directly. The new output stage used in the OPA3680 actually holds the difference between fundamental power and the 3rd-order intermodulation powers relatively constant with increasing output power until very large output swings are required (> 4Vp-p). The 3rd-order spurious levels are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Performance Curves show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For 2 tones centered at 20MHz, with 10dBm/ tone into a matched 50Ω load (i.e., 2Vp-p for each tone at the load, which requires 8Vp-p for the overall two-tone envelope at the output pin), the Typical Performance Curves show 57dBc difference between the test tone powers and the 3rd-order intermodulation spurious powers. This exceptional performance improves further when operating at lower frequencies. The criterion for setting this RS resistor is a maximum bandwidth, flat frequency response at the load. For the OPA3680 operating in a gain of +2, the frequency response at the output pin is already slightly peaked without the capacitive load requiring relatively high values of RS to flatten the response at the load. Increasing the noise gain will reduce the peaking as described previously. The circuit of Figure 10 demonstrates this technique, allowing lower values of RS to be used for a given capacitive load. This was used to generate the Recommended RS versus Capacitive Load plots. +5V 50Ω Power supply decoupling not shown. 50Ω 50Ω RNG 1/3 OPA3680 250Ω RS NOISE PERFORMANCE VO High slew rate, unity gain stable, voltage feedback op amps usually achieve their slew rate at the expense of a higher input noise voltage. The 4.8nV/√Hz input voltage noise for the OPA3680 is, however, much lower than comparable amplifiers. The input-referred voltage noise, and the two input-referred current noise terms, combine to give low output noise under a wide variety of operating conditions. Figure 11 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. CL 250Ω –5V FIGURE 10. Capacitive Load Driving with Noise Gain Tuning. This gain of +2 circuit includes a noise gain tuning resistor across the two inputs to increase the noise gain, increasing the unloaded phase margin for the op amp. Although this technique will reduce the required RS resistor for a given capacitive load, it does increase the noise at the output. It also will decrease the loop gain, slightly decreasing the distortion performance. If, however, the dominant distortion mechanism arises from a high RS value, significant dynamic range improvement can be achieved using this technique. ENI RS 1/3 OPA3680 IBN ERS EO RF √ 4kTRS DISTORTION PERFORMANCE 4kT RG The OPA3680 provides good distortion performance into a 100Ω load on ±5V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads and/or operating on a single +5V supply. RG IBI √ 4kTRF 4kT = 1.6E –20J at 290°K FIGURE 11. Op Amp Noise Analysis Model. ® 17 OPA3680 a worst-case output offset voltage equal to: – (NG = noninverting signal gain) The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 4 shows the general form for the output noise voltage using the terms shown in Figure 11. ±(NG • VOS(MAX)) ± (RF • IOS(MAX)) = ±(2 • 4.5mV) ± (250Ω • 0.7µA) = ±9.2mV (4) EO = (E 2 NI ) A fine scale output offset null, or DC operating point adjustment, is often required. Numerous techniques are available for introducing DC offset control into an op amp circuit. Most of these techniques eventually reduce to adding a DC current through the feedback resistor. In selecting an offset trim method, one key consideration is the impact on the desired signal path frequency response. If the signal path is intended to be non-inverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the non-inverting input may be considered. However, the DC offset voltage on the summing junction will set up a DC current back into the source which must be considered. Applying an offset adjustment to the inverting op amp input can change the noise gain and frequency response flatness. For a DC-coupled inverting amplifier, Figure 12 shows one example of an offset adjustment technique that has minimal impact on the signal frequency response. In this case, the DC offsetting current is brought into the inverting input node through resistor values that are much larger than the signal path resistors. This will insure that the adjustment circuit has minimal effect on the loop gain and hence the frequency response. + (I BN R S ) + 4 kTR S NG 2 + ( I BI R F ) + 4 kTR F NG 2 (6) 2 Dividing this expression by the noise gain (NG = (1+RF /RG)) will give the equivalent input-referred spot noise voltage at the non-inverting input, as shown in Equation 5: (5) 2 I R 4 kTR F 2 E N = E NI 2 + ( I BN R S ) + 4 kTR S + BI F + NG NG Evaluating these two equations for the OPA3680 circuit and component values shown in Figure 1 will give a total output spot noise voltage of 11nV/√Hz and a total equivalent input spot noise voltage of 5.5nV/√Hz. This is including the noise added by the bias current cancellation resistor (100Ω) on the non-inverting input. This total input-referred spot noise voltage is only slightly higher than the 4.8nV/√Hz specification for the op amp voltage noise alone. This will be the case as long as the impedances appearing at each op amp input are limited to the previously recommend maximum value of 125Ω. Keeping both (RF || RG) and the non-inverting input source impedance less than 125Ω will satisfy both noise and frequency response flatness considerations. Since the resistor-induced noise is relatively negligible, additional capacitive decoupling across the bias current cancellation resistor (RB) for the inverting op amp configuration of Figure 9 is not required. +5V Supply Decoupling Not Shown 328Ω 0.1µF 1/3 OPA3680 VO DC ACCURACY AND OFFSET CONTROL The balanced input stage of a wideband voltage feedback op amp allows good output DC accuracy in a wide variety of applications. The power supply current trim for the OPA3680 gives even tighter control than comparable products. Although the high speed input stage does require relatively high input bias current (typically 14µA out of each input terminal), the close matching between them may be used to reduce the output DC error caused by this current. The total output offset voltage may be considerably reduced by matching the DC source resistances appearing at the two inputs. This reduces the output DC error due to the input bias currents to the offset current times the feedback resistor. Evaluating the configuration of Figure 1, using worst-case +25°C input offset voltage and current specifications, gives –5V 5kΩ RF 250Ω VI 1.25kΩ ±200mV Output Adjustment 10kΩ 0.1µF 5kΩ VO VI =– RF RG = –2 –5V FIGURE 12. DC-Coupled, Inverting Gain of –2 with Offset Adjustment. ® OPA3680 RG 125Ω +5V 18 DISABLE OPERATION The transition edge rate (dv/dt) of the DIS control line will influence this glitch. For the plot of Figure 14, the edge rate was reduced until no further reduction in glitch amplitude was observed. This approximately 1V/ns maximum slew rate may be achieved by adding a simple RC filter into the DIS pin from a higher speed logic line. If extremely fast transition logic is used, a 1kΩ series resistor between the logic gate and the DIS input pin will provide adequate bandlimiting using just the parasitic input capacitance on the DIS pin while still ensuring adequate logic level swing. The OPA3680 provides an optional disable feature on each channel that may be used either to reduce system power or to impleme nt a simple channel multiplexing operation. If the DIS control pin of each channel is left unconnected, the OPA3680 will operate normally. To disable, the control pin must be asserted LOW. Figure 13 shows a simplified internal circuit for the disable control feature available on each channel. +VS 40 Output Voltage (20mV/div) 15kΩ Q1 25kΩ VDIS 110kΩ IS Control 20 Output Voltage (0V Input) 0 –20 –40 4.8V VDIS 0.2V –VS Time (20ns/div) FIGURE 13. Simplified Disable Control Circuit. FIGURE 14. Disable/Enable Glitch. In normal operation, base current to Q1 is provided through the 110kΩ resistor, while the emitter current through the 15kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1’s emitter. As VDIS is pulled LOW, additional current is pulled through the 15kΩ resistor eventually turning on those two diodes (≈100uA). At this point, any further current pulled out of VDIS goes through those diodes holding the emitter-base voltage of Q1 at approximately zero volts. This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the disable mode are only those required to operate the circuit of Figure 13. Additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break). THERMAL ANALYSIS Due to the high output power capability of the OPA3680, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. Operating junction temperature (TJ) is given by TA + PD•θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this condition, PDL = VS2/(4•RL) where RL includes feedback network loading. When disabled, the output and input nodes go to a high impedance state. If the OPA3680 is operating in a gain of +1, this will show a very high impedance at the output and exceptional signal isolation. If operating at a gain greater than +1, the total feedback network resistance (RF + RG) will appear as the impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. If configured as an inverting amplifier, the input and output will be connected through the feedback network resistance (RF + RG) and the isolation will be very poor as a result. Note that it is the power in the output stage and not into the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA3680E in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C and driving a grounded 100Ω load. One key parameter in disable operation is the output glitch when switching in and out of the disabled mode. Figure 14 shows these glitches for the circuit of Figure 1 with the input signal at 0V. The glitch waveform at the output pin is plotted along with the DIS pin voltage. PD = 10V•21mA + 3•[52/(4•(100Ω || 500Ω))] = 435mW Maximum TJ = +85°C + (0.44W•100°C/W) = 129°C ® 19 OPA3680 This worst-case condition is still well within rated maximum TJ for this 100Ω load. Heavier loads may, however, exceed the 175°C maximum junction temperature rating. Careful attention to internal power dissipation is required and perhaps airflow considered under extreme conditions. tors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 1.5kΩ, this parasitic capacitance can add a pole and/or zero below 500MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load driving considerations. The 250Ω feedback used in the typical performance specifications is a good starting point for design. Note that a 25Ω feedback resistor, rather than a direct short, is suggested for the unity gain follower application. This effectively isolates the inverting input capacitance from the output pin that would otherwise cause an additional peaking in the gain of +1 frequency response. BOARD LAYOUT GUIDELINES Achieving optimum performance with a high frequency amplifier like the OPA3680 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the non-inverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. d) Connections to other wideband devices on the board may be made with short direct traces or through on-board transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 5pF) may not need an RS since the OPA3680 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin) If a long trace is required, and the 6dB signal loss intrinsic to a doubly terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined (based on board material and trace dimensions), a matching series resistor into the trace from the output of the OPA3680 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA3680 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of Recommended RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. b) Minimize the distance (< 0.25") from the power supply pins to high frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capacitors. An optional supply decoupling capacitor (0.1µF) across the two power supplies (for bipolar operation) will improve 2nd harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high frequency performance of the OPA3680. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film or carbon composition axiallyleaded resistors can also provide good high frequency performance. Again, keep their leads and PC board traces as short as possible. Never use wirewound type resistors in a high frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as non-inverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resis- ® OPA3680 20 INPUT AND ESD PROTECTION The OPA3680 is built using a very high speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies as shown in Figure 15. +V CC External Pin These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g., in systems with ±15V supply parts driving into the OPA3680), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. Internal Circuitry –V CC FIGURE 15. Internal ESD Protection. ® 21 OPA3680