® OPA688 OPA 688 OPA 688 For most current data sheet and other product information, visit www.burr-brown.com Unity Gain Stable, Wideband VOLTAGE LIMITING AMPLIFIER TM FEATURES APPLICATIONS ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● HIGH LINEARITY NEAR LIMITING FAST RECOVERY FROM OVERDRIVE: 2.4ns LIMITING VOLTAGE ACCURACY: ±15mV –3dB BANDWIDTH (G = +1): 530MHz SLEW RATE: 1000V/µs ±5V AND 5V SUPPLY OPERATION HIGH GAIN VERSION: OPA689 FAST LIMITING ADC INPUT BUFFER CCD PIXEL CLOCK STRIPPING VIDEO SYNC STRIPPING HF MIXER IF LIMITING AMPLIFIER AM SIGNAL GENERATION NON-LINEAR ANALOG SIGNAL PROCESSING COMPARATOR DESCRIPTION The OPA688 is a wideband, unity gain stable voltage feedback op amp that offers bipolar output voltage limiting. Two buffered limiting voltages take control of the output when it attempts to drive beyond these limits. This new output limiting architecture holds the limiter offset error to ±15mV. The op amp operates linearly to within 30mV of the output limit voltages. the input, gives the specified limiting accuracy for any gain, and allows the OPA688 to be used in all standard op amp applications. The combination of narrow nonlinear range and low limiting offset allows the limiting voltages to be set within 100mV of the desired linear output range. A fast 2.4ns recovery from limiting ensures that overdrive signals will be transparent to the signal channel. Implementing the limiting function at the output, as opposed to The OPA688 is available in an industry standard pinout in PDIP-8 and SO-8 packages. For higher gain, or transimpedance applications requiring output limiting with fast recovery, consider the OPA689. Non-linear analog signal processing will benefit from the OPA688’s sharp transition from linear operation to output limiting. The quick recovery time supports high speed applications. DETAIL OF LIMITED OUTPUT VOLTAGE LIMITED OUTPUT RESPONSE 2.10 2.5 VH = –VL = 2.0V G = +2 2.05 2.00 1.5 VIN 1.0 VO Output Voltage (V) Input and Output Voltage (V) 2.0 0.5 0 –0.5 –1.0 1.95 VO 1.90 1.85 1.80 1.75 –1.5 1.70 –2.0 1.65 1.60 –2.5 Time (50ns/div) Time (200ns/div) International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1997 Burr-Brown Corporation PDS-1424D 1 Printed in U.S.A. January, 2000 OPA688 SPECIFICATIONS— VS = ±5V G = +2, RL = 500Ω, RF = 402Ω, VH = –VL = 2V (Figure 1 for AC performance only), unless otherwise noted. OPA688U, P GUARANTEED(1) TYP PARAMETER AC PERFORMANCE (see Figure 1) Small Signal Bandwidth Gain-Bandwidth Product (G ≥ +5) Gain Peaking 0.1dB Gain Flatness Bandwidth Large Signal Bandwidth Step Response: Slew Rate Rise/Fall Time Settling Time: 0.05% Spurious Free Dynamic Range Differential Gain Differential Phase Input Noise: Voltage Noise Density Current Noise Density DC PERFORMANCE (VCM = 0) Open Loop Voltage Gain (AOL) Input Offset Voltage Average Drift Input Bias Current(3) Average Drift Input Offset Current Average Drift INPUT Common-Mode Rejection Common-Mode Input Range(4) Input Impedance Differential-Mode Common-Mode OUTPUT Output Voltage Range Current Output, Sourcing Sinking Closed-Loop Output Impedance POWER SUPPLY Operating Voltage, Specified Maximum Quiescent Current, Maximum Minimum Power Supply Rejection Ratio +PSR (Input Referred) OUTPUT VOLTAGE LIMITERS Default Limit Voltage Minimum Limiter Separation (VH – VL) Maximum Limit Voltage Limiter Input Bias Current Magnitude (5) Maximum Minimum Average Drift Limiter Input Impedance Limiter Feedthrough(6) DC Performance in Limit Mode Limiter Offset Op Amp Input Bias Current Shift(3) AC Performance in Limit Mode Limiter Small Signal Bandwidth Limiter Slew Rate(7) Limited Step Response Overshoot Recovery Time Linearity Guardband(8) CONDITIONS +25°C +25°C 0°C to +70°C –40°C to +85°C VO < 0.2Vp-p G = +1, RF = 25Ω G = +2 G = –1 VO < 0.2Vp-p G = +1, RF = 25Ω, VO < 0.2Vp-p VO < 0.2Vp-p VO = 4Vp-p, VH = –VL = 2.5V 530 260 230 290 11 50 145 — 150 — 175 — — 100 — 140 — 170 — — 95 — 135 — 160 4V Step, VH = –VL = 2.5V 0.2V Step 2V Step f = 5MHz, VO = 2Vp-p NTSC, PAL, RL = 500Ω NTSC, PAL, RL = 500Ω 1000 1.2 7 66 0.02 0.01 800 2.6 — 62 — — f ≥ 1MHz f ≥ 1MHz 6.3 2.0 VO = ±0.5V 52 ±2 — +6 — ±0.3 — ±12 57 ±3.3 Input Referred, VCM = ±0.5V VH = –VL = 4.3V RL ≥ 500Ω VO = 0 VO = 0 G = +1, RF = 25Ω, f < 100kHz MIN/ TEST MAX LEVEL(2) — 90 MHz MHz MHz MHz dB MHz MHz Typ Min Typ Min Typ Typ Min C B C B C C B 770 2.7 — 58 — — 650 3 — 53 — — V/µs ns ns dB % ° Min Max Typ Min Typ Typ B B C B C C 7.2 2.5 7.8 2.9 8 3.6 nV/√Hz pA/√Hz Max Max B B 46 44 ±7 ±14 ±13 –60 ±3 ±10 43 ±9 ±14 ±20 –90 ±4 ±10 dB mV µV/°C µA nA/°C µA nA/°C Min Max Max Max Max Max Max A A B A B A B ±3.2 50 49 ±3.2 47 ±3.1 dB V Min Min A A 0.4 || 1 1 || 1 — — — — — — MΩ || pF MΩ || pF Typ Typ C C ±4.1 105 –85 0.2 ±3.9 90 –70 — ±3.9 85 –65 — ±3.8 80 –60 — V mA mA Ω Min Min Min Typ A A A C ±5 — 15.8 15.8 — ±6 17 14 — ±6 19 12.8 — ±6 20 11 V V mA mA Typ Max Max Min C A A A 65 58 57 55 dB Min A ±3.3 200 — ±3.0 200 ±4.3 ±3.0 200 ±4.3 ±2.9 200 ±4.3 V mV V Min Min Max A B B 54 54 — 2 || 1 –60 65 35 — — — 68 34 40 — — 70 31 45 — — µA µA nA/°C MΩ || pF dB Max Min Max Typ Typ A A B C C ±15 3 ±35 — ±40 — ±40 — mV µA Max Typ A C 450 100 — — — — — — MHz V/µs Typ Typ C C 250 2.4 30 — 2.8 — — 3.0 — — 3.2 — mV ns mV Typ Max Typ C B C ±6 — — ±2 — — +VS = 4.5V to 5.5V Pins 5 and 8 Limiter Pins Open VO = 0 f = 5MHz VIN = ±2V (VO – VH) or (VO – VL) VIN = ±2V, VO < 0.02Vp-p 2x Overdrive VIN = 0 to ±2V Step VIN = ±2V to 0V Step f = 5MHz, VO = 2Vp-p ® OPA688 UNITS 2 SPECIFICATIONS— VS = ±5V (CONT) G = +2, RL = 500Ω, RF = 402Ω, VH = –VL = 2V (Figure 1 for AC performance only), unless otherwise noted. OPA688U, P GUARANTEED(1) TYP PARAMETER THERMAL CHARACTERISTICS Temperature Range Thermal Resistance P 8-Pin DIP U 8-Pin SO-8 CONDITIONS +25°C +25°C 0°C to +70°C –40°C to +85°C UNITS Specification: P, U Junction-to-Ambient –40 to +85 — — — °C Typ C 100 125 — — — — — — °C/W °C/W Typ Typ C C MIN/ TEST MAX LEVEL(2) NOTES: (1) Junction Temperature = Ambient Temperature for low temperature limit and 25°C guaranteed specifications. Junction Temperature = Ambient Temperature + 23°C at high temperature limit guaranteed specifications. (2) TEST LEVELS: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value for information only. (3) Current is considered positive out of node. (4) CMIR tested as < 3dB degradation from minimum CMRR at specified limits. (5) IVH (VH bias current) is positive, and I VL (VL bias current) is negative, under these conditions. See Note 3, Figure 1 and Figure 8 . (6) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V H (or VL) when VIN = 0. (7) VH slew rate conditions are: VIN = +2V, G = +2, VL = –2V, VH = step between 2V and 0V. VL slew rate conditions are similar. (8) Linearity Guardband is defined for an output sinusoid (f = 5MHz, VO = 0VDC ±1Vp-p) centered between the limiter levels (VH and VL). It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 9). SPECIFICATIONS — VS = +5V G = +2, RL = 500Ω tied to VCM = 2.5V, RF = 402Ω, VL = VCM –1.2V, VH = VCM +1.2V (Figure 2 for AC performance only), unless otherwise noted. OPA688U, P GUARANTEED(1) TYP PARAMETER AC PERFORMANCE (see Figure 2) Small Signal Bandwidth Gain-Bandwidth Product (G ≥ +5) Gain Peaking 0.1dB Gain Flatness Bandwidth Large Signal Bandwidth Step Response: Slew Rate Rise/Fall Time Settling Time: 0.05% Spurious Free Dynamic Range Input Noise: Voltage Noise Density Current Noise Density DC PERFORMANCE Open Loop Voltage Gain (AOL) Input Offset Voltage Average Drift Input Bias Current(3) Average Drift Input Offset Current Average Drift CONDITIONS +25°C +25°C 0°C to +70°C –40°C to +85°C UNITS VO < 0.2Vp-p G = +1, RF = 25Ω G = +2 G = –1 VO < 0.2Vp-p G = +1, RF = 25Ω, VO < 0.2Vp-p VO < 0.2Vp-p VO = 2Vp-p 515 240 190 275 10 50 240 — 110 — 130 — — 110 — 105 — 125 — — 105 — 100 — 120 — — 100 MHz MHz MHz MHz dB MHz MHz Typ Min Typ Min Typ Typ Min C B C B C C B 2V Step 0.2V Step 1V Step f = 5MHz, VO = 2Vp-p 1000 2.3 12 64 800 2.6 — 60 770 2.7 — 56 650 3 — 51 V/µs ns ns dB Min Max Typ Min B B C B f ≥ 1MHz f ≥ 1MHz 6.3 2.0 7.2 2.5 7.8 2.9 8 3.6 nV/√Hz pA/√Hz Max Max B B 46 44 ±7 ±14 ±13 –60 ±3 ±10 43 ±9 ±14 ±20 –90 ±4 ±10 dB mV µV/°C µA nA/°C µA nA/°C Min Max Max Max Max Max Max A A B A B A B VCM = 2.5V VO = ±0.5V 52 ±2 — +6 — ±0.3 — ±6 — ±12 — ±2 — MIN/ TEST MAX LEVEL(2) ® 3 OPA688 SPECIFICATIONS— VS = +5V (CONT) G = +2, RL = 500Ω tied to VCM = 2.5V, RF = 402Ω, VL = –1.2V, VH = +1.2V (Figure 2 for AC performance only), unless otherwise noted. OPA688U, P GUARANTEED(1) TYP PARAMETER INPUT Common-Mode Rejection Common-Mode Input Range(4) Input Impedance Differential-Mode Common-Mode OUTPUT Output Voltage Range Current Output, Sourcing Sinking Closed-Loop Output Impedance POWER SUPPLY Operating Voltage, Specified Maximum Quiescent Current, Maximum Minimum Power Supply Rejection Ratio +PSR (Input Referred) OUTPUT VOLTAGE LIMITERS Default Limiter Voltage Minimum Limiter Separation (VH – VL) Maximum Limit Voltage Limiter Input Bias Current Magnitude(5) Maximum Minimum Average Drift Limiter Input Impedance Limiter Feedthrough(6) DC Performance in Limit Mode Limiter Voltage Accuracy Op Amp Bias Current Shift(3) AC Performance in Limit Mode Limiter Small Signal Bandwidth Limiter Slew Rate(7) Limited Step Response Overshoot Recovery Time Linearity Guardband(8) THERMAL CHARACTERISTICS Temperature Range Thermal Resistance P 8-Pin DIP U 8-Pin SO-8 CONDITIONS +25°C +25°C 0°C to +70°C –40°C to +85°C UNITS Input Referred, VCM = ±0.5V 55 VCM ±0.8 48 VCM ±0.7 47 VCM ±0.7 45 VCM ±0.6 dB V Min Min A A 0.4 || 1 1 || 1 — — — — — — MΩ || pF MΩ || pF Typ Typ C C VCM ±1.6 70 –60 0.2 VCM ±1.4 60 –50 — VCM ±1.4 55 –45 — VCM ±1.3 50 –40 — V mA mA Ω Min Min Min Typ A A A C +5 — 13 13 — +12 15 11 — +12 15 10 — +12 16 9 V V mA mA Typ Max Max Min C A A A 65 — — — dB Typ C VCM ±0.9 200 — VCM ±0.6 200 VCM ±1.8 VCM ±0.6 200 VCM ±1.8 VCM ±0.6 200 VCM ±1.8 V mV V Min Min Max A B B 35 35 — 2 || 1 –60 65 0 — — — 75 0 30 — — 85 0 50 — — µA µA nA/°C MΩ || pF dB Max Min Max Typ Typ A A B C C ±15 5 ±35 — ±40 — ±40 — mV µA Max Typ A C 300 20 — — — — — — MHz V/µs Typ Typ C C 55 15 30 — — — — — — — — — mV ns mV Typ Max Max C C C –40 to +85 — — — °C Typ C 100 125 — — — — — — °C/W °C/W Typ Typ C C VH = VCM +1.8V, VL = = VCM –1.8V RL ≥ 500Ω VO = 2.5V VO = 2.5V G = +1, RF = 25Ω, f < 100kHz MIN/ TEST MAX LEVEL(2) Single Supply Operation VS = 4.5V to 5.5V Pins 5 and 8 Limiter Pins Open VO = 2.5V f = 5MHz VIN = VCM ±1.2V (VO – VH) or (VO – VL) VIN = VCM ±1.2V, VO < 0.02Vp-p 2x Overdrive VIN = VCM to VCM ±1.2V Step VIN = VCM ±1.2V to VCM Step f = 5MHz, VO = 2Vp-p Specification: P, U Junction-to-Ambient NOTES: (1) Junction Temperature = Ambient Temperature for low temperature limit and 25°C guaranteed specifications. Junction Temperature = Ambient Temperature + 23°C at high temperature limit guaranteed specifications. (2) TEST LEVELS: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value for information only. (3) Current is considered positive out of node. (4) CMIR tested as < 3dB degradation from minimum CMRR at specified limits. (5) I VH (VH bias current) is negative, and I VL (VL bias current) is positive, under these conditions. See Note 3, Figures 2, and Figure 8. (6) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V H (or VL) when VIN = 0. (7) VH slew rate conditions are: V IN = VCM +0.4V, G = +2, V L = VCM –1.2V, VH = step between V CM + 1.2V and VCM. VL slew rate conditions are similar. (8) Linearity Guardband is defined for an output sinusoid (f = 5MHz, V O = VCM ±1Vp-p) centered between the limiter levels (V H and VL). It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 9). ® OPA688 4 ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Supply Voltage ................................................................................. ±6.5V Internal Power Dissipation .......................... See Thermal Characteristics Common-Mode Input Voltage ............................................................. ±VS Differential Input Voltage ..................................................................... ±VS Limiter Voltage Range ........................................................... ±(VS – 0.7V) Storage Temperature Range: P, U ................................ –40°C to +125°C Lead Temperature (DIP, soldering, 10s) ..................................... +300°C (SO-8, soldering, 3s) ...................................... +260°C Junction Temperature .................................................................... +175°C Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PIN CONFIGURATION Top View DIP-8, SO-8 NC 1 8 VH Inverting Input 2 7 +VS Non-Inverting Input 3 6 Output –VS 4 5 VL PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER OPA688P OPA688U DIP-8 Plastic DIP SO-8 Surface Mount 006 182 –40°C to +85°C –40°C to +85°C OPA688P OPA688U " " " " " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA OPA688P OPA688U OPA688U/2K5 Rails Rails Tape and Reel NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of OPA688U/2K5” will get a single 2500-piece Tape and Reel. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 5 OPA688 TYPICAL PERFORMANCE CURVES —VS = ±5V G = +2, RL = 500Ω, RF = 402Ω, VH = –VL = 2V (Figure 1 for AC performance only), unless otherwise noted. NON-INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 12 G = +1, RC = 175Ω, RF = 25Ω G = +2, RC = ∞ 3 0 RS 150Ω –3 –6 VIN VO –9 RC RF 0 –3 –6 –9 RG –15 G = +5, RC = ∞ –15 G = –5 –21 –24 –18 1M 10M 100M 1M 1G 10M 100M 1G Frequency (Hz) Frequency (Hz) LARGE-SIGNAL PULSE RESPONSE SMALL-SIGNAL PULSE RESPONSE 2.5 0.25 VO = 0.2Vp-p 0.20 VO = 4Vp-p 2.0 1.5 Output Voltage (V) 0.15 Output Voltage (V) G = –2 –12 –18 –12 0.10 0.05 0 –0.05 –0.10 VH = –VL = 2.5V 0.10 0.05 0 –0.5 –1.0 –0.15 –1.5 –0.20 –2.0 –2.5 –0.25 Time (5ns/div) Time (5ns/div) VL—LIMITED PULSE RESPONSE VH—LIMITED PULSE RESPONSE 2.5 2.5 2.0 2.0 Input and Output Voltages (V) Input and Output Voltages (V) G = –1 VO = 0.2Vp-p 3 Normalized Gain (dB) Normalized Gain (dB) 6 6 G = +1, RC = ∞, RF = 25Ω VO = 0.2Vp-p 9 INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 1.5 1.0 VIN 0.5 VO 0 –0.5 –1.0 G = +2 VH = +2V –1.5 G = +2 VL = –2V 1.5 1.0 0.5 0 –0.5 –1.0 VIN –1.5 –2.0 –2.0 –2.5 –2.5 Time (20ns/div) Time (20ns/div) ® OPA688 6 VO TYPICAL PERFORMANCE CURVES —VS = ±5V (cont.) G = +2, RL = 500Ω, RF = 402Ω, VH = –VL = 2V (Figure 1 for AC performance only), unless otherwise noted. HARMONIC DISTORTION NEAR LIMIT VOLTAGES 2nd and 3rd Harmonic Distortion (dBc) 2nd and 3rd Harmonic Distortion (dBc) HARMONIC DISTORTION vs FREQUENCY –40 VO = 2Vp-p RL = 500Ω –45 –50 –55 HD2 –60 –65 –70 HD3 –75 –80 –85 –90 1M 10M –40 VO = 0VDC ±1Vp f1 = 5MHz RL = 500Ω –45 –50 –55 –60 HD2 –65 –70 –75 HD3 –80 –85 –90 0.9 20M 1.0 1.1 1.2 Frequency (Hz) 1.5 1.6 1.7 1.8 1.9 2.0 3RD HARMONIC DISTORTION vs OUTPUT SWING 2ND HARMONIC DISTORTION vs OUTPUT SWING –40 RL = 500Ω –45 RL = 500Ω –45 3rd Harmonic Distortion (dBc) 2nd Harmonic Distortion (dBc) 1.4 ± Limit Voltage (V) –40 f1 = 20MHz –50 f1 = 10MHz –55 –60 –65 –70 f1 = 5MHz –75 f1 = 2MHz –80 f1 = 1MHz –50 –55 f1 = 2MHz –60 f1 = 5MHz –65 f1 = 1MHz f1 = 10MHz –70 f1 = 20MHz –75 –80 –85 –85 –90 –90 0.1 1.0 0.1 5.0 1.0 5.0 Output Swing (Vp-p) Output Swing (Vp-p) LARGE-SIGNAL FREQUENCY RESPONSE HARMONIC DISTORTION vs LOAD RESISTANCE 12 –40 VO = 2Vp-p f1 = 5MHz –45 –50 6 HD2 –55 3 –60 –65 ≤ 0.2Vp-p G = +2 9 Gain (dB) 2nd and 3rd Harmonic Distortion (dBc) 1.3 HD3 –70 2Vp-p 0 –3 –6 –75 –9 –80 –12 –85 –15 –18 –90 50 100 1M 1000 10M 100M 1G Frequency (Hz) Load Resistance (Ω) ® 7 OPA688 TYPICAL PERFORMANCE CURVES —VS = ±5V (cont.) G = +2, RL = 500Ω, RF = 402Ω, VH = –VL = 2V (Figure 1 for AC performance only), unless otherwise noted. FREQUENCY RESPONSE vs CAPACITIVE LOAD RS vs CAPACITIVE LOAD 12 70 9 Gain to Capacitive Load (dB) 80 60 RS (Ω) 50 40 30 20 10 VO = 0.2Vp-p CL = 0 6 CL = 10pF 3 CL = 100pF 0 –3 –6 200Ω VIN RS VO OPA688 –9 402Ω 1kΩ 402Ω –15 1kΩ is optional –18 0 1 10 100 1M 300 10M –60 30 –90 20 –120 VO = 0.2Vp-p 10 –150 0 –180 –10 –210 –20 –240 1G 10k 100k 1M 10M 100M Input Voltage Noise Density (nV/√Hz) Input Current Noise Density (pA/√Hz) 40 –30 Gain Open-Loop Phase (deg) Open-Loop Gain (dB) 100 0 Phase 1G INPUT NOISE DENSITY OPEN-LOOP FREQUENCY RESPONSE 60 50 100M Frequency (Hz) Capacitive Load (pF) Voltage Noise 10 6.3nV/√Hz Current Noise 2.0pA/√Hz 1 100 1k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) LIMITER SMALL-SIGNAL FREQUENCY RESPONSE LIMITER FEEDTHROUGH 6 –30 VO = 0.02Vp-p 3 –35 0 –40 –3 –45 –6 Feedthrough (dB) Limiter Gain (dB) CL –12 VH = 0.02Vp-p + 2.0VDC 200Ω –9 2VDC 8 –12 VO –15 402Ω –18 –50 VH = 0.02Vp-p + 2VDC 200Ω –55 8 –60 VO –65 402Ω –70 402Ω –21 402Ω –75 –24 –80 1M 10M 100M 1G 1M Frequency (Hz) ® OPA688 10M Frequency (Hz) 8 50M TYPICAL PERFORMANCE CURVES —VS = ±5V (cont.) G = +2, RL = 500Ω, RF = 402Ω, VH = –VL = 2V (Figure 1 for AC performance only), unless otherwise noted. CLOSED-LOOP OUTPUT IMPEDANCE LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE 100 Maximum Over Temperature G = +1 RF = 25Ω VO = 0.2Vp-p 10 1 0.1 1M 75 Limter Input Bias Current (µA) Output Impedance (Ω) 100 10M 100M 50 25 –25 –50 Limiter Headroom = +VS – VH = VL – (–VS) –75 Current = IVH or –IVL –100 1G Minimum Over Temperature 0 0.0 0.5 1.0 1.5 Frequency (Hz) SUPPLY AND OUTPUT CURRENTS vs TEMPERATURE 90 | Output Current, Sinking | 12 Output Current (mA) 14 80 10 –25 0 25 3.5 4.0 4.5 5.0 50 75 70 100 95 90 PSR– 85 PSRR 80 75 PSR+ 70 65 CMRR 60 55 50 –50 –25 0 Ambient Temperature (°C) 25 50 75 100 Ambient Temperature (°C) VOLTAGE RANGES vs TEMPERATURE 5.0 VH = –VL = 4.3V ±Voltage Range (V) Supply Current (mA) 100 Supply Current –50 3.0 100 110 Output Current, Sourcing 16 2.5 PSR AND CMR vs TEMPERATURE 120 PSR and CMR, Input Referred (dB) 20 18 2.0 Limiter Headroom (V) 4.5 Output Voltage Range 4.0 3.5 Common-Mode Input Range 3.0 –50 –25 0 25 50 75 100 Ambient Temperature (°C) ® 9 OPA688 TYPICAL PERFORMANCE CURVES —VS = +5V G = +2, RF = 402Ω, RL = 500Ω tied to VCM = 2.5V, VL = VCM –1.2V, VH = VCM +1.2V, (Figure 2 for AC performance only), unless otherwise noted. NON-INVERTING SMALL-SIGNAL FREQUENCY RESPONSE INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 12 6 6 G = +2, RC = ∞ 3 0 –3 RS 150Ω –6 VIN VO –9 RC RF –12 VO = 0.2Vp-p 3 G = +1, RC = 175Ω, RF = 25Ω Normalized Gain (dB) Normalized Gain (dB) G = +1, RC = ∞, RF = 25Ω VO = 0.2Vp-p 9 G = –1 0 G = –2 –3 G = –5 –6 –9 –12 –15 –18 G = +5, RC = ∞ RG –15 –21 –18 –24 1M 10M 100M 1G 1M 10M Frequency (Hz) LARGE-SIGNAL FREQUENCY RESPONSE 12.0 VH = VCM +1.2V VL = VCM –1.2V 6.0 Input and Output Voltages (V) 4.5 ≤ 0.2Vp-p 3.0 0 –3.0 1G VH AND VL—LIMITED PULSE RESPONSE 5.0 G = +2 9.0 Gain (dB) 100M Frequency (Hz) 2.0Vp-p –6.0 –9.0 –12.0 –15.0 4.0 3.5 3.0 2.5 VO VIN VCM = 2.5V 2.0 VIN 1.5 VO 1.0 0.5 –18.0 0 1M 10M 100M 1G Time (20ns/div) Frequency (Hz) HARMONIC DISTORTION NEAR LIMIT VOLTAGES 2nd and 3rd Harmonic Distortion (dBc) 2nd and 3rd Harmonic Distortion (dBc) HARMONIC DISTORTION vs FREQUENCY –40 VO = 2Vp-p RL = 500Ω –45 –50 –55 HD2 –60 –65 HD3 –70 –75 –80 –85 –90 –40 VO = 2.5V ±1Vp f1 = 5MHz RL = 500Ω –45 –50 –55 –60 HD2 –65 –70 HD3 –75 –80 –85 –90 1M 10M 20M 0.9 ® OPA688 1.0 1.1 1.2 1.3 1.4 1.5 | Limit Voltages – 2.5VDC | Frequency (Hz) 10 1.6 1.7 1.8 TYPICAL APPLICATIONS it matches, and a 500Ω load. The power supply bypass capacitors are shown explicitly in Figures 1 and 2, but will be assumed in the other figures. The limiter voltages (VH and VL) and their bias currents (IVH and IVL) have the polarities shown. Notice that the single supply circuit can use 3 resistors to set VH and VL, where the dual supply circuit usually uses 4 to reference the limit voltages to ground. DUAL SUPPLY, NON-INVERTING AMPLIFIER Figure 1 shows a non-inverting gain amplifier for dual supply operation. This circuit was used for AC characterization of the OPA688, with a 50Ω source, which it matches, and a 500Ω load. The power supply bypass capacitors are shown explicitly in Figures 1 and 2, but will be assumed in the other figures. The limiter voltages (VH and VL) and their bias currents (IVH and IVL) have the polarities shown. LIMITED OUTPUT, ADC INPUT DRIVER Figure 3 shows a simple ADC driver that operates on single supply, and gives excellent distortion performance. The limit voltages track the input range of the converter, completely protecting against input overdrive. SINGLE SUPPLY, NON-INVERTING AMPLIFIER Figure 2 shows an AC coupled, non-inverting gain amplifier for single supply operation. This circuit was used for AC characterization of the OPA688, with a 50Ω source, which 3.01kΩ 1.91kΩ +VS = +5V VS = +5V + 2.2µF 0.1µF 0.1µF + VH = +2V 0.1µF 2.2µF 523Ω 0.1µF 174Ω VH = 3.7V 7 3 VIN IVH 8 49.9Ω 5 VO IVL 3 IVH 7 VIN 57.6Ω 500Ω 806Ω OPA688 2 5 4 0.1µF 976Ω 8 4 RF 402Ω RG 402Ω 0.1µF 6 OPA688 2 806Ω 0.1µF 6 VO 500Ω IVL RF 402Ω 0.1µF VL = –2V 0.1µF RG 402Ω + 2.2µF 3.01kΩ VL = 1.3V 523Ω 0.1µF 1.91kΩ –VS = –5V FIGURE 1. DC-Coupled, Dual Supply Amplifier. FIGURE 2. AC-Coupled, Single Supply Amplifier. VS = +5V 562Ω VH = +3.6V 0.1µF 715Ω VS = +5V 102Ω +3.5V VS = +5V REFT 0.1µF 3 VIN RSEL +VS 7 8 OPA688 6 24.9Ω 5 2 ADS822 10-Bit 40MSPS IN 100pF 10-Bit Data 4 715Ω REFB 402Ω INT/EXT GND +1.5V 102Ω 402Ω 0.1µF VL = +1.4V 0.1µF 562Ω FIGURE 3. Single Supply, Limiting ADC Input Driver. ® 11 OPA688 PRECISION HALF WAVE RECTIFIER When VO tries to go below ground, CCII charges C1 through D1, which restores the output back to ground. D1 adds a propagation delay to the restoration process, which then has an exponential decay with time constant R1C1/G (G = +2 = the OPA688 gain). When the signal is above ground, it decays to ground with a time constant of R2C1. The OPA688 output recovers very quickly from overdrive. Figure 4 shows a half wave rectifier with outstanding precision and speed. VH (pin 8) will default to a voltage between 3.1 and 3.8V if left open, while the negative limit is set to ground. +VS = +5V 200Ω 7 2 VIN NC 8 OPA688 3.01kΩ 1.91kΩ +VS = +5V 6 VO 5 3 0.1µF 4 402Ω 200Ω 402Ω 402Ω VO VIN –VS = –5V 3 7 8 FIGURE 4. Precision Half Wave Rectifier. 6 OPA688 133Ω 2 VERY HIGH SPEED SCHMITT TRIGGER Figure 5 shows a very high speed Schmitt trigger. The output levels are precisely defined, and the switching time is exceptional. The output voltage swings between ±2V. 5 4 0.1µF 3.01kΩ 1.91kΩ –VS = –5V UNITY-GAIN BUFFER Figure 6 shows a unity-gain voltage buffer using the OPA688. The feedback resistor (RF) isolates the output from any board inductance between pins 2 and 6. We recommend that RF ≥ 24.9Ω for unity-gain buffer applications. RC is an optional compensation resistor that reduces the peaking typically seen at G = +1. Choosing RC = RS + RF gives a unity gain buffer with approximately the G = +2 frequency response. FIGURE 5. Very High Speed Schmitt Trigger. RS VS RF 24.9Ω DC RESTORER Figure 7 shows a DC restorer using the OPA688 and OPA660. The OPA660’s OTA amplifier is used as a current conveyor (CCII) in this circuit, with a current gain of 1.0. VIN 5 FIGURE 6. Unity-Gain Buffer. C1 100pF U1 200Ω 20Ω 6 +1 D1 1 RQ 1kΩ U1 = OPA660 RQ = 1kΩ (sets U1’s IQ) D1, D2 = 1N4148 R2 100kΩ VH = +3V 8 OPA688 VO 5 D2 VL = –1V 402Ω U1 C 20Ω 3 402Ω CCII B 2 E FIGURE 7. DC Restorer. ® OPA688 OPA688 RC 12 R1 40.2Ω VO DESIGN-IN TOOLS The limiters have a very sharp transition from the linear region of operation to output limiting. This allows the limiter voltages to be set very near (<100mV) the desired signal range. The distortion performance is also very good near the limiter voltages. APPLICATIONS SUPPORT The Burr-Brown Applications Department is available for design assistance at 1-800-548-6132 (US/Canada only). The Burr-Brown Internet web page (http://www.burr-brown.com) has the latest data sheets and other design aids. CIRCUIT LAYOUT Achieving optimum performance with the high frequency OPA688 requires careful attention to layout design and component selection. Recommended PCB layout techniques and component selection criteria are: DEMONSTRATION BOARDS Two PC boards are available to assist in the initial evaluation of circuit performance of the OPA688 in both package styles. These are available as an unpopulated PCB with descriptive documentation. See the demonstration board literature for more information. The summary information for these boards is shown below: DEMONSTRATION BOARD DEM-OPA68xP DEM-OPA68xU PACKAGE PRODUCT LITERATURE REQUEST NUMBER 8-Pin DIP SO-8 OPA68xP OPA68xU MKT-350 MKT-351 a) Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Open a window in the ground and power planes around the signal I/O pins, and leave the ground and power planes unbroken elsewhere. b) Provide a high quality power supply. Use linear regulators, ground plane and power planes to provide power. Place high frequency 0.1µF decoupling capacitors < 0.2" away from each power supply pin. Use wide, short traces to connect to these capacitors to the ground and power planes. Also use larger (2.2µF to 6.8µF) high frequency decoupling capacitors to bypass lower frequencies. They may be somewhat further from the device, and be shared among several adjacent devices. Contact the Burr-Brown Application Department for availability of these boards. c) Place external components close to the OPA688. This minimizes inductance, ground loops, transmission line effects and propagation delay problems. Be extra careful with the feedback (RF), input and output resistors. SPICE MODELS Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for high speed active devices, like the OPA688, where parasitic capacitance and inductance can have a major effect on frequency response. d) Use high frequency components to minimize parasitic elements. Resistors should be a very low reactance type. Surface mount resistors work best and allow a tighter layout. Metal film or carbon composition axially-leaded resistors can also provide good performance when their leads are as short as possible. Never use wirewound resistors for high frequency applications. Remember that most potentiometers have large parasitic capacitances and inductances. SPICE models are available through the Burr-Brown web site (www.burr-brown.com). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion, temperature effects or differential gain and phase characteristics. These models do not distinguish between the AC performance of different package types. Multilayer ceramic chip capacitors work best and take up little space. Monolithic ceramic capacitors also work very well. Use RF type capacitors with low ESR and ESL. The large power pin bypass capacitors (2.2µF to 6.8µF) should be tantalum for better high frequency and pulse performance. OPERATING INFORMATION e) Choose low resistor values to minimize the time constant set by the resistor and its parasitic parallel capacitance. Good metal film or surface mount resistors have approximately 0.2pF parasitic parallel capacitance. For resistors > 1.5kΩ, this adds a pole and/or zero below 500MHz. THEORY OF OPERATION The OPA688 is a voltage feedback op amp that is unity-gain stable. The output voltage is limited to a range set by the voltage on the limiter pins (5 and 8). When the input tries to overdrive the output, the limiters take control of the output buffer. This avoids saturating any part of the signal path, giving quick overdrive recovery and excellent limiter accuracy at any signal gain. Make sure that the output loading is not too heavy. The recommended 402Ω feedback resistor is a good starting point in your design. ® 13 OPA688 OUTPUT LIMITERS f) Use short direct traces to other wideband devices on the board. Short traces act as a lumped capacitive load. Wide traces (50 to 100 mils) should be used. Estimate the total capacitive load at the output, and use the series isolation resistor recommended in the RS vs Capacitive Load plot. Parasitic loads < 2pF may not need the isolation resistor. The output voltage is linearly dependent on the input(s) when it is between the limiter voltages VH (pin 8) and VL (pin 5). When the output tries to exceed VH or VL, the corresponding limiter buffer takes control of the output voltage and holds it at VH or VL. g) When long traces are necessary, use transmission line design techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω transmission line is not required on board—a higher characteristic impedance will help reduce output loading. Use a matching series resistor at the output of the op amp to drive a transmission line, and a matched load resistor at the other end to make the line appear as a resistor. If the 6dB of attenuation that the matched load produces is not acceptable, and the line is not too long, use the series resistor at the source only. This will isolate the source from the reactive load presented by the line, but the frequency response will be degraded. Because the limiters act on the output, their accuracy does not change with gain. The transition from the linear region of operation to output limiting is very sharp—the desired output signal can safely come to within 30mV of VH or VL with no onset of non-linearity. The limiter voltages can be set to within 0.7V of the supplies (VL ≥ –VS + 0.7V, VH ≤ +VS – 0.7V). They must also be at least 200mV apart (VH – VL ≥ 0.2V). When pins 5 and 8 are left open, VH and VL go to the Default Voltage Limit; the minimum values are in the spec table. Looking at Figure 8 for the zero bias current case will show the expected range of (Vs – default limit voltages) = headroom. Multiple destination devices are best handled as separate transmission lines, each with its own series source and shunt load terminations. Any parasitic impedances acting on the terminating resistors will alter the transmission line match, and can cause unwanted signal reflections and reactive loading. When the limiter voltages are more than 2.1V from the supplies (VL ≥ –VS + 2.1V or VH ≤ +VS – 2.1V), you can use simple resistor dividers to set VH and VL (see Figure 1). Make sure you include the Limiter Input Bias Currents (Figure 8) in the calculations (i.e., IVL ≈ –50µA out of pin 5, and IVH ≈ +50µA out of pin 8). For good limiter voltage accuracy, run at least 1mA quiescent bias current through these resistors. h) Do not use sockets for high speed parts like the OPA688. The additional lead length and pin-to-pin capacitance introduced by the socket creates an extremely troublesome parasitic network. Best results are obtained by soldering the part onto the board. If socketing for DIP prototypes is desired, high frequency flush mount pins (e.g., McKenzie Technology #710C) can give good results. LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE Limter Input Bias Current (µA) 100 POWER SUPPLIES The OPA688 is nominally specified for operation using either ±5V supplies or a single +5V supply. The maximum specified total supply voltage of 12V allows reasonable tolerances on the supplies. Higher supply voltages can break down internal junctions, possibly leading to catastrophic failure. Single supply operation is possible as long as common mode voltage constraints are observed. The common mode input and output voltage specifications can be interpreted as a required headroom to the supply voltage. Observing this input and output headroom requirement will allow design of non-standard or single supply operation circuits. Figure 2 shows one approach to single-supply operation. Maximum Over Temperature 75 50 25 Minimum Over Temperature 0 –25 –50 Limiter Headroom = +VS – VH = VL – (–VS) –75 Current = IVH or –IVL –100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Limiter Headroom (V) FIGURE 8. Limiter Bias Current vs Bias Voltage. ESD PROTECTION ESD damage has been known to damage MOSFET devices, but any semiconductor device is vulnerable to ESD damage. This is particularly true for very high speed, fine geometry processes. When the limiter voltages need to be within 2.1V of the supplies (VL ≤ –VS + 2.1V or VH ≥ +VS – 2.1V), consider using low impedance buffers to set VH and VL to minimize errors due to bias current uncertainty. This will typically be the case for single supply operation (VS = +5V). Figure 2 runs 2.5mA through the resistive divider that sets VH and VL. This keeps errors due to IVH and IVL < ±1% of the target limit voltages. ESD damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers, this may cause a noticeable degradation of offset voltage and drift. Therefore, ESD handling precautions are required when handling the OPA688. ® OPA688 14 The limiters’ DC accuracy depends on attention to detail. The two dominant error sources can be improved as follows: +VS R2 • Power supplies, when used to drive resistive dividers that set VH and VL, can contribute large errors (e.g., ±5%). Using a more accurate source, and bypassing pins 5 and 8 with good capacitors, will improve limiter PSRR. RTRIM 47kΩ OPA688 VO –VS • The resistor tolerances in the resistive divider can also dominate. Use 1% resistors. 0.1µF Other error sources also contribute, but should have little impact on the limiters’ DC accuracy: R1 R3 = R1 || R2 VIN or Ground • Reduce offsets caused by the Limiter Input Bias Currents. Select the resistors in the resistive divider(s) as described above. NOTES: (1) R3 is optional and minimizes output offset due to input bias currents. (2) Set R1 << RTRIM. • Consider the signal path DC errors as contributing to uncertainty in the useable output swing. FIGURE 10. Offset Voltage Trim. • The Limiter Offset Voltage only slightly degrades limiter accuracy. makes the OPA688 an ideal choice for a wide range of high frequency applications. Figure 9 shows how the limiters affect distortion performance. Virtually no degradation in linearity is observed for output voltage swinging right up to the limiter voltages. Many high speed applications, such as driving A/D converters, require op amps with low output impedance. As shown in the Output Impedance vs Frequency performance curve, the OPA688 maintains very low closed-loop output impedance over frequency. Closed-loop output impedance increases with frequency since loop gain decreases with frequency. 2nd and 3rd Harmonic Distortion (dBc) HARMONIC DISTORTION NEAR LIMIT VOLTAGES –40 VO = 0VDC ±1Vp f1 = 5MHz RL = 500Ω –45 –50 THERMAL CONSIDERATIONS The OPA688 will not require heat-sinking under most operating conditions. Maximum desired junction temperature will set a maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. –55 –60 HD2 –65 –70 –75 HD3 –80 The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and the additional power dissipated in the output stage (PDL) while delivering load power. PDQ is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signals and loads. For a grounded resistive load, and equal bipolar supplies, it is at a maximum when the output is at 1/2 either supply voltage. In this condition, PDL = VS2/ (4RL) where RL includes the feedback network loading. Note that it is the power in the output stage, and not in the load, that determines internal power dissipation. –85 –90 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 ± Limit Voltage (V) FIGURE 9. Harmonic Distortion Near Limit Voltages. OFFSET VOLTAGE ADJUSTMENT The circuit in Figure 10 allows offset adjustment without degrading offset drift with temperature. Use this circuit with caution since power supply noise can inadvertently couple into the op amp. The operating junction temperature is: TJ = TA + PD θJA, where TA is the ambient temperature. For example, the maximum TJ for a OPA688U with G = +2, RFB = 402Ω, RL = 100Ω, and ±VS = ±5V at the maximum TA = +85°C is calculated as: Remember that additional offset errors can be created by the amplifier’s input bias currents. Whenever possible, match the impedance seen by both DC input bias currents using R3. This minimizes the output offset voltage caused by the input bias currents. P DQ = (10V • 20mA ) = 200mW P DL = OUTPUT DRIVE ( 5V )2 4 • (100Ω ||804Ω ) = 70mW P D = 200mW + 70mW = 270mW The OPA688 has been optimized to drive 500Ω loads, such as A/D converters. It still performs very well driving 100Ω loads; the specifications are shown for the 500Ω load. This T J = 85° C + 270mW •125° C / W = 119° C ® 15 OPA688 CAPACITIVE LOADS capacitance from the inverting input to ground causes peaking or oscillations. To compensate for this effect, connect a small capacitor in parallel with the feedback resistor. The bandwidth will be limited by the pole that the feedback resistor and this capacitor create. In other high gain applications, use a three resistor “Tee” network to reduce the RC time constants set by the parasitic capacitances. Be careful to not increase the noise generated by this feedback network too much. Capacitive loads, such as the input to ADCs, will decrease the amplifier’s phase margin, which may cause high frequency peaking or oscillations. Capacitive loads ≥ 2pF should be isolated by connecting a small resistor in series with the output as shown in Figure 11. Increasing the gain from +2 will improve the capacitive drive capabilities due to increased phase margin. In general, capacitive loads should be minimized for optimum high frequency performance. The capacitance of coax cable (29pF/foot for RG-58) will not load the amplifier when the coaxial cable, or transmission line, is terminated in its characteristic impedance. PULSE SETTLING TIME The OPA688 is capable of an extremely fast settling time in response to a pulse input. Frequency response flatness and phase linearity are needed to obtain the best settling times. For capacitive loads, such as an A/D converter, use the recommended RS in the RS vs Capacitive Load plot. Extremely fine scale settling (0.01%) requires close attention to ground return current in the supply decoupling capacitors. The pulse settling characteristics when recovering from overdrive are very good. RS VO OPA688 RL DISTORTION The OPA688’s distortion performance is specified for a 500Ω load, such as an A/D converter. Driving loads with smaller resistance will increase the distortion as illustrated in Figure 12. Remember to include the feedback network in the load resistance calculations. CL RL is optional FIGURE 11. Driving Capacitive Loads. FREQUENCY RESPONSE COMPENSATION HARMONIC DISTORTION vs LOAD RESISTANCE 2nd and 3rd Harmonic Distortion (dBc) The OPA688 is internally compensated to be unity-gain stable, and has a nominal phase margin of 60° at a gain of +2. Phase margin and peaking improve at higher gains. Recall that an inverting gain of –1 is equivalent to a gain of +2 for bandwidth purposes (i.e., noise gain = 2). Standard external compensation techniques work with this device. For example, in the inverting configuration, the bandwidth may be limited without modifying the inverting gain by placing a series RC network to ground on the inverting node. This has the effect of increasing the noise gain at high frequencies, which limits the bandwidth. VO = 2Vp-p f1 = 5MHz –45 –50 HD2 –55 –60 –65 HD3 –70 –75 –80 –85 –90 50 To maintain a wide bandwidth at high gains, cascade several op amps, or use the high gain optimized OPA689. 100 1000 Load Resistance (Ω) In applications where a large feedback resistor is required, such as photodiode transimpedance amplifier, the parasitic FIGURE 12. 5MHz Harmonic Distortion vs Load Resistance. ® OPA688 –40 16