OPA843 OPA 843 SBOS268A – DECEMBER 2002 – OCTOBER 2003 Wideband, Low Distortion, Medium Gain, Voltage-Feedback OPERATIONAL AMPLIFIER FEATURES DESCRIPTION ● HIGH BANDWIDTH: 260MHz (G = +5) The OPA843 provides a level of speed and dynamic range previously unattainable in a monolithic op amp. Using a high Gain Bandwidth (GBW), two gain-stage design, the OPA843 gives a medium gain range device with exceptional dynamic range. The “classic” differential input complements this high dynamic range with DC precision beyond most high-speed amplifier products. Very low input offset voltage and current, high Common-Mode Rejection Ratio (CMRR) and PowerSupply Rejection Ratio (PSRR), and high open-loop gain combine to give a high DC precision amplifier along with low noise and high 3rd-order intercept. ● GAIN BANDWIDTH PRODUCT: 800MHz ● LOW INPUT VOLTAGE NOISE: 2.0nV/ √Hz ● VERY LOW DISTORTION: –96dBc (5MHz) ● HIGH OPEN-LOOP GAIN: 110dB ● FAST 12-BIT SETTLING: 10.5ns (0.01%) ● LOW INPUT OFFSET VOLTAGE: 300µV ● OUTPUT CURRENT: ±100mA 12- to 16-bit converter interfaces will benefit from this combination of features. High-speed transimpedance applications can be implemented with exceptional DC precision as well. Differential configurations using two OPA843s can deliver very low distortion to high output voltages, as shown below. APPLICATIONS ● ADC/DAC BUFFER AMPLIFIER ● LOW DISTORTION “IF” AMPLIFIER ● ACTIVE FILTERS ● LOW-NOISE RECEIVER OPA843 RELATED PRODUCTS ● WIDEBAND TRANSIMPEDANCE ● TEST INSTRUMENTATION ● PROFESSIONAL AUDIO ● OPA643 UPGRADE SINGLES INPUT NOISE VOLTAGE (nV/ √Hz ) GAIN-BANDWIDTH PRODUCT (MHz) OPA842 OPA846 OPA847 2.6 1.2 0.85 200 1750 3900 +5V DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE OPA843 –85 VI 50Ω 1:1 132Ω 402Ω 40.2Ω 402Ω RL 400Ω Harmonic Distortion (dBc) –5V 40.2Ω VO = 10VI +5V GD = 10 RL = 400Ω F = 5MHz –90 –95 2nd-Harmonic –100 3rd-Harmonic –105 OPA843 –110 1 –5V 10 Output Voltage Swing (Vp-p) Very Low Distortion Differential Driver Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2002-2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Power Supply ............................................................................... ±6.5VDC Internal Power Dissipation ...................................... See Thermal Analysis Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Voltage Range: D, DBV ................................... –40°C to +125°C Lead Temperature (soldering, 10s) ............................................... +300°C Junction Temperature (TJ) ............................................................ +150°C ESD Rating (Human Body Model) .................................................. 2000V (Charge Device Model) ............................................... 1500V (Machine Model) ........................................................... 200V This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING SO-8 D –40°C to +85°C OPA843 OPA843ID Rails, 100 " " " " OPA843IDR Tape and Reel, 2500 SOT23-5 DBV –40°C to +85°C OARI OPA843IDBVT Tape and Reel, 250 " " " " OPA843IDBVR Tape and Reel, 3000 OPA843 " OPA843 " ORDERING NUMBER TRANSPORT MEDIA, QUANTITY NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PIN CONFIGURATIONS 8 NC Inverting Input 2 7 +VS Noninverting Input 3 6 Output –VS 4 5 NC Output 1 –VS 2 Noninverting Input 3 NC = No Connection 5 +VS 4 Inverting Input 1 OARI 3 1 SOT 2 NC Top View 4 SO 5 Top View Pin Orientation/Package Marking 2 OPA843 www.ti.com SBOS268A ELECTRICAL CHARACTERISTICS: VS = ±5V Boldface limits are tested at +25°C. At TA = +25°C, VS = ±5V, RF = 402Ω, RL = 100Ω, and G = +5, unless otherwise noted. See Figure 1 for AC performance. OPA843ID, OPA843IDBV TYP PARAMETER AC PERFORMANCE (see Figure 1) Small-Signal Bandwidth (VO = 200mVp-p) Gain-Bandwidth Product Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +3 Harmonic Distortion 2nd-Harmonic 3rd-Harmonic 2-Tone, 3rd-Order Intercept Input Voltage Noise Input Current Noise Rise-and-Fall Time Slew Rate Settling Time to 0.01% 0.1% 1.0% Differential Gain Differential Phase DC PERFORMANCE(4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Offset Current Input Offset Current Drift INPUT Common-Mode Input Range (CMIR)(5) Common-Mode Rejection (CMRR) Input Impedance Differential-Mode Common-Mode OUTPUT Output Voltage Swing Current Output Closed-Loop Output Impedance POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Minimum Operating Voltage Max Quiescent Current Min Quiescent Current Power-Supply Rejection Ratio (+PSRR, –PSRR) THERMAL CHARACTERISTICS Specified Operating Range: D, DBV Thermal Resistance, θJA D SO-8 DBV SOT23-5 MIN/MAX OVER TEMPERATURE CONDITIONS +25°C +25°C(1) 0°C to 70°C –40°C to +85°C(2) G = +3 G = +5 G = +10 G = +20 500 260 85 40 800 65 3.5 185 66 30 562 34 180 65 30 560 33 175 64 30 558 32 –74 –94 –100 –105 –72 –92 –98 –102 –70 –90 –95 –100 2.2 3.35 1.95 650 2.31 3.4 2.0 600 2.36 3.45 2.1 525 10 5.4 10.3 5.8 10.6 6.4 100 96 ±1.4 ±4 –36 25 ±1.15 ±2 ±2.9 84 G = +5, RL = 100Ω, VO = 200mVp-p G = +5, f = 5MHz, VO = 2Vp-p RL = 100Ω RL = 500Ω RL = 100Ω RL = 500Ω G = +5, f = 25MHz f > 1MHz f > 1MHz 0.2V Step 2V Step 2V Step 2V Step 2V Step G = +4, NTSC, RL = 150Ω G = +4, NTSC, RL = 150Ω –76 –96 –102 –110 40 2.0 2.8 1.2 1000 10.5 7.5 3.2 0.001 0.012 VO = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V 110 ±0.30 ±1.20 –20 –35 ±0.25 ±1.0 VCM = ±1V, Input Referred ±3.2 95 ±3.0 VCM = 0V VCM = 0V 12 || 1 3.2 || 1.2 RL > 1kΩ, Positive Output RL > 1kΩ, Negative Output RL = 100Ω, Positive Output RL = 100Ω, Negative Output VO = 0V G = +5, f = 1kHz 3.2 –3.7 3.0 –3.5 ±100 0.0001 85 UNITS MIN/ MAX TEST LEVEL(3 ) MHz MHz MHz MHz MHz MHz dB typ min min min min min typ C B B B B B C dBc dBc dBc dBc dBm nV/√Hz pA/√Hz ns V/µs ns ns ns % deg max max max max typ max max max min typ max max typ typ B B B B C B B B B C B B C C 92 ±1.5 ±4 –37 25 ±1.17 ±2 dB mV µV/°C µA nA/°C µA nA/°C min max max max max max max A A B A B A B ±2.8 82 V dB min min A A kΩ || pF MΩ || pF typ typ C C V V V V mA Ω min min min min min typ A A A A A C 3.0 –3.5 2.8 –3.3 ±90 2.9 –3.4 2.7 –3.2 ±85 2.8 –3.3 2.6 –3.1 ±80 ±6 ±4 ±6 ±4 22.5 18.3 V V V mA mA typ max min max min C A A A A 85 dB min A –40 to +85 °C typ C 125 150 °C °C typ typ C C ±5 VS = ±5V VS = ±5V 20.2 20.2 20.8 19.6 ±6 ±4 22.2 19.1 |VS| = 4.5V to 5.5V, Input Referred 100 90 88 Junction-to-Ambient NOTES: (1) Junction temperature = ambient temperature for 25°C min/max specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C at high temperature limit for over temperature min/max specifications. (3) Test Levels: (A) 100% tested at 25°C over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive outof-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at ±CMIR limits. OPA843 SBOS268A www.ti.com 3 TYPICAL CHARACTERISTICS: VS = ±5V TA = +25°C, G = +5, RF = 402Ω, RG = 100Ω, and RL = 100Ω, unless otherwise noted. NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE 6 VO = 0.2Vp-p INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 3 G = +3 3 Normalized Gain (dB) Normalized Gain (dB) G = +5 0 –3 G = +10 –6 G = +20 –9 –12 –3 RG = RS = 50Ω VO = 0.2Vp-p –6 –9 G = –16 –12 G = –32 –15 –15 See Figure 1 See Figure 2 –18 –18 106 17 14 107 109 108 106 107 Frequency (Hz) NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE INVERTING LARGE-SIGNAL FREQUENCY RESPONSE 21 RL = 100Ω G = +5V/V 0.2Vp-p 1Vp-p 2Vp-p 18 200mVp-p to 1Vp-p RL = 100Ω G = –8V/V 15 109 108 Frequency (Hz) 12 Gain (dB) 11 Gain (dB) G = –4 G = –8 0 5Vp-p 8 2Vp-p 9 5Vp-p 6 3 5 0 2 –3 See Figure 1 108 107 109 108 Frequency (Hz) Frequency (Hz) NONINVERTING PULSE RESPONSE INVERTING PULSE RESPONSE Right Scale 100 G = –8 1.2 0.8 0.4 0 Small Signal ± 100mV –100 Left Scale –200 0 –0.4 –0.8 Output Voltage (100mV/div) 200 Large Signal ± 1V Output Voltage (400mV/div) G = +5 200 Large Signal ± 1V Right Scale 100 1.2 0.8 0.4 0 Small Signal ± 100mV –100 Left Scale –200 0 –0.4 –0.8 –1.2 –1.2 See Figure 2 See Figure 1 Time (2ns/div) 4 109 Time (2ns/div) OPA843 www.ti.com SBOS268A Output Voltage (400mV/div) 107 Output Voltage (100mV/div) See Figure 2 –6 –1 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = +25°C, G = +5, RF = 402Ω, RG = 100Ω, and RL = 100Ω, unless otherwise noted. 5MHz HARMONIC DISTORTION vs LOAD RESISTANCE 1MHz HARMONIC DISTORTION vs LOAD RESISTANCE –75 –75 VO = 2Vp-p G = +5 VO = 5Vp-p G = +5 –80 Harmonic Distortion (dBc) Harmonic Distortion (dBc) –80 –85 2nd-Harmonic –90 –95 –100 3rd-Harmonic –105 –85 –90 2nd-Harmonic –95 –100 3rd-Harmonic –105 See Figure 1 See Figure 1 –110 –110 100 150 200 250 300 350 400 450 500 100 150 200 Resistance (Ω) –70 2nd-Harmonic –80 –90 3rd-Harmonic 450 500 –80 –85 2nd-Harmonic –90 –95 3rd-Harmonic –100 –105 See Figure 1 See Figure 1 –110 –110 1 10 0.1 100 1 10 Output Voltage Swing (Vp-p) Frequency (MHz) HARMONIC DISTORTION vs INVERTING GAIN HARMONIC DISTORTION vs NONINVERTING GAIN –75 –70 2nd-Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) 400 RL = 200Ω F = 5MHz G = +5 –75 Harmonic Distortion (dBc) Harmonic Distortion (dBc) VO = 2Vp-p G = +5 RL = 200Ω 0.1 350 HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs FREQUENCY –100 300 Resistance (Ω) –60 –70 250 –80 VO = 2Vp-p RL = 200Ω F = 5MHz RF = 402Ω, RG Adjusted –90 –100 3rd-Harmonic 10 15 –95 –105 3rd-Harmonic –115 5 20 10 15 20 25 30 35 40 Gain (–V/V) Gain (V/V) OPA843 SBOS268A VO = 2Vp-p RL = 200Ω F = 5MHz RG = 50Ω, RF Adjusted See Figure 2 See Figure 1 –110 5 2nd-Harmonic –85 www.ti.com 5 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = +25°C, G = +5, RF = 402Ω, RG = 100Ω, and RL = 100Ω, unless otherwise noted. 2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT INPUT VOLTAGE AND CURRENT NOISE DENSITY 10 55 PI G = +5 Current Noise Intercept Point (+dBm) Voltage Noise nV/√Hz Current Noise pA/√Hz 50 2.8pA/√Hz Voltage Noise 2.0nV/√Hz 50Ω PO OPA843 50Ω 50Ω 402Ω 45 100Ω 40 35 30 1 25 102 103 104 105 106 107 10 15 20 25 30 NONINVERTING GAIN FLATNESS TUNE VO = 200mVp-p AV = +4 0.30 0.20 NG = 4 NG = 4.5 0 –0.10 NG = 5 –0.20 NG = 5.5 –0.30 55 60 65 70 1 G = –1 0 –1 –2 G = –2 –3 –4 External Compensation See Figure 11 –5 G = –3 –6 1 10 100 1k 1 10 Frequency (MHz) Normalized Gain to Capacitive Load (dB) 10 1 10 100 1k FREQUENCY RESPONSE vs CAPACITIVE LOAD G = +5 1 100 Frequency (MHz) RECOMMENDED RS vs CAPACITIVE LOAD 100 RS (Ω) 50 VO = 200mVp-p 2 –0.40 17 RS adjusted to cap load. 14 C = 10pF C = 100pF 11 C = 22pF VI 8 50Ω RS VO OPA843 CL C = 47pF 1kΩ 402Ω 5 100Ω 1kΩ is optional. 2 106 1k 107 108 109 Frequency (Hz) Capacitive Load (pF) 6 45 LOW GAIN INVERTING BANDWIDTH External Compensation See Figure 10 0.10 40 3 Normalized Gain (1dB/div) Deviation from 12dB Gain (0.1dB/div) 0.40 35 Frequency (MHz) Frequency (Hz) OPA843 www.ti.com SBOS268A TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = +25°C, G = +5, RF = 402Ω, RG = 100Ω, and RL = 100Ω, unless otherwise noted. OPEN-LOOP GAIN AND PHASE CMRR AND PSRR vs FREQUENCY 120 CMRR 80 –PSRR 60 40 –30 20log (AOL) 80 –60 ∠AOL 60 20 40 –120 20 –150 0 –180 –20 102 103 104 105 106 107 103 104 107 108 CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY 109 10 1 1W Internal Power Limit Output Impedance (Ω) RL = 100 RL = 50 0 RL = 25 –1 1W Internal Power Limit –2 OPA843 ZO 0.1 402Ω 0.01 100Ω 0.001 0.0001 –3 0.00001 –0.1 –0.05 0 0.05 0.1 102 0.15 103 104 NONINVERTING OVERDRIVE RECOVERY 4 3 Output Left Scale 106 107 108 RL = 100Ω G=5 See Figure 1 INVERTING OVERDRIVE RECOVERY 1 5 0.8 4 0.6 3 0.4 1 0.2 0 0 –1 –0.2 –2 –0.4 –3 –0.6 –4 –5 Output Voltage (1V/div) Input Right Scale Input Voltage (200mV/div) 5 105 Frequency (Hz) IO (mA) 2 1 RL = 100Ω G = –8 See Figure 2 Input Right Scale 0.6 0.2 0 –1 0.8 0.4 1 0 Output Left Scale –0.2 –2 –0.4 –3 –0.6 –0.8 –4 –0.8 –1 –5 Time (40ns/div) –1 Time (40ns/div) OPA843 SBOS268A 106 OUTPUT VOLTAGE AND CURRENT LIMITATIONS 2 2 105 Frequency (Hz) 3 –4 –0.15 102 Frequency (Hz) 4 1 –210 101 108 Input Voltage (200mV/div) 101 Output Voltage (1V/div) –90 Open-Loop Phase (°) 100 100 0 VO (V) 0 +PSRR Open-Loop Gain (dB) Common-Mode Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) 120 www.ti.com 7 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = +25°C, G = +5, RF = 402Ω, RG = 100Ω, and RL = 100Ω, unless otherwise noted. SETTLING TIME VIDEO DIFFERENTIAL GAIN/DIFFERENTIAL PHASE 0.20 Differential Gain (%) 0.15 0.1 G = +4 0.10 0.05 0 –0.05 –0.10 –0.15 0.015 0.075 dP, Negative Video 0.01 0.05 dP, Positive Video 0.005 0.025 dG, Positive Video –0.20 See Figure 1 –0.25 0 0 5 10 15 20 0 25 1 2 Time (ns) TYPICAL DC DRIFT OVER TEMPERATURE VIO 0 0 100 x IOS –0.5 –12.5 IB –1 Output Current (2mA/div) 12.5 25 50 75 100 22 106 20 Sourcing Output Current 98 19 Sinking Output Current 94 18 90 125 17 –50 –25 Ambient Temperature (°C) 0 25 50 75 100 125 Ambient Temperature (°C) COMMON-MODE INPUT RANGE AND OUTPUT SWING vs SUPPLY VOLTAGE COMMON-MODE AND DIFFERENTIAL INPUT IMPEDANCE 107 6 Impedance Magnitude (20log (Ω)) Positive Input 4 Voltage Range (V) 21 Supply Current 102 –25 0 5 110 Input Bias and Offset Current (µA) Input Offset Voltage (mV) 0.5 –25 4 SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 25 –50 3 Video Loads (150Ω each) 1 2 Positive Output 0 –2 Negative Output –4 Negative Input Common-Mode 106 105 Differential 104 103 102 –6 3 4 5 103 6 104 105 106 107 108 Frequency (Hz) Supply Voltage (±V) 8 dG, Negative Video OPA843 www.ti.com SBOS268A Supply Current (1mA/div) Percent of Final Value (%) 0.02 RL = 100Ω VO = 2V step G = +5 Differential Phase (°) 0.25 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = +25°C, GD = 10, RF = 1kΩ, RG = 100Ω, and RL = 100Ω, unless otherwise noted. DIFFERENTIAL PERFORMANCE TEST CIRCUIT DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE 3 VO = 400mVp-p +5V GD = 5 0 OPA843 RG 100Ω VI RG 100Ω Normalized Gain (dB) RF GD = 100Ω –5V RF RL RF VO +5V GD = 10 –3 GD = 16 –6 GD = 32 –9 –12 –15 OPA843 –18 1 10 DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE VO = 400mVp-p to 5Vp-p 17 VO = 8Vp-p 14 11 VO = 4Vp-p GD = 10 F = 5MHz –75 Harmonic Distortion (dBc) 20 Gain (dB) 1k DIFFERENTIAL DISTORTION vs LOAD RESISTANCE –70 23 GD = 10V/V 100 Frequency (MHz) –5V –80 –85 2nd-Harmonic –90 –95 –100 3rd-Harmonic –105 –110 8 10 100 10 200 100 DIFFERENTIAL DISTORTION vs FREQUENCY DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE –60 GD = 10 RL = 400Ω F = 5MHz –85 Harmonic Distortion (dBc) Gain (dB) –80 VO = 4Vp-p GD = 10 RL = 400Ω –70 1k Load Resistance (Ω) Frequency (MHz) –80 2nd-Harmonic –90 –100 –90 –95 2nd-Harmonic –100 3rd-Harmonic –105 –110 3rd-Harmonic –110 –115 1 10 20 1 Frequency (Hz) OPA843 SBOS268A 10 Output Voltage Swing (Vp-p) www.ti.com 9 APPLICATIONS INFORMATION +5V WIDEBAND NONINVERTING OPERATION The OPA843’s combination of speed and dynamic range is useful in a wide variety of application circuits, as long as simple guidelines common to all high-speed amplifiers are observed. For example, good power-supply decoupling, as shown in Figure 1, is essential to achieve the lowest possible harmonic distortion and smooth frequency response. Careful PC board layout and component selection will maximize the performance of the OPA843 in all applications, as discussed in the following sections of this data sheet. Figure 1 shows the gain of +5 configuration used as the basis for most of the typical characteristics. Most of the curves were characterized using signal sources with 50Ω driving impedance and with measurement equipment presenting 50Ω load impedance. In Figure 1, the 50Ω shunt resistor at the input terminal matches the source impedance of the test generator, while the 50Ω series resistor at the VO terminal provides a matching resistor for the measurement equipment load. Generally, data sheet specifications refer to the voltage swing at the output pin (VO in Figure 1) while those referring to load power are at the 50Ω load. The total 100Ω load from the series and shunt matching resistors, combined with the 502Ω total feedback network load, presents the OPA843 with an effective output load of approximately 83Ω. +5V +VS 0.1µF + 2.2µF 50Ω Source VIN 50Ω RS 50Ω Load 50Ω VO OPA843 RF 402Ω RG 100Ω 0.1µF + 2.2µF –VS –5V FIGURE 1. Gain of +5, High-Frequency Application and Characterization Circuit. 0.1µF RT 50Ω Source + RS 50Ω Load 50Ω VO OPA843 2.2µF RF 402Ω RG 50Ω VI RM (optional) 0.1µF + 2.2µF –5V FIGURE 2. Inverting G = –8 Specification and Test Circuit. both the input termination resistor and the gain setting resistor for the circuit. Although the signal gain for the circuit of Figure 2 is equal to –8V/V (versus the +5V/V for Figure 1), their noise gains are equal when the 50Ω source resistor is included. This has the interesting effect of nearly doubling the equivalent Gain Bandwidth Product (GBP) for the amplifier. This can be seen in comparing the G = +5 and G = –8 small-signal frequency response curves. Both show approximately 260MHz bandwidth, but the inverting configuration of Figure 2 is giving 4dB higher signal gain. If the signal source is actually the low impedance output of another amplifier, RG is increased to the minimum value allowed at the output of that amplifier and RF is adjusted to get the desired gain. It is critical for stable operation of the OPA843 that this driving amplifier show a very low output impedance through frequencies exceeding the expected closed-loop bandwidth for the OPA843. An optional input termination resistor is also shown in Figure 2. This RM resistor may be used to adjust the input impedance to lower values when RG needs to be adjusted higher. This might be desirable at lower gains where increasing RF will reduce the output loading improving harmonic distortion performance. For instance, at a gain of –4 an RG set to 50Ω will require a 200Ω feedback resistor. In this case, adjusting RF to 400Ω, setting RG to 100Ω, and then adding a 100Ω RM resistor will deliver a gain of –4 with a 50Ω input match. BUFFERING HIGH-PERFORMANCE ADCs WIDEBAND, INVERTING GAIN OPERATION There can be significant benefits to operating the OPA843 as an inverting amplifier. This is particularly true when a matched input impedance is required. Figure 2 shows the inverting gain circuit used as a starting point for the typical characteristics showing inverting mode performance. Driving this circuit from a 50Ω source, and constraining the gain resistor, RG, to equal 50Ω will give both a signal bandwidth and noise advantage. RG in this case is acting as 10 A single-channel interface using the OPA843 can provide a low noise/distortion interface to emerging 14-bit Analog-to-Digital Converters (ADCs) through approximately 5MHz for medium gain applications. Since the dominant distortion mechanism is 2nd-harmonic distortion, differential circuits using the OPA843 can extend this frequency range and/or power level to much higher levels. The example on the front page of this data sheet, for instance, shows better than 93dB SFDR at 5MHz for up to 8Vp-p signals. This is still being limited by the 2nd-harmonic with OPA843 www.ti.com SBOS268A the 3rd-harmonic much lower. 2-tone 3rd-order intermodulation terms will be much lower than most other solutions using the circuit shown on the front page. The differential typical characteristic curves also show that a 4Vp-p output will have > 80dBc SFDR through 20MHz using this differential approach. 1dB through 50MHz. For narrowband IF’s in the 44MHz region, this configuration of the OPA843 will show a 3rd-order intercept of 33dBm while dissipating only 200mW (23dBm) power from ±5V supplies. PHOTODIODE TRANSIMPEDANCE AMPLIFIER WIDE DYNAMIC RANGE “IF” AMPLIFIER The OPA843 offers an attractive alternative to standard fixedgain IF amplifier stages. Narrowband systems will benefit from the exceptionally high 2-tone 3rd-order intermodulation intercept, as shown in the Typical Characteristics. Op amps with high open-loop gain, like the OPA843, provide an intercept that decreases with frequency along with the loop gain. The OPA843’s 3rd-order intercept shows a decreasing intercept with frequency. The OPA843’s intercept is > 30dBm up to 50MHz but improves to > 50dBm as the operating frequency is reduced below 10MHz. Broadband systems will also benefit from the very low even-order harmonics and intermodulation components produced by the OPA843. Compared to standard fixed-gain IF amplifiers, the OPA843 operating at IF’s below 50MHz provides much higher intercepts for its quiescent power dissipation (200mW), superior gain accuracy, higher reverse isolation, and lower I/O return loss. The noise figure for the OPA843 will be higher than alternative fixed-gain stages. If the application comes late in the amplifier chain with significant gain in prior stages, this higher noise figure may be acceptable. Figure 3 shows an example of a noninverting configuration for the OPA843 used as an IF amplifier. High Gain Bandwidth Product (GBP) and low input voltage and current noise make the OPA843 an ideal wideband transimpedance amplifier for low to moderate gains. Note that unity-gain stability is not required for transimpedance applications. Figure 4 shows an example photodiode amplifier circuit. The key parameters of this design are the estimated diode capacitance (CD) at the applied DC reverse bias voltage (–VB), the desired transimpedance gain (RF), and the GBP for the OPA843 (800MHz). With these three variables set (and adding the OPA843’s parasitic input capacitance to the value of CD to get CS), the feedback capacitor value (CF) is selected to provide stability for the transimpedance frequency response. +5V Power-supply decoupling not shown. 0.01µF 10kΩ –5V λ +5V 50Ω Source ID Power-supply decoupling not shown. VO = IDRF OPA843 RF 10kΩ CF 0.75pF CD 20pF 0.01µF PI VO 52.3Ω 1kΩ OPA843 +5V RS 50Ω Load 50Ω P0 –VB FIGURE 3. High Dynamic Range IF Amplifier. To achieve a maximally flat 2nd-order Butterworth frequency response, the feedback pole should be set to: RF 1kΩ 1 = 2πRF CF RG 144Ω GBP 4 πRF CS CS = CD + CI (1) 0.01µF 1 PI RF Gain = P = 20log 2 1 + R dB = 12dB with values shown O G FIGURE 3. High Dynamic Range IF Amplifier. The input signal and the gain resistor are AC coupled through the 0.01µF blocking capacitors. This holds the DC input and output operating point at ground independent of source impedance and gain setting. The RG value in Figure 3 (144Ω), sets the gain to the matched load at 12dB. Using standard 1% tolerance resistors for RF and RG will hold the gain to a ±0.2dB tolerance. This example will give a –3dB bandwidth of approximately 100MHz while maintaining gain flatness within Adding the OPA843’s common-mode and differential mode input capacitances CI = (1.0 + 1.2)pF to the 20pF diode source capacitance of Figure 4, and targeting a 10kΩ transimpedance gain using the 800MHz GBP for the OPA843, the required feedback pole frequency is 16.9MHz. This will require a total feedback capacitance of 0.94pF. Typical surface-mount resistors have a parasitic capacitance of 0.2pF, leaving the required 0.75pF value shown in Figure 4 to get the required feedback pole. This will set the –3dB bandwidth according to: F −3dB ≅ (2) The example of Figure 4 will give approximately 24MHz –3dB bandwidth using the 0.75pF feedback compensation. OPA843 SBOS268A GBP Hz 2πRF CS www.ti.com 11 WIDEBAND INVERTING SUMMING AMPLIFIER 100pF One common application for a wideband op amp like the OPA843 is to sum a number of signal sources together. Figure 5 shows the inverting summing configuration that is most often used. This circuit offers the benefit that each input sees an input impedance set only by its individual input resistor, since the summing junction (inverting op amp node) is a virtual ground. Each input is non-interactive with every other. However, the bandwidth from any input to the summed output is set by the op amp noise gain (NG), which is equal to the noninverting voltage gain. Therefore, each inverting channel may have a low gain to the output (like the –1 shown in Figure 5); this noise gain will set the frequency response and the loop stability. The noninverting gain for Figure 5 is equal to +5, which will give a 260MHz bandwidth at a gain of –1 for each of the input signals. 0Ω Source VI 61Ω 150Ω VO 220pF OPA843 402Ω 100Ω FIGURE 6. 10MHz Butterworth Low-Pass Filter. 10MHz Low-Pass Filter 15 12 +5V 9 Power-supply decoupling not shown. 0.1µF OPA843 VO = –(V1 + V2 + V3 + V4) Gain (dB) 6 81.8Ω –5V 402Ω 3 0 –3 –6 RF 402Ω –9 –12 V1 –15 100k 402Ω V2 1M 10M 100M Frequency (MHz) 402Ω V3 FIGURE 7. Frequency Response for Figure 6. 402Ω V4 FIGURE 5. Wideband Inverting Summing Amplifier. 2nd-Order Filter Topology High-speed amplifiers like the OPA843 are good choices for 2nd-order filter building blocks as part of ADC driver channels. These can provide noise bandlimiting to improve the SNR for the amplifier/converter combination. The circuit of Figure 6 shows an example of a 10MHz Butterworth lowpass filter where the amplifier provides a low frequency gain of 5 and a 2nd-order cutoff at 10MHz. The resistor values have been adjusted slightly to account for the amplifier bandwidth. Figure 7 shows the small-signal frequency response for this filter. EQUALIZING FILTER APPLICATION In sensor receiver applications, where the pickup is a sensor or cable giving a bandlimited frequency response, an equalizing filter can sometimes be used to extend the useable frequency range for the sensor. This is done mathematically by taking the inverse of the rolloff transfer function and implementing that as the amplifier frequency response. See Figure 8 for one example of a wideband equalizer where two stages of the OPA843 are used. This example is set to 12 transition from a unity gain receiver at lower frequencies (through the R5 path) to a gain of 20dB (10V/V) through the R1 path at higher frequencies. The component values have been selected to set the peak gain at approximately 30MHz. A unique feature for this circuit is an independent tune on the width of the peaking (Q of the response) by adjusting RG. See Figure 9 for the effect of adjusting RG over the range of 20Ω to 100Ω. DESIGN-IN TOOLS DEMONSTRATION BOARDS Two PC boards are available to assist in the initial evaluation of circuit performance using the OPA843 in its two package styles. Both of these are available, free, as an unpopulated PC board delivered with descriptive documentation. The summary information for these boards is shown in the table below. PRODUCT PACKAGE BOARD PART NUMBER OPA843U OPA843N SO-8 SOT23-5 DEM-OPA68xU DEM-OPA6xx LITERATURE REQUEST NUMBER SBOU010 SBOU009 Contact your sales representative or go to the TI web site (www.ti.com) to request evaluation boards. OPA843 www.ti.com SBOS268A +5V +5V VCC VCC OPA843 OPA843 Power-supply decoupling not shown. VEE VEE –5V R4 600Ω C2 41.125pF –5V RF 1.2kΩ R1 120Ω VOUT RLOAD 1kΩ R2 1.2kΩ VIN C1 5.2pF RG R5 1.2kΩ FIGURE 8. Adjustable Equalizer. value should be between 200Ω and 1kΩ. Below 200Ω, the feedback network will present additional output loading that can degrade the harmonic distortion performance of the OPA843. Above 1kΩ, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor may cause unintentional band limiting in the amplifier response. 40 (dB) 20 0 –20 –40 100kHz 1MHz 10MHz 100MHz 1GHz Frequency FIGURE 9. Equalizer Plot, Multiple Settings. MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often a quick way to analyze the performance of the OPA843 and its circuit designs. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can play a major role on circuit performance. A SPICE model for the OPA843 is available through the TI web page (http://www.ti.com). The applications department is also available for design assistance. These models predict typical small-signal AC, transient steps, DC performance, and noise under a wide variety of operating conditions. The models include the noise terms found in the electrical specifications of this data sheet. These models do not attempt to distinguish between the package types in their small-signal AC performance. OPERATING SUGGESTIONS A good rule of thumb is to target the parallel combination of RF and RG (see Figure 1) to be less than about 200Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the feedback network, and thus a zero in the forward response. Assuming a 2pF total parasitic on the inverting node, holding RF || RG < 200Ω will keep this pole above 400MHz. By itself, this constraint implies that the feedback resistor RF can increase to several kΩ at high gains. This is acceptable as long as the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest. In the inverting configuration, an additional design consideration must be noted. RG becomes the input resistor and, therefore, the load impedance to the driving source. If impedance matching is desired, RG may be set equal to the required termination value. However, at low inverting gains the resultant feedback resistor value can present a significant load to the amplifier output. For example, an inverting gain of –4 with a 50Ω input matching resistor (= RG) would require a 200Ω feedback resistor, which would contribute to output loading in parallel with the external load. In such a case, it would be preferable to increase both the RF and RG values, and then achieve the input matching impedance with a third resistor to ground, see Figure 2. The total input impedance becomes the parallel combination of RG and the additional shunt resistor. BANDWIDTH vs GAIN OPTIMIZING RESISTOR VALUES Since the OPA843 is a voltage-feedback op amp, a wide range of resistor values may be used for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. Usually, the feedback resistor Voltage-feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the GBP shown in the electrical characteristics. Ideally, dividing GBP by the noninverting signal gain (also called the Noise Gain, or NG) will predict the closed-loop bandwidth. In practice, this only holds true when OPA843 SBOS268A www.ti.com 13 the phase margin approaches 90°, as it does in high-gain configurations. At low signal gains, most amplifiers will exhibit a more complex response with lower phase margin. The OPA843 is optimized to give a maximally flat 2nd-order Butterworth response in a gain of 5. In this configuration, the OPA843 has approximately 60° of phase margin and will show a typical –3dB bandwidth of 260MHz. When the phase margin is 60°, the closed-loop bandwidth is approximately √2 greater than the value predicted by dividing GBP by the noise gain. Increasing the gain will cause the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +20, the 40MHz bandwidth shown in the Electrical Characteristics agrees with that predicted using the simple formula and the typical GBP of 800MHz. LOW GAIN OPERATION Decreasing the operating gain for the OPA843 from the nominal design point of +5 will decrease the phase margin. This will increase the Q for the closed-loop poles, peak up the frequency response, and extend the bandwidth. A peaked frequency response will show overshoot and ringing in the pulse response as well as a higher integrated output noise. Operating at a noise gain less than +3 runs the risk of sustained oscillation (loop instability). However, operation at low gains would be desirable to take advantage of the much higher slew rate and lower input noise voltage available in the OPA843, as compared to the performance offered by unity-gain stable op amps. Numerous external compensation techniques have been suggested for operating a high-gain op amp at low gains. Most of these give zero/pole pairs in the closed-loop response that cause long term settling tails in the pulse response and/or phase nonlinearity in the frequency response. Figure 10 shows an external compensation method for a noninverting configuration that does not suffer from these drawbacks. tune the flatness by adjusting RI. The Typical Characteristics show a signal gain of +4 with the noise gain adjusted for flatness using different values for R1. Where low gain is desired, and inverting operation is acceptable, a new external compensation technique may be used to retain the full slew rate and noise benefits of the OPA843 while maintaining the increased loop gain and the associated improvement in distortion offered by the decompensated architecture. This technique shapes the noise gain for good stability while giving an easily controlled 2nd-order low-pass frequency response. Figure 11 shows this circuit. Considering only the noise gain for the circuit of Figure 11, the low-frequency noise gain (NG1) will be set by the resistor ratios while the highfrequency noise gain (NG2) will be set by the capacitor ratios. The capacitor values set both the transition frequencies and the high-frequency noise gain. If this noise gain, determined by NG2 = 1 + CS/CF, is set to a value greater than the recommended minimum stable gain for the op amp and the noise gain pole (set by 1/RFCF) is placed correctly, a very well controlled 2nd-order low-pass frequency response will result. +5V Power-supply decoupling not shown. 280Ω 0.1µF OPA843 VO –5V RF 806Ω 402Ω V1 RS = 0Ω CS 12.6pF CF 1.9pF FIGURE 10. Noninverting Low Gain Circuit. To choose the values for both CS and CF, two parameters and only three equations need to be solved. The first parameter is the target high-frequency noise gain, NG2, which should be greater than the minimum stable gain for the OPA843. Here, a target NG2 of 7.5 will be used. The second parameter is the desired low-frequency signal gain, which also sets the low-frequency noise gain, NG1. To simplify this discussion, we will target a maximally flat 2nd-order low-pass Butterworth frequency response (Q = 0.707). The signal gain of –2 shown in Figure 11 will set the low-frequency noise gain to NG1 = 1 + RF/RG (= 3 in this example). Then, using only these two gains and the GBP for the OPA843 (800MHz), the key frequency in the compensation is determined by: +5V 50Ω Source VI RT 50Ω R1 133Ω VO RS 50Ω OPA843 50Ω Load +5V RF 402Ω RG 402Ω FIGURE 10. Noninverting Low Gain Circuit. The R1 resistor across the two inputs will increase the noise gain (i.e., decrease the loop gain) without changing the signal gain. This approach will retain the full slew rate to the output but will give up some of the low-noise benefit of the OPA843. Assuming a low source impedance, set R1 so that 1 + RF/(RG || RI) is ≥ +3. This approach may also be used to 14 Z0 = GBP NG1 NG1 1− − 1− 2 2 NG NG 2 2 NG 1 (11) Physically, this Z0 (13.6MHz for the values shown in Figure 11) is set by 1/(2π • RF (CF + CS)) and is the frequency at which the rising portion of the noise gain would intersect unity gain if projected back to 0dB gain. The actual zero in the noise gain OPA843 www.ti.com SBOS268A occurs at NG1 • Z0 and the pole in the noise gain occurs at NG2 • Z0. Since GBP is expressed in Hz, multiply Z0 by 2π and use this to get CF by solving: CF = 1 2πRF Z0 NG2 (12) Finally, since CS and CF set the high-frequency noise gain, determine CS by: CS = (NG2 – 1)CF (13) The resulting closed-loop bandwidth will be approximately equal to: F −3dB ≅ Z0 GBP (14) For the values shown in Figure 10, the F–3dB will be approximately 105MHz. This is less than that predicted by simply dividing the GBP product by NG1. The compensation network controls the bandwidth to a lower value while providing full slew rate and exceptional distortion performance due to increased loop gain at frequencies below NG1 • Z0. The capacitor values shown in Figure 10 are calculated for NG1 = 3 and NG2 = 7.5 with no adjustment for parasitics. OUTPUT DRIVE CAPABILITY The OPA843 has been optimized to drive the demanding load of a doubly-terminated transmission line. When a 50Ω line is driven, a series 50Ω into the cable and a terminating 50Ω load at the end of the cable are used. Under these conditions, the impedance of the cable appears resistive over a wide frequency range and the total effective load on the OPA843 is 100Ω in parallel with the resistance of the feedback network. The Electrical Characteristics show a 6.1Vp-p swing into a 100Ω load—which is then reduced to a 3Vp-p swing at the termination resistor. The ±85mA output drive over temperature provides adequate current drive margin for this load. A common IF amplifier specification, which describes available output power is the –1dB compression point. This is usually defined at a matched 50Ω load to be the sinusoidal power where the gain has compressed by –1dB vs the gain seen at very low power levels. This compression level is frequency dependent for an op amp, due to both bandwidth and slew rate limitations. For frequencies well within the bandwidth and slew rate limit of the OPA843, the –1dB compression at a matched 50Ω load will be > 13dBm based on the minimum available 3Vp-p swing at the load. One common use for the –1dB compression is to predict intermodulation intercept. This is normally 10dB greater than the –1dB compression power for a standard RF amplifier. This simple rule of thumb does NOT apply to the OPA843. The high open-loop gain and Class AB output stage of the OPA843 produce a much higher intercept than the –1dB compression would predict, as shown in the Typical Characteristics. DRIVING CAPACITIVE LOADS One of the most demanding, and yet very common, load conditions for an op amp is capacitive loading. A high-speed, high open-loop gain amplifier like the OPA843 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. In simple terms, the capacitive load reacts with the open-loop output resistance of the amplifier to introduce an additional pole into the loop and thereby decrease the phase margin. This issue has become a popular topic of application notes and articles, and several external solutions to this problem have been suggested. When the primary considerations are frequency-response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended “RS vs Capacitive Load” and the resulting frequency response at the load. The criterion for setting the recommended resistor is maximum bandwidth and flat frequency response at the load. Since there is now a passive low-pass filter between the output pin and the load capacitance, the response at the output pin itself is typically somewhat peaked, and becomes flat after the roll off action of the RC network. This is not a concern in most applications, but can cause clipping if the desired signal swing at the load is very close to the amplifier’s swing limit. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA843. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully and add the recommended series resistor as close as possible to the OPA843 output pin (see Board Layout section). DISTORTION PERFORMANCE The OPA843 is capable of delivering an exceptionally low distortion signal at high frequencies and medium gains. The distortion plots in the Typical Characteristics show the typical distortion under a wide variety of conditions. Most of these plots are limited to 100dB dynamic range. The OPA843’s distortion does not rise above –100dBc until either the signal level exceeds 0.5Vp-p and/or the fundamental frequency exceeds 500kHz. Distortion in the audio band is < –120dBc. Generally, until the fundamental signal reaches very high frequencies or powers, the 2nd-harmonic will dominate the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network—in the noninverting configuration this is the sum of RF + RG, whereas in the inverting configuration this is just RF (see Figure 1). Increasing output voltage swing increases harmonic distortion directly. A 6dB increase in output swing will generally increase OPA843 SBOS268A www.ti.com 15 the 2nd-harmonic 12dB and the 3rd-harmonic 18dB. Increasing the signal gain will also increase the 2nd-harmonic distortion. Again, a 6dB increase in gain will increase the 2nd- and 3rd-harmonic by 6dB even with a constant output power and frequency. Finally, the distortion increases as the fundamental frequency increases due to the roll off in the loop gain with frequency. Conversely, the distortion will improve going to lower frequencies down to the dominant open-loop pole at approximately 3kHz. Starting from the –100dBc 2nd-harmonic for 2Vp-p into 200Ω, G = +5 distortion at 500kHz (from the Typical Characteristics), the 2ndharmonic distortion at 20kHz should be approximately: shows the general form for this output noise voltage using the terms presented in Figure 12. EO = (E 2 NI ENI √4kTRS 4kT RG 16 RF RG IBI √4kTRF 4kT = 1.6E – 20J at 290°K FIGURE 12. Op Amp Noise Analysis Model. Dividing this expression by the noise gain (NG = 1 + RF/RG) will give the equivalent input referred spot noise voltage at the noninverting input, as shown in Equation 16. 2 4kTRF I R 2 EN = ENI + (IBN RS )2 + 4kTRS + BI F + NG NG (16) Evaluating these two equations for the OPA843 circuit presented in Figure 1 will give a total output spot noise voltage of 12.4nV/√Hz and an equivalent input spot noise voltage of 2.48nV/√Hz. DC OFFSET CONTROL The OPA843 can provide excellent DC signal accuracy due to its high open-loop gain, high common-mode rejection, high power supply rejection, and low input offset voltage and bias current offset errors. To take full advantage of this low input offset voltage, careful attention to input bias current cancellation is also required. The high-speed input stage for the OPA843 has a relatively high input bias current (20µA typical into the pins) but with a very close match between the two input currents—typically 0.17µA input offset current. Figures 13 and 14 show typical distribution of input offset voltage and current for the OPA843. 1000 NOISE PERFORMANCE 800 Mean = 0.38mV Standard Deviation = 0.31mV Total Count = 5572 Count 700 600 500 400 300 200 100 0 < –1.20 < –1.08 < –0.96 < –0.84 < –0.72 < –0.60 < –0.48 < –0.36 < –0.24 < –0.12 < –0.00 <0.12 <0.24 <0.36 <0.48 <0.60 <0.72 <0.84 <0.96 <1.08 <1.20 >1.20 The total output spot noise voltage is computed as the square root of the squared contributing terms to the output noise voltage. This computation is adding all the contributing noise powers at the output by superposition, and then taking the square root to get back to a spot noise voltage. Equation 15 IBN ERS 900 The OPA843 complements its ultra low harmonic distortion with low input noise terms. Both the input-referred voltage noise, and the two input-referred current noise terms combine to give a low output noise under a wide variety of operating conditions. Figure 12 shows the op amp noise analysis model with all the noise terms included. In this model, all the noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. EO OPA843 RS –100dB – 20log (500kHz/20kHz) = –128dBc. The OPA843 has an extremely low 3rd-order harmonic distortion. This also gives an exceptionally good 2-tone, 3rd-order intermodulation intercept, as shown in the Typical Characteristics. This intercept curve is defined at the 50Ω load when driven through a 50Ω-matching resistor to allow direct comparisons to RF MMIC devices. This network attenuates the voltage swing from the output pin to the load by 6dB. If the OPA843 drives directly into the input of a high-impedance device, such as an ADC, this 6dB attenuation is not taken. Under these conditions, the intercept will increase by a minimum of 6dBm. The intercept is used to predict the intermodulation spurious for two closely spaced frequencies. If the two test frequencies, f1 and f2, are specified in terms of average and delta frequency, fO = (f1 + f2)/2 and µf = |f2 – f1|/2, the two, 3rd-order, close-in spurious tones will appear at fO ± (3 • ∆f). The difference between two equal test-tone power levels and these intermodulation spurious power levels is given by 2 • (IM3 – PO) where IM3 is the intercept taken from the typical characteristic curve and PO is the power level in dBm at the 50Ω load for one of the two closely spaced test frequencies. For instance, at 10MHz the OPA843 at a gain of +5 has an intercept of 49dBm at a matched 50Ω load. If the full envelope of the two frequencies needs to be 2Vp-p, this requires each tone to be 4dBm. The 3rd-order intermodulation spurious tones will then be 2 • (49 – 4) = 90dBc below the test-tone power level (–86dBm). If this same 2Vp-p 2tone envelope were delivered directly into the input of an ADC without the matching loss or loading of the 50Ω network, the intercept would increase to at least 55dBm. With the same signal and gain conditions now driving directly into a light load, the spurious tones will then be at least 2 • (55 – 4) = 102dBc below the 1Vp-p test-tone signal levels. ) + (IBN RS )2 + 4kTRS NG2 + (IBI RF )2 + 4kTRF NG (15) mV FIGURE 13. Input Offset Voltage Distributing in mV. OPA843 www.ti.com SBOS268A 1600 1400 +5V VCC Mean = 0.04µA Standard Deviation = 0.17µA Total Count = 5572 Power-supply decoupling not shown. 1200 Count 200Ω 0.1µF 1000 OPA843 800 VEE –5V 600 +5V RG 250Ω 400 RF 1kΩ VIN 200 5kΩ 0 < –1.00 < –0.90 < –0.80 < –0.70 < –0.60 < –0.50 < –0.40 < –0.30 < –0.20 < –0.10 < –0.00 <0.10 <0.20 <0.30 <0.40 <0.50 <0.60 <0.70 <0.80 <1.90 <1.00 >1.00 20kΩ ±125mV Output Adjustment 10kΩ 0.1µF mV 5kΩ FIGURE 14. VO VIN =– RF RG = –4 –5V The total output offset voltage may be considerably reduced by matching the source impedances looking out of the two inputs. For example, one way to add bias current cancellation to the circuit of Figure 1 would be to insert a 55Ω series resistor into the noninverting input from the 50Ω terminating resistor. When the 50Ω source resistor is DC coupled, this will increase the source impedance for the noninverting input bias current to 80Ω. Since this is now equal to the impedance looking out of the inverting input (RF || RG), the circuit will cancel the gains for the bias currents to the output leaving only the offset current times the feedback resistor as a residual DC error term at the output. Using a 402Ω feedback resistor, this output error will now be less than 1µA • 402Ω = 0.4mV at 25°C. A fine-scale output offset null, or DC operating point adjustment, is sometimes required. Numerous techniques are available for introducing a DC offset control into an op amp circuit. Most of these techniques eventually reduce to setting up a DC current through the feedback resistor. One key consideration to selecting a technique is to insure that it has a minimal impact on the desired signal path frequency response. If the signal path is intended to be noninverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path uses the inverting mode, applying an offset control to the noninverting input can be considered. For a DC-coupled inverting input signal, this DC offset signal will set up a DC current back into the source that must be considered. An offset adjustment placed on the inverting op amp input can also change the noise gain and frequency response flatness. Figure 15 shows one example of an offset adjustment for a DC-coupled signal path that will have minimum impact on the signal frequency response. In this case, the input is brought into an inverting gain resistor with the DC adjustment an additional current summed into the inverting node. The FIGURE 15. DC Coupled, Inverting Gain of –4 with Output Offset Adjustment. resistor values for setting this offset adjustment are chosen to be much larger than the signal path resistors. This will insure that this adjustment has minimal impact on the loop gain and hence, the frequency response. THERMAL ANALYSIS The OPA843 will not require heat sinking or airflow in most applications. Maximum desired junction temperature would set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed +150°C. Operating junction temperature (TJ ) is given by TA + PD • θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this worst-case condition, PDL = VS2/(4 • RL), where RL includes feedback network loading. Note that it is the power in the output stage and not in the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA843IDBV (SOT23-5 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C. PD = 10V(22.5mA) + 52/(4 • (100Ω || 500Ω)) = 300mW. Maximum TJ = +85°C + (0.30W • 150°C/W) = 130°C. OPA843 SBOS268A VO www.ti.com 17 BOARD LAYOUT Achieving optimum performance with a high-frequency amplifier such as the OPA843 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high-frequency performance of the OPA843. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wire-wound type resistors in a highfrequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Where double-feedback side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values 18 > 1.5kΩ, this parasitic capacitance can add a pole and/or a zero below 500MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load driving considerations. d) Connections to other wideband devices on the board may be made with short, direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of recommended “RS vs Capacitive Load.” Low parasitic capacitive loads (< 5pF) may not need an RS since the OPA843 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched-impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact a higher impedance environment will improve distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA843 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and input impedance of the destination device; this total effective impedance should be set to match the trace impedance. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be seriesterminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of “RS vs Capacitive Load.” This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA843 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA843 onto the board. OPA843 www.ti.com SBOS268A INPUT AND ESD PROTECTION The OPA843 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 16. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g., in systems with ±15V supply parts driving into the OPA843), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. Figure 17 shows one example of an overdrive protection circuit added to a G = +5V/V design. 50Ω Source +VCC +5V 125Ω Power-supply decoupling not shown. 50Ω External Pin Internal Cicuitry 50Ω D1 D2 50Ω –VCC RG 126Ω FIGURE 16. Internal ESD Protection. –5V VO RF 505Ω D1 = D2 IN5911 (or equivalent) FIGURE 17. Gain of +5 with Input Protection. OPA843 SBOS268A OPA843 www.ti.com 19 PACKAGE DRAWINGS D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. B. C. D. 20 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 OPA843 www.ti.com SBOS268A PACKAGE DRAWINGS (Cont.) DBV (R-PDSO-G5) PLASTIC SMALL-OUTLINE 0,50 0,30 0,95 5 0,20 M 4 1,70 1,50 1 0,15 NOM 3,00 2,60 3 Gage Plane 3,00 2,80 0,25 0° – 8° 0,55 0,35 Seating Plane 1,45 0,95 0,05 MIN 0,10 4073253-4/G 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-178 OPA843 SBOS268A www.ti.com 21 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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