PCM ® PCM1718E ® 171 8 Stereo Audio DIGITAL-TO-ANALOG CONVERTER TM FEATURES DESCRIPTION ● ACCEPTS 16- or 18-BIT I2S, OR 18-BIT NORMAL INPUT DATA The PCM1718 is a complete low cost stereo, audio digital-to-analog converter, including digital interpolation filter, 3rd-order delta-sigma DAC, and analog output amplifiers. PCM1718 is fabricated on a highly advanced 0.6µ CMOS process. PCM1718 accepts 18bit normal input data format, or 16- or 18-bit I2S data format. ● COMPLETE STEREO DAC: 8X Oversampling Digital Filter Multi-Level Delta-Sigma DAC Analog Low Pass Filter Output Amplifier The digital filter performs an 8X interpolation function, as well as special functions such as soft mute and digital de-emphasis. ● HIGH PERFORMANCE: –90dB THD+N 96dB Dynamic Range 100dB SNR PCM1718 is suitable for a wide variety of cost-sensitive consumer applications where good performance is required. Its low cost, small size, and single power supply make it ideal for BS tuners, keyboards, MPEG audio, PCMCIA audio cards (ZV port), MIDI applications, and set-top boxes. ● SYSTEM CLOCK: 256fs or 384fs ● WIDE POWER SUPPLY: +2.7V to +5.5V ● SELECTABLE FUNCTIONS: Soft Mute Digital De-emphasis ● SMALL 20-PIN SSOP PACKAGE BCKIN LRCIN DIN MUTE DM0 DM1 Serial Input I/F 8X Oversampling Digital Filter with Multi Function Control Mode Control I/F Multi-level Delta-Sigma Modulator DAC Multi-level Delta-Sigma Modulator DAC Output Amp and Low-pass Filter Output Amp and Low-pass Filter VOUTL D/C_L VOUTR D/C_R ZERO FORMAT Open Drain RSTB Reset Clock/OSC Manager XTI XTO CLKO Power Supply VCC AGND VDD DGND InternationalAirportIndustrialPark • MailingAddress:POBox11400,Tucson,AZ85734 • StreetAddress:6730S.TucsonBlvd.,Tucson,AZ 85706 • Tel:(520)746-1111 • Twx:910-952-1111 Internet:http://www.burr-brown.com/ • FAXLine:(800)548-6133(US/CanadaOnly) • Cable:BBRCORP • Telex:066-6491 • FAX:(520)889-1510 • ImmediateProductInfo:(800)548-6132 ® © 1996 Burr-Brown Corporation PDS-1325A 1 PCM1718E Printed in U.S.A. June, 1996 SPECIFICATIONS All specifications at +25°C, +VCC = +VDD = +5V, fs = 44.1kHz, and 18-bit input data, SYSCLK = 384fs, unless otherwise noted. Measurement bandwidth is 20kHz. PCM1718E PARAMETER CONDITIONS MIN RESOLUTION TYP 16 DIGITAL INPUT/OUTPUT Logic Family Input Logic Level: VIH(2) VIL(2) VIH(3) VIL(3) VIH(4) VIL(4) Input Logic Current: IIH(5) IIL(5) IIH(6) IIL(6) IIH(4) IIL(4) Output Logic Level: (+VDD = +5V) VOH(7) VOL(7) VOL(8) Interface Format Data Format Sampling Frequency System Clock Frequency DC ACCURACY Gain Error Gain Mismatch Channel-to-Channel Bipolar Zero Error –6.0 –120 –2 0.02 40 –40 µA µA µA µA µA µA 1.0 1.0 V V V 70% of VDD 30% of VDD 64% of VDD VIN = 3.2V VIN = 1.4V IOH = –5mA IOL = +5mA IOL = +5mA 3.8 256fs/384fs Selectable Normal, I2S 16/18 Bits MSB First Binary Two’s Complement 32 44.1 48 8.192/12.288 11.2896/16.9344 12.288/18.432 kHz MHz ±5.0 ±5.0 VO = 1/2 VCC at Bipolar Zero ±1.0 ±1.0 ±30 % of FSR % of FSR mV –90 –34 96 100 97 ±0.5 –80 dB dB dB dB dB dB VCC = +3V, f = 991Hz EIAJ, A-weighted EIAJ, A-weighted 90 92 90 –86 91 94 EIAJ, A-weighted EIAJ, A-weighted dB dB dB ±0.17 –35 0.445 (fs = 32kHz ~ 48kHz) 0.555 –0.2 +0.55 11.125/fs FS (0dB) OUT 62% of VCC 50% of VCC +VCC +VCC +VCC +VCC +VCC +VDD = +VDD = +VDD = +VDD = +VDD +2.7 +2.7 = = = = +5V +3V +5V +3V TEMPERATURE RANGE Operation Storage 18.0 9.0 90 27 –25 –55 dB dB fs fs dB sec Vp-p kΩ V 5 POWER SUPPLY REQUIREMENTS Voltage Range: Power Dissipation 28% of VDD V V V V V V 30% of VDD DYNAMIC PERFORMANCE(1) THD+N at FS (0dB) Dynamic Range Signal-To-Noise Ratio Supply Current: +ICC +IDD(9) Bits 70% of VDD VCC = +5V, f = 991Hz ANALOG OUTPUT Voltage Range Load Impedance Center Voltage UNITS 18 CMOS DYNAMIC PERFORMANCE(1) THD+N at FS (0dB) THD+N at –60dB Dynamic Range Signal-To-Noise Ratio Channel Separation Level Linearity Error (–90dB) DIGITAL FILTER PERFORMANCE Pass Band Ripple Stop Band Attenuation Pass Band Stop Band De-emphasis Error Delay Time (Latency) MAX +5.5 +5.5 25.0 15.0 125 45 VDC VDC mA mA mW mW +85 +100 °C °C NOTES: (1) Tested with Shibasoku #725 THD. Meter 400Hz HPF, 30kHz LPF On, Average Mode with 20kHz bandwidth limiting. (2) Pins 4, 5, 6, 14: LRCIN, DIN, BCKIN, FORMAT. (3) Pins 15, 16, 17, 18: RSTB, DM0, DM1, MUTE (Schmitt trigger input). (4) Pin 1: XTI. (5) Pins 15, 16, 17, 18: RSTB, DM0, DM1, MUTE (if pull-up resistor is used). (6) Pins 4, 5, 6: LRCIN, DIN, BCKIN (if pull-up resistor is not used). (7) Pin 19: CLKO. (8) Pin 7: ZERO. (9) No load on pins 19 (CLKO) and 20 (XTO). ® PCM1718E 2 PIN CONFIGURATION PIN ASSIGNMENTS TOP VIEW SSOP PIN NAME FUNCTION Data Input Interface Pins XTI 1 20 XTO DGND 2 19 CLKO VDD 3 18 MUTE LRCIN 4 17 DM1 DIN 5 16 DM0 BCKIN 6 15 RSTB ZERO 7 14 FORMAT D/C_R 8 13 DC_L LRCIN Sample Rate Clock Input. Controls the update rate (fs). 5 DIN Serial Data Input. MSB first, right justified (Sony format, 18 bits) or I2S (Philips format, 16 or 18 bits). 6 BCKIN Bit Clock Input. Clocks in the data present on DIN input. Mode Control and Clock Signals 9 12 VOUTL AGND 10 11 VCC VOUTR 4 1 XTI Oscillator Input (External Clock Input). For an internal clock, tie XTI to one side of the crystal oscillator. For an external clock, tie XTI to the output of the chosen external clock. 14(1) FORMAT A “HIGH” selects I2S input data format, and a “LOW” selects Normal (Sony) input data format. De-emphasis selection. 16(1) DM0 17(1) DM1 18(1) MUTE 19 CLKO 20 XTO De-emphasis selection. Soft Mute Control. When set “LOW”, the outputs are muted. Buffered Output of Oscillator. Equivalent to XTI. Oscillator Output. When using the internal clock, tie to the opposite side (from pin 1) of the crystal oscillator. When using an external clock, leave XTO open. Operational Controls and Flags PACKAGE INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) PCM1718E 20-Pin SSOP 334-1 7 ZERO Infinite Zero Detection Flag, open drain output. When the input is continuously zero for 65,536 cycles of BCKIN, ZERO is “LOW”. 15(1) RSTB Resets DAC operation with an active “LOW” pulse. Analog Output Functions NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ABSOLUTE MAXIMUM RATINGS Power Supply Voltage ....................................................................... +6.5V +VCC to +VDD Difference ................................................................... ±0.1V Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V) Power Dissipation .......................................................................... 200mW Operating Temperature Range ......................................... –25°C to +85°C Storge Temperature ........................................................ –55°C to +125°C Lead Temperature (soldering, 5s) .................................................. +260°C Thermal Resistance, θJA ....................................................................................... +70°C/W 8 D/C_R Right Channel Output Amplifier Common. Bypass to ground with 10µF capacitor. 9 VOUTR Right Channel Analog Output. VOUT max = 0.62 x VCC. 12 VOUTL Left Channel Analog Output. VOUT max = 0.62 x VCC. 13 D/C_L Left Channel Output Amplifier Common. Bypass to ground with 10µF capacitor. Power Supply Connections 2 DGND 3 VDD 10 AGND 11 VCC Digital Ground. Digital Power Supply (+5V or +3V). Analog Ground. Analog Power Supply (+5V or +3V). NOTE: (1) With internal pull-up. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 PCM1718E TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = +5V, RL = 100Ω, CL = 2pF, and RFB = 402Ω, unless otherwise noted. DYNAMIC PERFORMANCE THD+N vs VCC, VDD fIN = 1kHz, 384fs DYNAMIC RANGE vs INPUT DATA fIN = 1kHz –30 –60dB –88 –34 –90 –92 98 Dynamic Range (dB) THD+N at FS (dB) –86 100 THD+N at –60dB (dB) –84 96 384fs 94 –38 92 0dB –94 90 3.5 4.0 4.5 5.0 5.5 6.0 16-Bit 18-Bit VCC, VDD (V) Input Data THD+N vs TEMPERATURE fIN = 1kHz, 384fs THD+N vs INPUT DATA fIN = 1kHz, FS (0dB) –30 –88 –34 –60dB –90 –92 –86 THD+N (dB) –86 –84 THD+N at –60dB (dB) –84 –38 –88 384fs –90 –92 256fs 0dB –90 –25 –94 0 25 50 75 85 100 16-Bit 18-Bit Temperature (°C) Input Data DYNAMIC RANGE AND SNR vs VCC, VDD fIN = 1kHz, 384fs 100 SNR 98 96 (dB) THD+N at FS (dB) 256fs Dynamic Range 94 92 90 3.5 4.0 4.5 VCC, VDD ® PCM1718E 4 5.0 5.5 6.0 TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = +5V, RL = 44.1kHz, fSYS = 384fs, and 18-bit input data, unless otherwise noted. DIGITAL FILTER PASSBAND RIPPLE CHARACTERISTIC OVERALL FREQUENCY CHARACTERISTIC 0 –20 –0.2 –40 –0.4 dB dB 0 –60 –0.6 –80 –0.8 –1 –100 0 0.4536fs 1.3605fs 2.2675fs 3.1745fs 4.0815fs 0 0.1134fs 5k 10k 15k Frequency (Hz) 20k 0 Level (dB) Error (dB) 10k 15k 20k 3628 0 25k 4999.8375 Level (dB) Error (dB) 15k 20k 9999.675 Frequency (Hz) 14999.5125 19999.35 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0 10k 14512 DE-EMPHASIS ERROR (48kHz) DE-EMPHASIS FREQUENCY RESPONSE (48kHz) 0 –2 –4 –6 –8 –10 –12 5k 10884 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 Frequency (Hz) 0 7256 Frequency (Hz) DE-EMPHASIS ERROR (44.1kHz) DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) 5k 0.4535fs 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 25k 0 –2 –4 –6 –8 –10 –12 0 0.3402fs DE-EMPHASIS ERROR (32kHz) Error (dB) Level (dB) DE-EMPHASIS FREQUENCY RESPONSE (32kHz) 0 –2 –4 –6 –8 –10 –12 0 0.2268fs Frequency (Hz) Frequency (Hz) 25k 5442 10884 Frequency (Hz) 16326 21768 Frequency (Hz) ® 5 PCM1718E SYSTEM CLOCK The system clock for PCM1718 must be either 256fs or 384fs, where fs is the audio sampling frequency (typically 32kHz, 44.1kHz, or 48kHz). The system clock is used to operate the digital filter and the modulator. ference internally. If the phase difference between left-right and system clocks is greater than 6 bit clocks (BCKIN), the synchronization is performed internally. While the synchronization is processing, the analog output is forced to a DC level at bipolar zero. The synchronization typically occurs in less than 1 cycle of LRCIN. The system clock can be either a crystal oscillator placed between XTI (pin 1) and XTO (pin 20), or an external clock input to XTI. If an external system clock is used, XTO is open (floating). Figure 1 illustrates the typical system clock connections. DATA INTERFACE FORMATS Digital audio data is interfaced to PCM1718 on pins 4, 5, and 6—LRCIN (left-right clock), DIN (data input) and BCKIN (bit clock). PCM1718 can accept both normal and I2S data formats. Normal data format is MSB first, two’s complement, right-justified. I2S data is compatible with Philips serial data protocol. Figures 3 and 4 illustrate the input data formats. PCM1718 has a system clock detection circuit which automatically senses if the system clock is operating at 256fs or 384fs. The system clock should be synchronized with LRCIN (pin 4) clock. LRCIN (left-right clock) operates at the sampling frequency fs. In the event these clocks are not synchronized, PCM1718 can compensate for the phase dif- CLKO CLKO Internal System Clock C1 X’tal Internal System Clock XTI XTI External Clock C2 XTO C1, C2 = typ 22pF XTO PCM1718E PCM1718E CRYSTAL RESONATOR CONNECTION EXTERNAL CLOCK INPUT XTO pin = No Connection FIGURE 1. Internal Clock Circuit Diagram and Oscillator Connection. FUNCTIONAL CONTROLS tXTIH 1/256fs or 1/384fs PCM1718 allows the user to control the input data format, soft mute, and digital de-emphasis frequency. Table I illustrates the selectable functions: 64% OF VDD 28% OF VDD FUNCTION tXTIL External System Clock High External System Clock Low tXTIH tXTIL Data Input Format Normal I2S De-emphasis 32kHz 44.1kHz 48kHz 10ns (min) 10ns (min) FIGURE 2. External Clock Timing Requirements. PCM1718E 6 DM0, DM1 (Pins 16, 17) Soft Mute MUTE (Pin 18) Reset RSTB (Pin 15) TABLE I. Selectable Functions. ® CONTROL PIN FORMAT (Pin 14) 1 f/s Left-channel Data Right-channel Data LRCIN (pin 4) BCKIN (pin 6) Audio Data Word = 18-Bit MSB DIN (pin 5) 1 16 17 18 LSB 2 3 16 MSB 17 18 1 LSB 2 3 16 17 18 FIGURE 3. “Normal” Data Input Timing. 1 f/s Left-channel Data Right-channel Data LRCIN (pin 4) BCKIN (pin 6) Audio Data Word = 16-Bit MSB DIN (pin 5) 1 Audio Data Word = 18-Bit MSB 1 DIN (pin 5) LSB 2 3 2 3 14 MSB 15 16 1 LSB 16 17 18 LSB 2 3 2 3 14 15 16 MSB 1 1 2 1 2 LSB 16 17 18 FIGURE 4. “I2S” Data Input Timing. Data Format LRCIN tBCH tBCL BCKIN 50% of VDD A “HIGH” on pin 14 (FORMAT) sets the input format to I2S, and a “LOW” sets the format to Normal (MSB-first, right-justified Sony format). 50% of VDD Soft Mute 50% of VDD A “LOW” on pin 18 (MUTE) causes both outputs to be muted. This muting is done in the digital domain so there is no audible “click” when the soft mute is enacted. tLB tBL tBCY DIN tDH tDS BCKIN Pulsewidth (High Level) BCKIN Pulsewidth (Low Level) BCKIN Pulse Cycle Time BCKIN Rising Edge ➝ LRCIN Edge LRCIN Edge ➝ BCKIN Rising Edge DIN Setup Time DIN Hold Time De-Emphasis tBCH tBCL tBCY tBL tLB tDS tDH PCM1718 allows for digital de-emphasis for all three standard sampling frequencies: 50ns (min) 50ns (min) 100ns (min) 30ns (min) 30ns (min) 30ns (min) 30ns (min) FIGURE 5. Data Input Timing. DM1 (Pin 17) DM0 (Pin 16) 0 0 1 1 0 1 0 1 De-Emphasis Mode OFF 48kHz 44.1kHz 32kHz ® 7 PCM1718E Reset For the RSTB-pin, PSTB-pin accepts external forced reset by RSTB = L. During RSTB = L, the output of the DAC is invalid and the analog outputs are forced to VCC/2 after internal initialize (1024 system clocks count after RSTB = H.) Figure 7 illustrates the timing of RSTB-pin reset. PCM1718 has both internal power on reset circuit and the RSTB-pin (pin 15) which accepts external forced reset by RSTB = LOW. For internal power on reset, initialize (reset) is done automatically at power on VDD >2.2V (typ). During internal reset = LOW, the output of the DAC is invalid and the analog outputs are forced to VCC/2. Figure 6 illustrates the timing of internal power on reset. 2.6V VCC/VDD 2.2V 1.8V Reset Reset Removal Internal Reset 1024 system (= XTI) clocks XTI Clock FIGURE 6. Internal Power-On Reset Timing. RSTB-pin 50% of VDD tRST(1) Reset Reset Removal Internal Reset 1024 system (XTI) clocks XTI Clock NOTE: (1) tRST = 20ns min FIGURE 7. RSTB-Pin Reset Timing. 0.1µF ~ 10µF Bypass Capacitor +5V or +3 Analog Power Supply 2 10pF ~ 22pF 1 DGND XTI 3 VDD FOUT = Inverted XTI (1 pin) to Other System CLKO 19 20 XTO 10pF ~ 22pF PCM Audio Data Processor 4 LRCIN 5 DIN 6 BCKIN VOUTR 9 D/C_R 8 Post Low Pass Filter + + Format Control 14 FORMAT D/C_L 13 18 MUTE VOUTL 12 (optional) 10µF 10µF Post Low Pass Filter VDD 17 DM1 ZERO 16 DM0 15 RSTB AGND VCC 10 11 Reset 0.1µF ~ 10µF Bypass Capacitor FIGURE 8. Typical Connection Diagram of PCM1718. ® PCM1718E (optional) 4.7kΩ 8 7 To External Mute Circuit POWER SUPPLY CONNECTIONS PCM1718 has two power supply connections: digital (VDD) and analog (VCC). Each connection also has a separate ground. If the power supplies turn on at different times, there is a possibility of a latch-up condition. To avoid this condition, it is recommended to have a common connection between the digital and analog power supplies. If separate supplies are used without a common connection, the delta between the two supplies during ramp-up time must be less than 0.6V. A block diagram of the 5-level delta-sigma modulator is shown in Figure 10. This 5-level delta-sigma modulator has the advantage of stability and clock jitter sensitivity over the typical one-bit (2 level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the internal 8-times interpolation filter is 48fs for a 384fs system clock, and 64fs for a 256fs system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in Figure 11. An application circuit to avoid a latch-up condition is shown in Figure 9. Digital Power Supply Analog Power Supply VDD VCC DGND AGND 3rd-ORDER ∆Σ MODULATOR 20 0 FIGURE 9. Latch-up Prevention Circuit. –20 Gain (–dB) –40 BYPASSING POWER SUPPLIES The power supplies should be bypassed as close as possible to the unit. Refer to Figure 8 for optimal values of bypass capacitors. –60 –80 –100 –120 –140 THEORY OF OPERATION –160 0 The delta-sigma section of PCM1718 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. This section converts the oversampled input data to 5-level deltasigma format. + In + 8fs 18-Bit 5 10 25 + + – 20 FIGURE 11. Quantization Noise Spectrum. + Z–1 15 Frequency (kHz) + Z–1 Z–1 – + + 5-level Quantizer + 4 3 Out 48fs (384fs) 64fs (256fs) 2 1 0 FIGURE 10. 5-Level ∆Σ Modulator Block Diagram. ® 9 PCM1718E APPLICATION CONSIDERATIONS INTERNAL ANALOG FILTER FREQUENCY RESPONSE (20Hz~24kHz, Expanded Scale) 1.0 DELAY TIME There is a finite delay time in delta-sigma converters. In A/D converters, this is commonly referred to as latency. For a delta-sigma D/A converter, delay time is determined by the order number of the FIR filter stage, and the chosen sampling rate. The following equation expresses the delay time of PCM1718: dB 0.5 0 –0.5 TD = 11.125 x 1/fs For fs = 44.1kHz, TD = 11.125/44.1kHz = 251.4µs –1.0 20 Applications using data from a disc or tape source, such as CD audio, CD-Interactive, Video CD, DAT, Minidisc, etc., generally are not affected by delay time. For some professional applications such as broadcast audio for studios, it is important for total delay time to be less than 2ms. 100 1k Frequency (Hz) 10k 24k FIGURE 12. Low Pass Filter Frequency Response. OUTPUT FILTERING INTERNAL ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz) dB For testing purposes all dynamic tests are done on the PCM1718 using a 20kHz low pass filter. This filter limits the measured bandwidth for THD+N, etc. to 20kHz. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the specifications. The low pass filter removes out of band noise. Although it is not audible, it may affect dynamic specification numbers. The performance of the internal low pass filter from DC to 24kHz is shown in Figure 12. The higher frequency rolloff of the filter is shown in Figure 13. If the user’s application has the PCM1718 driving a wideband amplifier, it is recommended to use an external low pass filter. A simple 3rdorder filter is shown in Figure 14. For some applications, a passive RC filter or 2nd-order filter may be adequate. 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 10 100 1k 10k 100k 1M 10M Frequency (Hz) FIGURE 13. Low Pass Filter Frequency Response. GAIN vs FREQUENCY 6 90 + 10kΩ VSIN 10kΩ 680pF OPA604 10kΩ 0 –34 –90 –54 –180 Phase 100pF – –74 –270 –94 –360 100 FIGURE 14. 3rd-Order LPF. ® PCM1718E 10 1k 10k Frequency (Hz) 100k 1M Phase (°) 1500pF Gain (dB) Gain –14 Test Disk Shibasoku #725 Through Lch CD Player Digital DAI DEMPCM1718 PGA THD Meter 0dB/60dB 30KHz LPF on 11th-order LPF Rch For test of S/N ratio and Dynamic Range, A-filter ON. FIGURE 15. Test Block Diagram. TEST CONDITIONS Figure 15 illustrates the actual test conditions applied to PCM1718 in production. The 11th-order filter is necessary in the production environment for the removal of noise resulting from the relatively long physical distance between the unit and the test analyzer. In most actual applications, the 3rd-order filter shown in Figure 14 is adequate. Under normal conditions, THD+N typical performance is –70dB with a 30kHz low pass filter (shown here on the THD meter), improving to –89dB when the external 20kHz 11thorder filter is used. For cost-sensitive applications, a single RC filter, as shown in Figure 18, may be adequate. 110 Dynamic Range (dB) 105 100 Multi-level 95 90 85 80 75 PWM 70 65 60 0 100 200 300 400 500 600 Clock Jitter (ps) EVALUATION FIXTURES DEM-PCM1718 This evaluation fixture is primarily intended for quick evaluation of the PCM1718’s performance. DEM-PCM1718 can accept either an external clock or a user-installed crystal oscillator. All of the functions can be controlled by on-board switches. DEM-PCM1718 does not contain a receiver chip or an external low pass filter. DEM-PCM1718 requires a single +2.7V to +5V power supply. FIGURE 16. Simulation Results of Clock Jitter Sensitivity. 2 1 0 OUT-OF-BAND NOISE CONSIDERATIONS Delta-sigma DACs are by nature very sensitive to jitter on the master clock. Phase noise on the clock will result in an increase in noise, ultimately degrading dynamic range. It is difficult to quantify the effect of jitter due to problems in synthesizing low levels of jitter. One of the reasons deltasigma DACs are prone to jitter sensitivity is the large quantization noise when the modulator can only achieve two discrete output levels (0 or 1). The multi-level delta-sigma DAC has improved theoretical SNR because of multiple output states. This reduces sensitivity to jitter. Figure 16 contrasts jitter sensitivity between a one-bit PWM type DAC and multi-level delta-sigma DAC. The data was derived using a simulator, where clock jitter could be completely synthesized. 14.4ps –1 48fs 2 FIGURE 17. Simulation Method for Clock Jitter. PCM1718 Output 1kΩ 1800pF fC = 88kHz FIGURE 18. RC Output Filter. ® 11 PCM1718E