PCM1804
SLES022A – DECEMBER 2001
FULL DIFFERENTIAL ANALOG INPUT 24-BIT, 192-kHz
STEREO A/D CONVERTER
D Small 28-Pin SSOP
D DSD Output: 1 Bit, 64 fS
D Lead-Free Product
FEATURES
D 24-Bit Delta-Sigma Stereo A/D Converter
D High Performance:
D
D
D
D
D
D
D
D
D
– Dynamic Range: 112 dB (Typically)
– SNR: 111 dB (Typically)
– THD+N: -102 dB (Typically)
High Performance Linear Phase antialias
Digital Filter:
– Pass-Band Ripple: ±0.005 dB
– Stop-Band Attenuation: –100 dB
Fully Differential Analog Input: ±2.5 V
Audio Interface: Master or Slave Mode
Selectable
Data Formats: Left Justified, I2S, Standard
24-Bit and DSD
Function:
– Peak Detection
– Low-Cut Filter (HPF): –3 dB at 1 Hz,
fS = 48 kHz
Sampling Rate up to 192 kHz
System Clock: 128 fS, 256 fS, 384 fS, 512 fS, or
768 fS
Dual Power Supplies:
– 5 V for Analog
– 3.3 V for Digital
Power Dissipation: 225 mW
APPLICATIONS
D AV Amp
D MD Player
D Digital VTR
D Digital Mixer
D Digital Recorder
DESCRIPTION
The PCM1804 is a high-performance single chip stereo
A/D converter with full differential analog voltage input.
The PCM1804 uses a precision delta-sigma modulator
and includes a linear phase antialias digital filter and
HPF (low-cut filter) that removes dc offset of the input
signal. The PCM1804 is suitable for a wide variety of
mid-to-high grade consumer and professional
applications, where excellent performance and 5-V
analog supply and 3.3-V digital power supply operation
are required. The PCM1804 can achieve both PCM
audio and DSD format due to precision delta-sigma
modulator. The PCM1804 is fabricated on an advanced
CMOS process and is available in small 28-pin SSOP
package.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
PCM1804DB
28 Lead SSOP
28-Lead
28DB
OPERATING
TEMPERATURE RANGE
PACKAGE
MARKING
–10°C
10°C to 70°C
PCM1804DB
ORDERING NUMBER
TRANSPORT
MEDIA
PCM1804DB
Tube
PCM1804DBR
Tape and Reel
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
PCM1804
SLES022A – DECEMBER 2001
pin assignments
PCM1804 PACKAGE
(TOP VIEW)
VREFL
AGNDL
VCOML
VINL+
VINL–
FMT0
FMT1
S/M
OSR0
OSR1
OSR2
BYPAS
DGND
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VREFR
AGNDR
VCOMR
VINR+
VINR–
AGND
VCC
OVFL
OVFR
RST
SCKI
LRCK/DSDBCK
BCK/DSDL
DATA/DSDR
functional block diagram
OSR0
CLK
Control
SCKI
OSR1
OSR2
VINL+
VINL–
VCOML
AGNDL
VREFL
VREFR
AGNDR
VCOMR
VINR+
VINR–
Delta-Sigma
Modulator (L)
Decimation
Filter (L)
HPF
S/M
FMT0
FMT1
VREFL
Serial
Output
Interface
VREFR
LRCK/DSDBCK
BCK/DSDL
DATA/DSDR
Decimation
Filter (R)
Delta-Sigma
Modulator (R)
HPF
OVFL
OVFR
BYPAS
Power Supply
VCC AGND
2
DGND
RST
VDD
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PCM1804
SLES022A – DECEMBER 2001
Terminal Functions
TERMINAL
NAME
AGND
PIN
I/O
DESCRIPTIONS
23
–
Analog ground
AGNDL
2
–
Analog ground for VREFL
AGNDR
27
–
Analog ground for VREFR
BCK/DSDL
16
I/O
BYPAS
12
I
DATA/DSDR
15
O
L-channel and R-channel audio data output in PCM mode. R-channel audio data output in DSD mode.
(DSD output, when DSD mode)
DGND
13
–
Digital ground
FMT0
6
I
Audio data format 0. See Table 5†
Audio data format 1. See Table 5†
FMT1
7
I
LRCK/DSDBCK
17
I/O
OSR0
9
I
OSR1
10
I
Bit clock input/output in PCM mode. L-channel audio data output in DSD mode. §
HPF bypass control. High: HPF disable, Low: HPF enable§
Sampling clock input / output in PCM and DSD mode. §
Oversampling ratio 0. See Table 1 and Table 2†
OSR2
11
I
Oversampling ratio 1. See Table 1 and Table 2†
Oversampling ratio 2. See Table 1 and Table 2†
OVFL
21
O
Overflow signal of L-channel in PCM mode. This is available in PCM mode only.
OVFR
20
O
RST
19
I
Overflow signal of R-channel in PCM mode. This is available in PCM mode only.
Reset, power down input, active low†
SCKI
18
I
S/M
8
I
System clock input; 128 fS, 256 fS, 384 fS, 512 fS or 768 fS.‡
Master / slave mode selection. See Table 4.†
VCC
VCOML
22
–
Analog power supply
3
–
L-channel analog common mode voltage (2.5 V)
VCOMR
VDD
26
–
R-channel analog common mode voltage (2.5 V)
14
–
Digital power supply
VINL–
VINL+
5
I
L-channel analog input, negative pin
4
I
L-channel analog input, positive pin
VINR–
VINR+
24
I
R-channel analog input, negative pin
25
I
R-channel analog input, positive pin
VREFL
1
–
L-channel voltage reference output, requires capacitors for decoupling to AGND
VREFR
28
–
R-channel voltage reference output, requires capacitors for decoupling to AGND
† Schmitt-trigger input with internal pulldown (51 kΩ typically), 5-V tolerant.
‡ Schmitt-trigger input, 5-V tolerant.
§ Schmitt-trigger input
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3
PCM1804
SLES022A – DECEMBER 2001
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage: VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
Ground voltage differences: AGND, AGNDL, AGNDR, DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V
Digital input voltage: FMT0, FMT1, S/M, OSR0, OSR1, OSR2, SCKI, RST . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V
BYPAS, DATA/DSDR, BCK/DSDL, LRCK/DSDBCK,
OVFL, OVFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VDD + 0.3 V)
Analog input voltage: VREFL, VREFR, VCOML, VCOMR, VINL+, VINR+, VINL–, VINR– . . . –0.3 V to (VCC + 0.3 V)
Input current (any pins except supplies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Ambient temperature under bias, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature (soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5 s
Package temperature (IR reflow, peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 10 s
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4
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PCM1804
SLES022A – DECEMBER 2001
electrical characteristics, all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode,
single-speed mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless otherwise noted)
PCM1804DB
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
24
UNIT
Bits
DATA FORMAT
Standard, I2S,
left justified
Audio data interface format
Audio data bit length
24-bits
MSB first,
2s complement, DSD
Audio data format
DIGITAL INPUT/OUTPUT
Logic family
TTL compatible
See Notes 1 and 2
2
5.5
See Note 3
2
VDD
0.8
VIH
High level input voltage
High-level
VIL
Low-level input voltage
See Notes 1, 2, and 3
High-level
High
level in
input
ut current
VIN = VDD,
VIN = VDD,
See Note 1
IIH
See Note 2
±10
VIN = VDD,
VIN = 0 V,
See Note 3
±100
IIL
Low level input current
Low-level
VOH
VOL
65
±10
See Note 3
±50
High-level output voltage
See Note 4
Low-level output voltage
IOL = 1 mA,
See Note 5
VDC
100
See Notes 1 and 2
VIN = 0 V,
IOH = –1 mA,
VDC
2.4
µA
µA
A
VDC
0.4
VDC
192
kHz
CLOCK FREQUENCY
fS
Sampling frequency
System clock frequency
32
256 fS, Single rate, See Note 5
12.288
384 fS, Single rate, See Note 5
18.432
512 fS, Single rate, See Note 5
24.576
768 fS, Single rate, See Note 5
36.864
256 fS, Dual rate,
See Note 6
24.576
384 fS, Dual rate,
See Note 6
36.864
128 fS, Quad rate, See Note 7
24.576
192 fS, Quad rate, See Note 7
36.864
MHz
DC ACCURACY
Gain mismatch channel-to-channel
Gain error (VIN = –0.5 dB)
Bipolar zero error
HPF bypass
±0.2
±3
%/FSR
±4
%/FSR
%/FSR
NOTES: 1. Pins 6–11, 19: FMT0, FMT1, S/M, OSR0, OSR1, OSR2, RST (Schmitt-trigger input with internal pulldown (51 kΩ typically), 5 V
tolerant)
2. Pin 18: SCKI (Schmitt-trigger input, 5 V tolerant)
3. Pins 12, 16–17: BYPAS, BCK/DSDL, LRCK/DSDBCK (in slave mode, Schmitt-trigger input)
4. Pins 15–17, 20, and 21: DATA/DSDR, BCK/DSDL, LRCK/DSDBCK (in master mode), OVFR, OVFL
5. Single rate, fS = 48 kHz
6. Dual rate, fS = 96 kHz
7. Quad rate, fS = 192 kHz
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5
PCM1804
SLES022A – DECEMBER 2001
electrical characteristics, all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode,
single-speed mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless otherwise noted)
(continued)
PCM1804DB
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–102
–95
UNIT
DYNAMIC PERFORMANCE (see Note 8)
THD+N
Total
T
t lh
harmonic
i di
distortion
t ti
plus noise
Dynamic range (A-weighted)
(A weighted)
VIN = –0.5 dB
VIN = –60 dB
fS = 48 kHz,
kHz System clock = 256 fS
VIN = –0.5 dB
VIN = –60 dB
fS = 96 kHz,
kHz System clock = 256 fS
VIN = –0.5 dB
VIN = –60 dB
fS = 192 kHz,
kHz System clock = 128 fS
VIN = –0.5 dB
DSD mode
VIN = –60
60 dB
fS = 48 kHz, System clock = 256 fS
fS = 96 kHz, System clock = 256 fS
–49
–101
–47
–101
–47
–100
106
separation
Channel se
aration
112
112
fS = 192 kHz, System clock = 128 fS
dB
112
DSD mode
SNR (A-weighted)
(A weighted)
dB
112
fS = 48 kHz,
fS = 96 kHz,
System clock = 256 fS
105
System clock = 256 fS
111
111
fS = 192 kHz,
DSD mode
System clock = 128 fS
111
fS = 48 kHz,
fS = 96 kHz,
System clock = 256 fS
System clock = 256 fS
107
fS = 192 kHz,
System clock = 128 fS
107
dB
111
97
109
dB
ANALOG INPUT
Input voltage
Differential input
Center voltage
Input impedance
Single end
±2.5
V
2.5
VDC
10
kΩ
DIGITAL FILTER PERFORMANCE
Pass-band edge
Single rate, dual rate
Stop-band edge
Single rate, dual rate
Pass-band ripple
Single rate, dual rate
Stop-band attenuation
Single rate, dual rate
Pass-band edge (–0.005 dB)
Quad rate
Pass-band edge (–3 dB)
Quad rate
Stop-band edge
Quad rate
Pass-band ripple
Quad rate
Stop-band attenuation
Quad rate
0.453 fS
0.547 fS
HPF frequency response
Hz
±0.005
dB
0.375 fS
Hz
0.49 fS
Hz
–100
dB
0.77 fS
Hz
±0.005
–135
Group delay
dB
dB
37/fS
fS/48000
–3 dB
Hz
s
Hz
NOTE 8: fIN = 1 kHz, using Audio Precision’s System II, RMS mode with 20-kHz LPF and 400-Hz HPF in calculation for single rate, with 40-kHz
LPF for dual and quad rate in calculation.
6
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PCM1804
SLES022A – DECEMBER 2001
electrical characteristics, all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode,
single-speed mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless otherwise noted)
(continued)
PCM1804DB
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.75
5
5.25
3
3.3
3.6
VCC = 5 V,
See Notes 5, 6, and 7
VDD = 3.3 V, See Notes 5 and 9
35
45
15
20
VDD = 3.3 V, See Notes 6 and 9
VDD = 3.3 V, See Notes 7 and 9
27
UNIT
POWER SUPPLY REQUIREMENTS
VCC
VDD
Supply voltage range
ICC
IDD
Supply current
Operation,
Operation,
PD
Power dissipation
Operation,
VCC = 5 V, VDD = 3.3 V,
VCC = 5 V, VDD = 3.3 V,
VCC = 5 V, VDD = 3.3 V,
VDC
mA
18
See Notes 5 and 9
225
See Notes 6 and 9
265
See Notes 7 and 9
235
Power down, VCC = 5 V, VDD = 3.3 V
290
mW
5
TEMPERATURE RANGE
Operation temperature
–10
θJA
Thermal resistance
28-pin SSOP
NOTES: 5. Single rate, fS = 48 kHz
6. Dual rate, fS = 96 kHz
7. Quad rate, fS = 192 kHz
9. Minimum load on DATA/DSDR (pin 15)
70
100
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°C
°C/W
7
PCM1804
SLES022A – DECEMBER 2001
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION PLUS
NOISE (–0.5 dB, –60 dB)
vs
TEMPERATURE
DYNAMIC RANGE AND SNR
vs
TEMPERATURE
–90
–35
–95
–40
–45
–0.5 dB
–50
–60 dB
–105
0
20
40
T – Temperature – °C
60
115
Dynamic Range
105
100
–20
–55
80
Figure 1
THD+N – Total Harmonic Distortion Plus Nouse – dB (–0.5 dB)
SNR
110
0
20
40
T – Temperature – °C
Figure 2
TOTAL HARMONIC DISTORTION PLUS
NOISE (–0.5 dB, –60 dB)
vs
SUPPLY VOLTAGE
–35
–90
–40
–95
–45
–100
–0.5 dB
–105
–110
4.5
–60 dB
4.75
5
5.25
VCC – Supply Voltage – V
–50
–55
5.5
THD+N – Total Harmonic Distortion Plus Nouse – dB (–60 dB)
–100
–110
–20
120
Dynamic Range and SNR – dB
THD+N – Total Harmonic Distortion Plus Nouse – dB (–0.5 dB)
single rate
Figure 3
† All specifications at T = 25°C, V
A
CC = 3.3 V, VDD = 5 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless otherwise noted.
8
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60
80
PCM1804
SLES022A – DECEMBER 2001
TYPICAL CHARACTERISTICS
single rate (continued)
DYNAMIC RANGE AND SNR
vs
SUPPLY VOLTAGE
Dynamic Range and SNR – dB
120
115
Dynamic Range
SNR
110
105
100
4.5
4.75
5
5.25
VCC – Supply Voltage – V
5.5
TOTAL HARMONIC DISTORTION PLUS
NOISE (–0.5 dB, –60 dB)
vs
SAMPLING FREQUENCY
–90
–35
–95
–40
–100
–105
–110
–0.5 dB
–60 dB
–45
–50
–55
32
44.1
48
fS – Sampling Frequency – kHz
THD+N – Total Harmonic Distortion Plus Nouse – dB (–60 dB)
THD+N – Total Harmonic Distortion Plus Nouse – dB (–0.5 dB)
Figure 4
Figure 5
† All specifications at T = 25°C, V
A
CC = 3.3 V, VDD = 5 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless otherwise noted.
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9
PCM1804
SLES022A – DECEMBER 2001
TYPICAL CHARACTERISTICS
single rate (continued)
AMPLITUDE
vs
FREQUENCY
DYNAMIC RANGE AND SNR
vs
SAMPLING FREQUENCY
0
120
Output Spectrum:
–0.50 dB,
N = 8192
–40
115
Dynamic Range
Amplitude – dB
Dynamic Range and SNR – dB
–20
SNR
110
–60
–80
–100
–120
105
–140
–160
100
0
44.1
32
48
fS – Sampling Frequency – kHz
12000
f – Frequency – Hz
Figure 6
Figure 7
AMPLITUDE
vs
FREQUENCY
THD+N – Totla Harmonic Distortion Plus Noise – dB
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
SIGNAL LEVEL
0
fS = 96 kHz,
System Clock = 256 fS
–20
Amplitude – dB
–40
Output Spectrum:
–60 dB,
N = 8192
–60
–80
–100
–120
–140
–160
0
12000
f – Frequency – Hz
24000
24000
0
–20
–40
–60
–80
–100
–120
–100
–80
–60
–40
–20
Signal Level – dB
Figure 8
Figure 9
† All specifications at T = 25°C, V
A
CC = 3.3 V, VDD = 5 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless otherwise noted.
10
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0
PCM1804
SLES022A – DECEMBER 2001
TYPICAL CHARACTERISTICS
dual rate
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
0
fS = 96 kHz,
System Clock = 256 fS
–20
–40
Amplitude – dB
–40
Amplitude – dB
Output Spectrum:
–60 dB,
N = 8192
–20
–60
Output Spectrum:
–0.5 dB,
N = 8192
–80
–100
–60
–80
–100
–120
–120
–140
–140
–160
–160
0
24000
f – Frequency – Hz
48000
24000
f – Frequency – Hz
0
Figure 10
48000
Figure 11
quad rate
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
0
fS = 192 kHz,
System Clock = 128 fS
–20
–40
–40
–60
Amplitude – dB
Amplitude – dB
fS = 192 kHz,
System Clock = 128 fS
–20
Output Spectrum:
–0.5 dB,
N = 8192
–80
–100
–80
–100
–120
–120
–140
–140
–160
0
48000
f – Frequency – Hz
96000
Output Spectrum:
–60 dB,
N = 8192
–60
–160
0
48000
96000
f – Frequency – Hz
Figure 12
Figure 13
† All specifications at T = 25°C, V
A
CC = 3.3 V, VDD = 5 V, master mode, 24-bit data, unless otherwise noted.
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11
PCM1804
SLES022A – DECEMBER 2001
TYPICAL CHARACTERISTICS
DSD mode
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
–20
–20
–40
–40
–60
–80
Amplitude – dB
Amplitude – dB
0
Output Spectrum:
–0.5 dB,
N = 8192
–100
–60
–80
–100
–120
–120
–140
–140
–160
0
11025
f – Frequency – Hz
Output Spectrum:
–60 dB,
N = 8192
–160
22050
0
11025
f – Frequency – Hz
Figure 14
22050
Figure 15
† All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 44.1 kHz, system clock = 16.9344 MHz, unless otherwise noted.
linear phase antialias digital filter frequency response
OVERALL CHARACTERISTICS AT
SINGLE RATE FILTER
STOPBAND ATTENUATION CHARACTERISTICS AT
SINGLE RATE FILTER
50
0
fS = 48 kHz
–10
fS = 48 kHz
–20
0
–30
Amplitude – dB
Amplitude – dB
–40
–50
–100
–50
–60
–70
–80
–90
–100
–110
–150
–120
–130
–200
0
0.5
1
1.5
2
2.5
3
Normalized Frequency – × fS
3.5
4
–140
–150
0.25
0.5
0.75
Normalized Frequency – × fS
Figure 17
Figure 16
12
0
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1
PCM1804
SLES022A – DECEMBER 2001
TYPICAL CHARACTERISTICS
linear phase antialias digital filter frequency response (continued)
PASSBAND RIPPLE CHARACTERISTICS AT
SINGLE RATE FILTER
TRANSIENT BAND CHARACTERISTICS AT
SINGLE RATE FILTER
0.02
0
fS = 48 kHz
fS = 48 kHz
–1
–2
–3
–0.02
Amplitude – dB
Amplitude – dB
0
–0.04
–4
–5
–6
–0.06
–7
–8
–0.08
–9
–0.1
0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency – × fS
–10
0.45
0.6
0.47
0.49
0.51
0.53
Normalized Frequency – × fS
Figure 18
0.55
Figure 19
OVERALL CHARACTERISTICS AT
DUAL RATE FILTER
STOPBAND ATTENUATION CHARACTERISTICS AT
DUAL RATE FILTER
50
0
fS = 96 kHz
fS = 96 kHz
–10
–20
–30
0
Amplitude – dB
Amplitude – dB
–40
–50
–100
–50
–60
–70
–80
–90
–100
–110
–150
–120
–130
–200
0
0.2 0.4
0.6
0.8
1
1.2
1.4 1.6
1.8
2
–140
–150
Normalized Frequency – × fS
Figure 20
0
0.25
0.5
0.75
Normalized Frequency – × fS
1
Figure 21
www.ti.com
13
PCM1804
SLES022A – DECEMBER 2001
TYPICAL CHARACTERISTICS
linear phase antialias digital filter frequency response (continued)
PASSBAND RIPPLE CHARACTERISTICS AT
DUAL RATE FILTER
TRANSIENT BAND CHARACTERISTICS AT
DUAL RATE FILTER
0
0.02
fS = 96 kHz
fS = 96 kHz
–1
–2
–3
–0.02
Amplitude – dB
Amplitude – dB
0
–0.04
–0.06
–4
–5
–6
–7
–8
–0.08
–9
–10
0.45
–0.1
0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency – × fS
0.6
0.47
0.49
0.51
0.53
0.55
Normalized Frequency – × fS
Figure 22
Figure 23
OVERALL CHARACTERISTICS AT
QUAD RATE FILTER
STOPBAND ATTENUATION CHARACTERISTICS AT
QUAD RATE FILTER
50
0
–10
fS = 192 kHz
fS = 192 kHz
–20
–30
0
Amplitude – dB
Amplitude – dB
–40
–50
–100
–50
–60
–70
–80
–90
–100
–110
–150
–120
–130
–200
0
0.1 0.2 0.3 0.4
0.5
0.6 0.7
0.8 0.9
1
Normalized Frequency – × fS
Figure 24
14
–140
–150
0
0.25
0.5
0.75
Normalized Frequency – × fS
Figure 25
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1
PCM1804
SLES022A – DECEMBER 2001
TYPICAL CHARACTERISTICS
linear phase antialias digital filter frequency response (continued)
PASSBAND RIPPLE CHARACTERISTICS AT
QUAD RATE FILTER
TRANSIENT BAND CHARACTERISTICS AT
QUAD RATE FILTER
0.02
0
fS = 192 kHz
fS = 192 kHz
–1
–2
–3.90 dB at 0.5 fS
–3
–0.02
Amplitude – dB
Amplitude – dB
0
–0.04
–0.06
–4
–5
–6
–7
–8
–0.08
–9
–0.1
0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency – × fS
–10
0.45
0.6
0.47
0.49
0.51
0.53
Normalized Frequency – × fS
0.55
Figure 27
Figure 26
HPF (low-cut filter) frequency response
PASSBAND CHARACTERISTICS
0.2
–20
0
Amplitude – dB
Amplitude – dB
STOPBAND CHARACTERISTICS
0
–40
–60
–0.2
–0.4
–0.6
–80
–0.8
–100
0
0.1
0.2
0.3
Normalized Frequency – × fS/1000
0.4
–1
0
0.5
1
1.5
2
2.5
3
3.5
4
Normalized Frequency – × fS/1000
Figure 28
Figure 29
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15
PCM1804
SLES022A – DECEMBER 2001
PRINCIPLES OF OPERATION
theory of operation
The PCM1804 consists of a band-gap reference, a delta-sigma modulator with full differential architecture for
L-channel and R-channel respectively, a decimation filter with a low-cut filter, and a serial interface circuit.
Figure 1 illustrates the total architecture of the PCM1804. An on-chip high-precision reference with 10-µF
external capacitor(s) provides all the reference voltage needed in the PCM1804, and it defines the full-scale
voltage range of both channels. Full differential architecture provides a wide dynamic range and excellent power
supply rejection performance. The input signal is sampled at ×128, ×64, and ×32 oversampling rate for
oversampling ratio. The single rate, dual rate, and quad rate eliminate the external sample-hold amp. Figure 31
illustrates how the PCM1804 for each oversampling ratio decimates the modulator output down to PCM data
when the modulator is running at 6.144 MHz. The delta-sigma modulation randomizes the modulator outputs
and reduces the idle tone level. The oversampled data stream from the delta-sigma modulator is converted to
a 1 fS, 24-bit digital signal, while removing high-frequency noise components by a decimation filter. The dc
components of the signal are removed by the HPF, and the HPF output is converted to a time-multiplexed serial
signal through the serial interface, which provides flexible serial formats and master/slave modes. The
PCM1804 also has a DSD output mode. The PCM1804 can output directly the signal from the modulators to
the DSDL (pin 16) and the DSDR (pin 15).
OSR0
CLK
Control
SCKI
OSR1
OSR2
VINL+
VINL–
VCOML
AGNDL
VREFL
VREFR
AGNDR
VCOMR
VINR+
VINR–
Delta-Sigma
Modulator (L)
Decimation
Filter (L)
HPF
S/M
FMT0
FMT1
VREFL
Serial
Output
Interface
VREFR
LRCK/DSDBCK
BCK/DSDL
DATA/DSDR
Decimation
Filter (R)
Delta-Sigma
Modulator (R)
HPF
OVFL
OVFR
BYPAS
Power Supply
VCC AGND
DGND
RST
VDD
Figure 30. Total Block Diagram of PCM1804
16
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PCM1804
SLES022A – DECEMBER 2001
PRINCIPLES OF OPERATION
theory of operation (continued)
0
Quad-Rate Filter
–20
Level – dB
–40
Dual-Rate Filter
Single
Rate
Filter
–60
Modulator
–80
–100
–120
–140
–160
48
0
96
144
f – Frequency – kHz
192
Figure 31. Spectrum of Modulator Output and Decimation Filter
system clock input
The PCM1804 supports 128 fS, 192 fS (only master mode at quad rate), 256 fS, 384 fS, 512 fS, and 768 fS as
a system clock, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 18).
Table 1 shows the relationship of typical sampling frequency and the system clock frequency, and Figure 32
shows system clock timing. In master mode, the system clock rate is selected by OSR2 (pin 11), OSR1 (pin 10),
and OSR0 (pin 9) as shown in Table 1. In slave mode, the system clock rate is automatically detected. In DSD
mode, OSR2 (pin 11), OSR1 (pin 10), OSR0 (pin 9), and the system clock frequency are fixed as shown in
Table 1 and 3.
tw(SCKH)
tw(SCKL)
SCKI
2V
SCKI
0.8 V
PARAMETER
MIN
UNIT
System clock pulse width high, tw(SCKH)
11
ns
System clock pulse width low, tw(SCKL)
11
ns
Figure 32. System Clock Input Timing
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17
PCM1804
SLES022A – DECEMBER 2001
PRINCIPLES OF OPERATION
power-on and reset functions
The PCM1804 has both an internal power-on reset circuit and an RST (pin 19). For internal power-on reset,
initialize (reset) is done automatically at the timing the power supply VDD exceeds 2 V (typ) and VCC exceeds
4 V (typ). RST accepts external forced reset, and a low level on RST initiates the reset sequence. As the internal
pull-down resistor terminates RST, no connection of RST is equal to the low-level input. As the system clock
is used as a clock signal of the reset circuit, the system clock has to be supplied as soon as power is supplied;
more specifically, at least three system clocks are required prior to VDD > 2 V, VCC > 4 V and RST = high. During
either VDD < 2 V (typ), VCC < 4 V (typ), or RST = low, and 1/fS (max) count after VDD > 2 V (typ),
VCC > 4 V (typ) and RST = high, the PCM1804 stays in the reset state and the digital output is forced to zero.
The digital output is valid after the reset state is released and the time of 1116/fS is passed. Figure 33 and
Figure 34 illustrate the internal power on reset and external reset timing. Figure 35 illustrates the digital output
for power on reset and control. The PCM1804 needs RST = low when SCKI, LRCK, BCK (in slave mode), and
control pins are changed.
power-down function
The PCM1804 has a power-down feature that is controlled by the RST (pin 19). Entering the power-down mode
is done by keeping the RST low-level input for over 65536/fS. In the master mode, the SCKI (pin 18) is used
as the clock signal of the power-down counter. While in the slave mode, the SCKI (pin 18) and the LRCK (pin 17)
are used as the clock signal. The clock(s) has to be supplied until the power-down sequence completes. As soon
as RST goes high, the PCM1804 starts the reset-release sequence described in the power-on and reset
functions section.
oversampling ratio
Oversampling ratio is selected by OSR2 (pin 11), OSR1 (pin 10) and OSR0 (pin 9) as shown in Table 1 and
Table 2. The PCM1804 needs RST = low when OSR2, OSR1, and OSR0 pins are changed.
Table 1. Oversampling Ratio in Master Mode
OSR2
OSR1
OSR0
OVERSAMPLING RATIO
SYSTEM CLOCK RATE
Low
Low
Low
Single rate (× 128 fS)
768 fS
Low
Low
High
Single rate (× 128 fS)
512 fS
Low
High
Low
Single rate (× 128 fS)
384 fS
Low
High
High
Single rate (× 128 fS)
256 fS
High
Low
Low
Dual rate (× 64 fS)
384 fS
High
Low
High
High
High
Low
Dual rate (× 64 fS)
Quad rate (× 32 fS)
256 fS
192 fS{
High
High
High
Low
Low
Quad rate (× 32 fS)
DSD mode (× 64 fS)
128 fS
High
DSD mode (× 64 fS)
256 fS
High
Low
High
† Only master mode at quad rate
18
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384 fS
PCM1804
SLES022A – DECEMBER 2001
PRINCIPLES OF OPERATION
Table 2. Oversampling Ratio in Slave Mode
OSR2
OSR1
OSR0
OVERSAMPLING RATIO
SYSTEM CLOCK RATE
Low
Low
Low
Low
Single rate (× 128 fS)
Automatically detected
Low
High
Dual rate (× 64 fS)
Automatically detected
Low
High
Low
Quad rate (× 32 fS)
Automatically detected
Low
High
High
Reserved
–
High
Low
Low
Reserved
–
High
Low
High
Reserved
–
High
High
Low
Reserved
–
High
High
High
Reserved
–
Table 3. Sampling Frequency and System Clock Frequency
OVERSAMPLING RATIO
Single rate (see Note 10)
Dual rate (see Note 11)
Quad rate (see Note 12)
SAMPLING FREQUENCY
128 fS
SYSTEM CLOCK FREQUENCY (MHz)
192 fS{
256 fS
384 fS
512 fS
8.192
12.288
16.384
768 fS
24.576
—
11.2896
16.9344
22.5792
33.8688
—
12.288
18.432
24.576
36.864
—
—
22.5792
33.8688
—
—
96 kHz
—
—
24.576
36.864
—
—
176.4 kHz
22.5792
33.8688
—
—
—
192 kHz
24.576
36.864
—
—
—
32 kHz
—
—
44.1 kHz
—
48 kHz
—
88.2 kHz
DSD mode (see Note 11)
44.1 kHz
† Only master mode
NOTES: 10. Modulator is running at 128 fS
11. Modulator is running at 64 fS
12. Modulator is running at 32 fS
VCC / VDD
—
16.9344 for 384 fS, 11.2896 for 256 fS
4.4 V / 2.2 V
4V/2V
3.6 V / 1.8 V
Reset
Reset Removal
Internal Reset
1024 System Clock + 1/fS(max)
System Clock
Figure 33. Internal Power-On Reset Timing
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19
PCM1804
SLES022A – DECEMBER 2001
PRINCIPLES OF OPERATION
RST
RST Pulse Width (tRST) = 40 ns (min)
tRST
Reset
Reset Removal
Internal Reset
1/fS (max)
System Clock
Figure 34. External Reset Timing
Power ON
RST ON
Internal Reset
Reset Removal
READY / OPERATION
RESET
1116 / fS
Data (A)
Zero Data
Converted Data (B)
NOTES: A. In case of DSD mode, DSDL is also controlled like DSDR.
B. The HPF transient response appears initially.
Figure 35. ADC Digital Output for Power-On Reset and RST Control
audio data interface
The PCM1804 interfaces the audio system through BCK/DSDL (pin 16), LRCK/DSDBCK (pin 17), and
DATA/DSDR (pin 15). The PCM1804 needs RST = low when in the interface mode and/or the data format are
changed.
interface mode
The PCM1804 supports master mode and slave mode as interface modes, which are selected by S/M (pin 8)
as shown in Table 4. In master mode, the PCM1804 provides the timing of the serial audio data communications
between the PCM1804 and the digital audio processor or external circuit. While in slave mode, the PCM1804
receives the timing of data transfer from an external controller. Slave mode is not available for DSD.
Table 4. Interface Mode
20
S/M
MODE
Low
Master mode
High
Slave mode
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PCM1804
SLES022A – DECEMBER 2001
PRINCIPLES OF OPERATION
data format
The PCM1804 supports four audio data formats in both of master and slave mode, and these data formats are
selected by the FMT0 (pin 6) and FMT1 (pin 7) as shown in Table 5.
Table 5. Data Format
FMT1
FMT0
FORMAT
MASTER
SLAVE
Low
Low
Yes
High
PCM, Left justified, 24 bit.
PCM, I2S, 24 bit.
Yes
Low
Yes
Yes
High
Low
PCM, Standard, 24 bit
Yes
Yes
High
High
DSD
Yes
—
interface timing for PCM
Figure 36 through Figure 38 illustrate the interface timing for PCM.
(1) Left-Justified Data Format; L-Channel = High, R-Channel = Low
1/fS
LRCK
L-Channel
R-Channel
BCK
DATA
1 2 3
22 23 24
1 2 3
22 23 24
1 2
(2) I2S Data Format; L-Channel = Low, R-Channel = High
1/fS
L-Channel
LRCK
R-Channel
BCK
1 2 3
DATA
22 23 24
1 2 3
22 23 24
1 2
(3) Standard Data Format; L-Channel = High, R-Channel = Low
1/fS
L-Channel
LRCK
R-Channel
BCK
DATA
22 23 24
1 2 3
22 23 24
1 2 3
22 23 24
NOTE: LRCK and BCK work as outputs at master mode, inputs at slave mode, respectively.
Figure 36. Audio Data Format for PCM
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21
PCM1804
SLES022A – DECEMBER 2001
PRINCIPLES OF OPERATION
interface timing for PCM (continued)
t(LRCP)
0.5 VDD
LRCK
tw(BCKH)
tw(BCKL)
t(CKLR)
0.5 VDD
BCK
t(BCKP)
t(CKDO)
t(LRDO)
DATA
0.5 VDD
PARAMETERS
MIN
BCK period, t(BCKP)
TYP
MAX
UNIT
1/(64 fS)
BCK pulse width high, tw(BCKH)
32
ns
BCK pulse width low, tw(BCKL)
32
ns
Delay time BCK falling edge to LRCK valid, t(CKLR)
–5
LRCK period, t(LRCP)
15
ns
1/fS
Delay time BCK falling edge to DATA valid, t(CKDO)
–5
15
ns
Delay time LRCK edge to DATA valid, t(LRDO)
–5
15
ns
Rising time of all signals, tr
10
ns
Falling time of all signals, tf
10
ns
NOTES: A. Rising and falling time is measured from 10% to 90% of IN/OUT signals swing.
B. Load capacitance of all signals are 10 pF.
C. t(BCKP) is fixed at 1/(64 fS) in case of master mode.
Figure 37. Audio Data Interface Timing for PCM (Master Mode: LRCK and BCK Work as Outputs)
22
www.ti.com
PCM1804
SLES022A – DECEMBER 2001
PRINCIPLES OF OPERATION
interface timing for PCM (continued)
t(LRCP)
1.4 V
LRCK
tw(BCKH)
tw(BCKL)
t(LRHD)
t(LRSU)
1.4 V
BCK
t(BCKP)
t(CKDO)
t(LRDO)
0.5 VDD
DATA
PARAMETERS
BCK period, t(BCKP)
MIN
TYP
MAX
1/(64 fS)
1/(64 fS)
1/(48 fS)
UNIT
BCK pulse width high, tw(BCKH)
32
ns
BCK pulse width low, tw(BCKL)
32
ns
LRCK setup time to BCK rising edge, t(LRSU)
12
ns
LRCK hold time to BCK rising edge, t(LRHD)
12
LRCK period, t(LRCP)
ns
1/fS
Delay time BCK falling edge to DATA valid, t(CKDO)
5
25
ns
Delay time LRCK edge to DATA valid, t(LRDO)
5
25
ns
Rising time of all signals, tr
10
ns
Falling time of all signals, tf
10
ns
NOTES: A. Rising and falling time is measured from 10% to 90% of IN/OUT signals swing.
B. Load capacitance of DATA/DSDR signal is 10 pF.
Figure 38. Audio Data Interface Timing for PCM (Slave Mode: LRCK and BCK Work as Inputs)
interface timing for DSD
Figure 39 and Figure 40 illustrate the interface timing for DSD.
DSDBCK
DSDL
Dn–3
Dn–2
Dn–1
Dn
Dn+1
Dn+2
Dn+3
DSDR
Dn–3
Dn–2
Dn–1
Dn
Dn+1
Dn+2
Dn+3
Figure 39. Audio Data Format
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23
PCM1804
SLES022A – DECEMBER 2001
PRINCIPLES OF OPERATION
interface timing for DSD (continued)
tw(BCKH)
tw(BCKL)
t(CKDO)
DSDBCK
0.5 VDD
t(BCKP)
DSDL
DSDR
0.5 VDD
PARAMETERS
MIN
TYP
MAX
UNIT
DSDBCK period, t(BCKP)
354.308
ns
DSDBCK pulse width high, tw(BCKH)
177.154
ns
DSDBCK pulse width low, tw(BCKL)
177.154
Delay time DSDBCK falling edge to DSDL, DSDR valid, t(CKDO)
–5
ns
15
ns
Rising time of all signals, tr
10
ns
Falling time of all signals, tf
10
ns
NOTES: A. Rising and falling time is measured from 10% to 90% of IN/OUT signals swing.
B. Load capacitance of DSDBCK/DSDL/DSDR signal is 10 pF.
Figure 40. Audio Data Interface Timing for DSD (Mast Mode Only)
synchronization with digital audio system for PCM
In slave mode, the PCM1804 operates under LRCK synchronized with the system clock SCKI. The PCM1804
does not need specific phase relationship between LRCK and SCKI, but does require the synchronization of
LRCK and SCKI.
If the relationship between LRCK and SCKI changes more than ±6 BCK during one sample period due to LRCK
or SCKI jitter, internal operation of the ADC halts within 1/fS and digital output is forced into BPZ code until
resynchronization between LRCK and SCKI is completed.
In case of changes less than ±5 BCK, resynchronization does not occur and above digital output control and
discontinuity does not occur.
Figure 41 illustrates ADC digital output for loss of synchronization and resynchronization. During undefined
data, it may generate some noise in the audio signal. Also, the transitions of normal to undefined data and
undefined or zero data to normal make a discontinuity of data on the digital output. This may generate noise
in the audio signal. In master mode, synchronization loss never occurs.
HPF (low-cut filter) bypass control for PCM
The built-in function for dc component rejection can be bypassed by BYPAS (pin 12) control. In bypass mode,
the dc component of the input analog signal and the internal dc offset are also converted and output in the digital
output data.
Table 6. HPF Bypass Control
24
BYPASS
LPF (HIGH-PASS FILTER) MODE
Low
Normal (dc cut) mode
High
Bypass (through) mode
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PCM1804
SLES022A – DECEMBER 2001
PRINCIPLES OF OPERATION
overflow flag for PCM
The PCM1804 has two overflow flag pins, OVFR (pin 20) and OVFL (pin 21). The pins go to high as soon as
the analog input goes across the full-scale range. The high level is held for 1.016 s at maximum, and returns
to low if the analog input does not go across the full-scale range for the period.
Synchronization Lost
State of
Synchronization
SYNCHRONOUS
Resynchronization
ASYNCHRONOUS
1 / fS
Data (A)
Normal Data
Undefined
Data
SYNCHRONOUS
90 / fS
Zero Data
Converted Data (B)
NOTES: A. Applies only for slave mode, the loss of synchronization never occurs in master mode.
B. The HPF transient response appears initially.
Figure 41. ADC Digital Output for Lost of Synchronization and Resynchronization
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25
PCM1804
SLES022A – DECEMBER 2001
PRINCIPLES OF OPERATION
typical circuit connection diagram
Figure 42 illustrates a typical circuit connection diagram in the PCM data format operation.
PCM1804
C1
+ 1
2
C3
+ 3
4
+
L-Channel In
5
–
C2
28 +
VREFL
VREFR
AGNDL
AGNDR
VCOML
VCOMR
VINL+
27
C4
26 +
VINR+
VINR–
FMT0
AGND
FMT1
VCC
8
10
Oversampling
Ratio [2:0]
11
12
HPF Bypass
13
3.3 V
C5
+ 14
C6
22
5V
+
21
S/M
OVFL
OSR0
OVFR
OSR1
RST
OSR2
SCKI
20
9
Control
R-Channel In
–
23
7
Master/Slave
+
24
VINL–
6
Format [1:0]
25
Overflow
19
Reset
18
System Clock
17
BYPAS
LRCK/DSDBCK
L/R Clock
16
DGND
BCK/DSDL
Audio Data
Processor
Data Clock
15
VDD
DATA/DSDR
Data Out
NOTES: A. C1, C2, C5, and C6: Bypass capacitor 0.1-µF ceramic and 10-µF tantalum, depends on layout and power supply.
B. C3, C4: Bypass capacitor 0.1-µF tantalum, depends on layout and power supply.
Figure 42. Typical Circuit Connection Diagram at PCM
26
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PCM1804
SLES022A – DECEMBER 2001
PRINCIPLES OF OPERATION
typical circuit connection diagram (continued)
Figure 43 illustrates a typical circuit connection diagram in the DSD data format operation.
PCM1804
C1
+ 1
2
C3
+ 3
4
+
L-Channel In
5
–
C2
28 +
VREFL
VREFR
AGNDL
AGNDR
VCOML
VCOMR
VINL+
27
C4
26 +
VINR+
VINR–
FMT0
AGND
FMT1
VCC
8
10
Oversampling
Ratio [2:0]
11
12
HPF Bypass
13
3.3 V
C5
+ 14
C6
22
5V
+
21
S/M
OVFL
OSR0
OVFR
OSR1
RST
OSR2
SCKI
20
9
Control
R-Channel In
–
23
7
Master/Slave
+
24
VINL–
6
Format [1:0]
25
Overflow
19
Reset
18
System Clock
17
BYPAS
LRCK/DSDBCK
Data Clock
16
DGND
BCK/DSDL
Audio Data
Processor
L-Channel Data Out
15
VDD
DATA/DSDR
R-Channel Data Out
NOTES: A. C1, C2, C5, and C6: Bypass capacitor 0.1-µF ceramic and 10-µF tantalum, depends on layout and power supply.
B. C3, C4: Bypass capacitor 0.1-µF tantalum, depends on layout and power supply.
Figure 43. Typical Circuit Connection Diagram at DSD
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27
PCM1804
SLES022A – DECEMBER 2001
APPLICATION INFORMATION
board design and layout considerations
VCC, VDD pins
The digital and analog power supply lines to the PCM1804 should be bypassed to the corresponding ground
pins with 0.1-µF ceramic and 10-µF tantalum capacitors placed as close to the pins as possible to maximize
the dynamic performance of the ADC. Although the PCM1804 has two power lines to maximize the potential
of dynamic performance, using one common power supply is recommended to avoid unexpected power supply
trouble like latch-up or power-supply sequence.
VIN pins
Use 100-pF ceramic capacitors between VINL+, VINL–, VINR+, VINR–, and AGND, and 0.022-µF ceramic
capacitors between VINL+ and VINL–, VINR+, and VINR– to remove higher-frequency noise at the delta-sigma
input section.
VREFX, VCOMX inputs
Use 0.1-µF ceramic and 10-µF tantalum capacitors between VREFL, VREFR, and corresponding AGNDx, to
insure low-source impedance at ADC references. Use 0.1-µF tantalum capacitors between VCOML, VCOMR and
corresponding AGNDx to insure low-source impedance of common voltage. These capacitors should be
located as close as possible to the VREFL, VREFR, VCOML, and VCOMR pins to reduce dynamic errors on
references and common voltage. The dc voltage level of these pins is 2.5 V.
DATA/DSDR, BCK/DSDL, and LRCK/DSDBCK pins
The DATA/DSDR, BCK/DSDL, and LRCK/DSDBCK pins in master mode have large load drive capability.
Locating the buffer near the PCM1804 and minimizing the load capacitance, minimizes the digital analog
crosstalk and maximizes the dynamic performance of the ADC.
system clock
The quality of the system clock may influence dynamic performance, as the PCM1804 operates based on
system clock. In that case, it may be required to consider the system clock duty, jitter, and the time difference
between system clock transition and BCK/DSDL or LRCK/DSDBCK transition in slave mode.
reset control
If capacitors larger than 10 µF are used on VREFL and VREFR, the external reset control with a delay time
corresponding to the VREFL and VREFR response is required. Also, it works as a power-down control.
application circuit for single-end input
An application circuit for a single-end input circuit is shown in Figure 44. The maximum signal input voltage and
differential gain of this circuit is designed as Vinmax = 8.28 Vpp, A = 0.3. Differential gain (Ad) is given by
R3/R1(R4/R2) as normal inverted gain amp. Resistor R5 (R6) in the feedback loop gives low-impedance drive
operation and noise filtering for analog input of the PCM1804. The circuit technique R5 (R6) is recommended.
28
www.ti.com
PCM1804
SLES022A – DECEMBER 2001
APPLICATION INFORMATION
R3 = 909 Ω
100 pF (See Note)
4.99 kΩ
4.99 kΩ
Analog In
_
10 µ R1 = 3 kΩ
PCM1804
R5 = 51.1 Ω
_
+
+
VIN–
+
100 pF
OPA2134 1/2
OPA2134 1/2
VCOM
R4 = 909 Ω
0.1 µF
0.022 µF
100 pF (See Note)
10 µ R2 = 3 kΩ
_
+
R6 = 51.1 Ω
VIN+
+
100 pF
OPA2134 1/2
NOTE: 3300 pF is recommended if the input signal level is more than –6 dB of FS at 100 kHz is applied in DSD mode.
Figure 44. Application Circuit for Single-Ended Input Circuit (PCM)
VIN+
∆Σ Modulator
VIN–
_
BGR
VCOM
VREF
+
_
+
Figure 45. Equivalent Circuit of Internal Reference (VCOM, VREF)
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29
MECHANICAL DATA
MSSO002D – JANUARY 1995 – REVISED SEPTEMBER 2000
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,15 NOM
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /D 09/00
NOTES: A.
B.
C.
D.
30
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15 mm.
Falls within JEDEC MO-150
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