SHC298 SHC298A ® Monolithic SAMPLE/HOLD AMPLIFIER FEATURES DESCRIPTION ● 12-BIT THROUGHPUT ACCURACY ● LESS THAN 10µs ACQUISITION TIME The SHC298 and SHC298A are high-performance monolithic sample/hold amplifiers featuring high DC accuracy with fast acquisition times and a low droop rate. Dynamic performance and holding performance can be optimized with proper selection of the external holding capacitor. With a 1000pF holding capacitor, 12-bit accuracy can be achieved with a 6µs acquisition time. Droop rates less than 5mV/min are possible with a 1µF holding capacitor. ● WIDEBAND NOISE LESS THAN 20µVrms ● RELIABLE MONOLITHIC CONSTRUCTION ● 1010Ω INPUT RESISTANCE ● TTL-CMOS-COMPATIBLE LOGIC INPUT These sample/holds will operate over a wide supply voltage ranging from ±5V to ±18V with very little change in performance. A separate Offset Adjust pin is used to adjust the offset in either the Sample on the Hold modes. The fully differential logic inputs have low input current, and are compatible with TTL, 5V CMOS, and CMOS logic families. Offset Adjust 2 30kΩ A2 Analog Input Logic 3 Output A1 150Ω 8 Logic 7 Reference 5 C1 Mode Control (S/H) Input 6 Hold Capacitor The SHC298AM is available in a hermetically sealed 8-pin TO-99 package and is specified over a temperature range from –25°C to +85°C. The SHC298JP and SHC298JU are 8-pin plastic DIP and SOIC packaged parts specified over 0°C to +70°C. The SHC298AJP, specified over 0°C to +70°C, is available in an 8-pin plastic DIP. The SHC298A grade features improved gain and offset error, improved drift over temperature, and faster acquisition time. The SHC298 family is a price-performance bargain. It is well suited for use with several 12-bit A/D converters in data acquisition systems, data distribution systems, and analog delay circuits. International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1977 Burr-Brown Corporation PDS-373E Printed in U.S.A. August, 1996 SPECIFICATIONS ELECTRICAL At TJ = +25°C, ±15V supplies, 1000pF holding capacitor, –11.5V ≤ VIN ≤ +11.5, RL = 10kΩ, Logic Reference Voltage = 0V, and Logic Voltage = 2.5 V, unless otherwise noted. SHC298AM, JP, JU PARAMETER MIN ANALOG INPUT Resistance Bias Current(1) SHC298AJP TYP MAX 1010 10 50 MIN TYP MAX UNITS ✻ ✻ 25 Ω nA DIGITAL INPUT Pin 7 Pin 8 Circuit State Mode Control Truth Table 0V 0V +2.4V +0.8V +2.4V +0.8V +2.8V +2.8V Sample (Track) Hold Hold Sample (Track) Mode Control and Mode Control Reference Input Current Differential Logic Threshold 0.8 1.4 µA V 10 2.4 TRANSFER CHARACTERISTICS ACCURACY (+25°C) Gain Gain Error Input Voltage Offset (adjust to zero)(1) Droop Rate(1) Power Supply Rejection +1 ±0.004 ±2 ±30 ±25 ACCURACY DRIFT Gain Drift Input Offset Drift Droop Rate at TJ = +85°C 3 15 10 DYNAMIC CHARACTERISTICS Aperture Time : Negative Input Step Positive Input Step Acquisition Time (C = 1000pF): to ±0.1%, 10V Step Sample/Hold Transient: Peak Amplitude Settling to 1mV Feedthrough (Response to 10V Input Step) ✻ ±0.001 ±1 ✻ ✻ ±0.010 ±7 ±100 4 70 1 ✻ ✻ ✻ ✻ 4 ✻ ✻ ±0.004 200 150 5 160 1 ±0.007 ±0.005 ±2 ✻ 2 25 6 V/V % mV µV/ms µV/V ppm/°C µV/°C mV/ms ns ns µs mV µs % of 20V OUTPUT ANALOG OUTPUT Voltage Range Current Range Impedance (in Hold Mode) POWER SUPPLY Rate Voltage Range Current(1) ±11.5 ±2 0.5 ✻ ✻ ✻ 4 ±4.5 ✻ Ω ✻ 15 ±5 V mA ±18 ±6.5 ✻ ✻ ✻ ✻ VDC VDC mA ✻ Same as specifications for SHC298AM, JP, JU. NOTES: (1) These parameters guaranteed over a supply voltage range of ±5V to = ±18V. (2) Charge offset is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1pF, for instance, will create an additional 0.5mV step with a 5V logic swing and a 0.01µF hold capacitor. Magnitude of the charge offset is inversely proportional to hold capacitor value. ® SHC298/298A 2 PIN CONFIGURATIONS Top View TO-99 Top View Plastic DIP/Small Outline Tab 8 +VCC 1 Mode Control (S/H) Input Logic 7 Mode Control Reference Offset Adjust +VCC 1kΩ 2 6 5 Output 3 Mode Control Input 2 7 Mode Control Reference Analog Input 3 6 Hold Capacitor –VCC 4 5 Output 1 Offset Adjust Logic Hold Cap 24kΩ Analog Input 8 +VCC 4 –VCC ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDERING INFORMATION Supply Voltage .................................................................................. ±18V Power Dissipation (Package Limitation) ........................................ 500mV Junction Temperature, TJ MAX AM ................................................................................................ 125°C JP, JU .......................................................................................... 100°C Operating Temperature Range ....................................... –25°C to +85°C Storage Temperature Range ........................................ –65°C to +150°C Input Voltage ....................................................... Equal to Supply Voltage Logic-to-Logic Reference Differential Voltage(1) ..................... +7V, –30V Output Short Circuit Duration ...................................................... Indefinite Hold Capacitor Short Circuit Duration ................................................. 10s Lead Temperature (soldering, 10s) ................................................. 300°C PRODUCT SHC298AM SHC298JP SHC298JU SHC298AJP PACKAGE PACKAGE DRAWING NUMBER(1) TEMPERATURE RANGE TO-99 8-Pin Plastic DIP 8-Lead SOIC 8-Pin Plastic DIP 001 006 182 006 –25°C to +85°C 0°C to +70°C 0°C to +70°C 0°C to +70°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. NOTE: (1) Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below the positive supply and 3V above the negative supply. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 SHC298/298A TYPICAL PERFORMANCE CURVES At TJ = +25°C, ±15V supplies, 1000pF holding capacitor, –11.5V ≤ VIN ≤ +11.5, RL = 10kΩ, Logic Reference Voltage = 0V, and Logic Voltage = 2.5 V, unless otherwise noted. CHARGE OFFSET APERTURE TIME 100 500 +VCC = –VCC = 15V ∆VIN = 10V 10 Hold Step (mV) Time (ns) VIN = 0V TJ = 25°C ∆VOUT ≤ mV 400 300 Negative Input Step 200 Positive Input Step 1 0.1 100 0.01 0 –50 –25 0 25 50 75 100 125 0.0001 150 0.001 0.01 0.1 1 Hold Capacitor (µF) Junction Temperature (°C) SAMPLE-TO-HOLD TRANSIENT SETTLING TIME OUTPUT DROOP RATE 100 2 +VCC = –VCC = 15V 1.8 Settling to 1mV TJ = 125°C 1.6 10–1 ∆V/∆T (V) Time (ns) 1.4 1.2 1 0.8 0.6 TJ = 70°C 10–2 10–3 0.4 TJ = 25°C TJ = 0°C 0.2 10–4 0 –50 –25 0 25 50 75 100 125 0.0001 150 0.001 0.01 0.1 1 Hold Capacitor (µF) Junction Temperature (°C) OUTPUT NOISE ACQUISITION TIME 160 1 VIN = 0V to ±10V TJ = 25°C 140 Noise (nV/√Hz) 120 Time (µs) 10 0.1% 100 “Hold” Mode 100 80 60 40 0.01% “Sample” Mode 20 0 1000 0.001 0.01 0.1 10 1 ® SHC298/298A 100 1k Frequency (Hz) Hold Capacitor (µF) 4 10k 100k TYPICAL PERFORMANCE CURVES (CONT) At TJ = +25°C, ±15V supplies, 1000pF holding capacitor, –11.5V ≤ VIN ≤ +11.5, RL = 10kΩ, Logic Reference Voltage = 0V, and Logic Voltage = 2.5 V, unless otherwise noted. DYNAMIC SAMPLING ERROR GAIN ERROR 100 0.3 +VCC = –VCC = 15V Error (mV) 10 Input-Output Voltage (mV) TJ = 25°C 1000pF Hold Capacitor 0.01µF 1 0.1µF 0.1 3000pF TJ = 25°C RL = 10kΩ Sample Mode 0.2 0.1 0 –0.1 Slope ≈ 0.0007% –0.2 1µF 0.01 –0.3 0.1 1 10 100 –15 1000 –5 –10 10 15 160 CH = 0.01µF TJ = 25°C 1.2 TJ = 25°C +VCC = –VCC = 15V VOUT = 0V 140 0.4 Rejection Ratio (dB) 0.8 Hold Step (mV) 5 POWER SUPPLY REJECTION CHARGE OFFSET 1.6 TJ = –55°C 0 –0.4 –0.8 0 Output Voltage (V) Input Slew Rate (V/ms) TJ = 125°C TJ = 25°C 120 100 Positive Supply 80 Negative Supply 60 40 20 –1.2 –1.6 0 –15 –5 –10 0 5 10 15 100 1k Input Voltage (V) 10k 100k 1M Frequency (Hz) INPUT BIAS CURRENT FEEDTHROUGH REJECTION RATIO 25 130 20 120 15 110 Rejection Ratio (dB) Current (nA) +VCC = –VCC = 15V 10 5 0 –5 TJ = 25°C 100 CH = 0.01µF 90 CH = 1000pF 80 70 60 –10 –15 –50 VIN = 10Vp-p CH ≥ 0.1µF 50 –25 –0 25 50 75 100 125 150 10 Junction Temperature (°C) 100 1k 10k 100k 1M Frequency (Hz) ® 5 SHC298/298A TYPICAL PERFORMANCE CURVES (CONT) 40 30 CH = 0.01µF 20 CH ≥ 0.1µF CH = 0 10 0 1k 10k 100k 1M Hold Step (mV) CH = 1000pF Input to Output Phase Delay (°) Gain Input to Output (dB) At TJ = +25°C, ±15V supplies, 1000pF holding capacitor, –11.5V ≤ VIN ≤ +11.5, RL = 10kΩ, Logic Reference Voltage = 0V, and Logic Voltage = 2.5 V, unless otherwise noted. PHASE AND GAIN (Input to Output, Small Signal) CHARGE OFFSET 80 5 3.5 CH = 0 CH = 0.01µF 70 0 3 TJ = 25°C CH = 1000pF VIN = 0V 60 –5 2.5 CH = 0.01µF 50 –10 2 1.5 1 0.5 0 –0.5 10M 0.01 0.1 Frequency (Hz) 1 10 100 Logic Slew Rate (V/µs) DISCUSSION OF SPECIFICATIONS THROUGHPUT NONLINEARITY ACQUISITION TIME Throughput nonlinearity is defined as total Hold mode, nonadjustable, input to output error caused by charge offset, gain nonlinearity, 1ms of droop, feedthrough, and thermal transients. It is the inaccuracy due to these errors which cannot be corrected by offset and gain adjustments. Throughput nonlinearity is tested with a 1000pF holding capacitor, 10V input changes, 10µs acquisition time, and 1ms Hold time (see Figure 1). Acquisition Time is the time required for the sample/hold output to settle within a given error band of its final value when the mode control is switched from Hold to Sample. Control Signal Sample Hold GAIN ACCURACY Sample Time Gain Accuracy is the difference between input and output voltage (when in the Sample mode) due to amplifier gain errors. Input Voltage DROOP RATE Droop Rate is the voltage decay at the output when in the Hold mode due to storage capacitor, FET switch leakage currents, and output amplifier bias current. Time FEEDTHROUGH Feedthrough is the amount of the input voltage change that appears at the output when the amplifier is in the Hold mode. Output Voltage APERTURE TIME Aperture Time is the time required to switch from Sample to Hold. The time is measured from the 50% point of the mode control transition to the time at which the output stops tracking the input. Acquisition Time Gain Error Actual Aperture Time Ideal Throughput Error Time Offset Error FIGURE 1. Sample/Hold Errors. ® SHC298/298A 6 CHARGE OFFSET With a 0.1µF storage capacitor, the output may be held 10 seconds with less than 0.1% error. With a 1µF storage capacitor, the output may be held more than 15 minutes with less than 1% error. Charge Offset is the offset that results from the charge coupled through the gate capacitance of the switching FET. This charge is coupled into the storage capacitor when the FET is switched to the “hold” mode. CAPACITIVE LOADING SHC298 is sensitive to capacitive loading on the output and may oscillate. When driving long lines, a buffer should be used. OPERATING INSTRUCTIONS EXTERNAL CAPACITOR SELECTION Capacitors with high insulation resistance and low dielectric absorption, such as Teflon®, polystyrene or polypropylene units, should be used as storage elements (polystyrene should not be used above +85°C). Care should be taken in the printed circuit layout to minimize AC and DC leakage currents from the capacitor to reduce charge offset and droop errors. HIGH SPEED DATA ACQUISITION The minimum sample time for one channel in a data acquisition system is usually considered to be the acquisition time of the sample/hold plus the conversion time of the analog-todigital converter. If two or more sample/holds are used with a high-speed multiplexer, the acquisition time of the sample/ hold can be virtually eliminated. While the first channel is in hold and switched on to the ADC, the multiplexer may be addressed to the next channel. The second sample/hold will have acquired this data by the time the conversion is complete. Then, the sample/holds reverse roles and another channel is addressed (see Figure 5). For low-level systems, and instrumentation amplifier and double-ended multiplexer may be connected to the sample/hold inputs. The settling time of the multiplexer, instrumentation amplifier, and sample/hold can be eliminated from the channel conversion time as before. The value of the external capacitor determines the droop, charge offset and acquisition time of the Sample/Hold. Both droop and charge offset will vary linearly with capacitance from the values given in the specification table for a 0.001µF capacitor. With a capacitor of 0.01µF, the droop will reduce to approximately 2.5µV/ms and the charge offset to approximately 1.5mV. The behavior of acquisition time with changes in external capacitance is shown in the Typical Performance Curves. OFFSET ADJUSTMENT The offset should be adjusted with the input grounded. During the adjustment, the sample/hold should be switching continuously between the Sample and the Hold mode. The error should then be adjusted to zero when the unit is in the Hold mode. In this way, charge offset as well as amplifier offset will be adjusted. When a 0.001µF capacitor is used, it will not be possible to adjust the full offset error at the sample/hold. It should be adjusted elsewhere in the system. –15VDC 0.005µF Storage 0.1µF To A/D Converter Analog Inputs 4 6 3 5 SHC298 8 Analog Multiplexer APPLICATIONS DATA ACQUISITION The SHC298 may be used to hold data for conversion with an analog-to-digital converter or used to provide Pulse Amplitude Modulation (PAM) data output (see Figures 2 and 3). 7 2 1 Mode Control PAM Output 0.1µF 1kΩ 24kΩ +15VDC FIGURE 2. Data Acquisition. DATA DISTRIBUTION The SHC298 may be used to hold the output of a digital-toanalog converter whose digital inputs are multiplexed (see Figure 4). PAM Output Actual Input TEST SYSTEMS The SHC298 is also well suited for use in test systems to acquire and hold data transients for human operators or for the other parts of the test system such as comparators, digital voltmeters, etc. Mode Control Hold FIGURE 3. PAM Output. ®Teflon, DuPont de Nemours ® 7 SHC298/298A 1000pF Storage Capacitor 0.1µF –15VDC 6 4 6 3 5 SHC298 Analog Output 3 SHC298 5 1 Channel 1 8 7 2 Digital Output 1 Offset Adjust Ch1 Ch2 0.1µF (1) 1kΩ 24kΩ MUX B12 6 4 Analog Address Input 6 3 5 SHC298 D/A Converter 3 SHC298 5 2 High Speed Switch Channel 2 8 7 2 1 8 Mode Control FIGURE 5. “Ping-Pong” Sample Holds. +15VDC Additional SHC298 Units –15VDC 4 6 3 5 SHC298 Channel N 8 7 2 1 Mode Control Logic Digital Inputs A/D Converter ChN –15VDC Digital Inputs 1000pF (0) +15VDC B1 B2 8 +15VDC FIGURE 4. Data Distribution. ® SHC298/298A 8