® SHC605 SHC6 05 DEMO BOARD AVAILABLE High-Speed Operational TRACK-AND-HOLD AMPLIFIER FEATURES DESCRIPTION ● VERY GOOD SPURIOUS FREE DYNAMIC RANGE: 90dB at 1MHz FIN and 20MSPS 86dB at 2MHz FIN and 20MSPS 77dB at 5MHz FIN and 20MSPS ● LOW ACQUISITION TIME: 30ns to 0.01% The SHC605 is a monolithic high-speed, high accuracy track-and-hold amplifier. It combines fast acquisition and low distortion to provide a complete solution for a wide range of sampling applications. Its new proprietary closed-loop architecture provides a singlechip solution to many data acquisition problems formerly requiring more than one device. Noninverting, inverting, and differential gain configurations are easy to apply with the SHC605. An on-board logic reference circuit makes the SHC605 compatible with both single-ended and differential ECL or TTL clock inputs. An internal track-mode lockout circuit allows edge-triggered operation in data acquisition systems. The SHC605 is available in a SO-16 surface-mount package specified for the –40C to +85C industrial temperature range. ● LOW DROOP RATE: 8mV/µs max TMIN to TMAX ● LOW POWER CONSUMPTION: 335mW ● EXTREMELY VERSATILE ARCHITECTURE: Noninverting, Inverting, and Differential Gains ● LOGIC FLEXIBILITY: TTL and ECL Compatible ● SMALL PACKAGE: SO-16 ● EXTENDED TEMPERATURE SPECS: –40°C to +85°C +VS 2, 3 –VS 15, 16 C1 APPLICATIONS ● A/D CONVERTER FRONT ENDS ● MULTIPLE CHANNEL SIMULTANEOUS SAMPLING ● IMPROVING FLASH ADC PERFORMANCE ● PEAK DETECTORS ● DAC DEGLITCHING –IN +IN 8 9 1 C2 Select 10 4 DGND International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1992 Burr-Brown Corporation 12 11 Vout AGND 5, 6, 7 14 13 Hold Thresh/ Hold Lock Lock • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 PDS-1165D Printed in U.S.A. July, 1993 SPECIFICATIONS ELECTRICAL At TA = +25°C, ±VS = ±5V, G = +1V/V, RL = 100Ω, CL = 5pF, and ECL Hold/Hold Inputs, unless otherwise noted. SHC605AU PARAMETER CONDITION DC INPUT PARAMETERS Offset Voltage Power Supply Rejection Input Bias Current Input Offset Current Common-Mode Input Range Common-Mode Rejection Differential Input Impedance Common-Mode Input Impedance Open-Loop Voltage Gain OUTPUT Voltage Output Current Output Short Circuit Current Output Resistance, Closed-Loop: Track-Mode Hold-Mode DIGITAL INPUTS/OUTPUTS TTL Input Levels(1) VIL VIH Single-Ended ECL Input Levels VIL VIH Common-Mode Input Voltages (2) Differential Input Voltages Digital Input Currents IIL, Lock/Lock Inputs Only IIL, Hold/Hold Inputs Only IIH, Lock/Lock Inputs Only IIH, Hold/Hold Inputs Only Threshold Voltage Output(3) TTL(4) ECL(5) TRACK-MODE RESPONSE Closed-Loop Bandwidth Full Power Response Slew Rate(6) Acquisition Time to 1%(7) 0.1% 0.012% 0.012% Input Voltage Noise Input Bias Current Noise Differential Gain Differential Phase Spurious Free Dynamic Range (5MHz) (10MHz) TEMP RANGE Full +25°C Full Full Full Full Full Full +25°C VS = ±4.5 to ±5.5V VCM = 0V VCM = 0V VCM = ±2VDC VO = ±2V, RL = 100Ω RL = 50Ω Full +25°C Full Full DC DC Full Full Hold Input Only Logic “LO” Logic “HI” Hold/Hold and Lock/Lock Inputs Logic “LO” Logic “HI” Hold/Hold Lock/Lock Hold/Hold and Lock/Lock Inputs ECL Logic “LO”, VIL = –1.60V ECL or TTL Logic “LO” Logic “HI”, VIH = –1.0V MIN 60 ±2.0 ±2.0 ±40 ±40 TYP MAX UNITS ±1 85 15 ±0.2 ±2.5 80 13||1 2||1 100 ±7.5 mV dB µA µA V dB kΩ||pF MΩ||pF dB ±2.5 ±80 ±60 ±140 V mA mA mA 0.0001 0.01 Ω Ω Full Full 0 +2.0 +1.0 +5.0 V V Full Full Full Full Full –1.80 –1.05 –3 –VS 0.2 –1.45 –0.80 +5 +3 5.0 V V V V V 5 –100 50 –10 µA µA µA µA 1.9 –1.10 V V Full Full Full Full –VS = –5.2V Gain = +1V/V Gain = +2V/V Gain = +5V/V Gain = +10V/V ±1V Input, –3dB Output G = +1, 2V Step 2V Step 2V Step 2V Step 4V Step 1MHz to 100MHz 1MHz to 100MHz 3.58MHz, VO = 0 to 0.7Vp–p 3.58MHz, VO = 0 to 0.7Vp–p VO = ±1V VO = ±1V 50 ±5 Full Full 1.1 –1.40 1.5 +25°C +25°C +25°C +25°C Full +25°C Full Full Full Full Full 100 200 75 20 10 32 200 200 15 23 30 40 2.5 2.5 0.005 0.005 140 120 83 73 25 35 45 60 MHz MHz MHz MHz MHz V/µs V/µs ns ns ns ns nV√Hz pA/√Hz % Degrees dBc dBc NOTE: (1) Select (Pin 10) connected to +VS for TTL threshold voltage on Pin 11. (2) Select (Pin 10) connected to –VS for ECL threshold voltage on Pin 11. (3) Output voltage on pin 11. (4) Pin 10 (Select) connected to +VS. (5) Pin 10 (Select) connected to –VS. (6) Slew rate is rate of change from 10% to 90% of a 2V output step. (7) Acquisition time includes hold-to-track delay switch time. (8) Hold noise is proportional to the time in the hold mode. For example, if the hold time is 25ns, the accumulated noise is 10µVrms. (9) This is the maximum length of time the SHC605 can remain in the hold mode and still maintain a linear droop rate. (10) Select (Pin 10) connected to +VS. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® SHC605 2 SPECIFICATIONS (CONT) ELECTRICAL At TA = +25°C, ±VS = ±5V, G = +1V/V, RL = 100Ω, CL = 5pF, and ECL Hold/Hold Inputs, unless otherwise noted. SHC605AU PARAMETER TRACK-TO-HOLD SWITCHING CONDITION TEMP RANGE Full Full +25°C Full Full Full Full VO = ±1V VO = ±1V VO = ±1V VO = ±1V VO = ±0.5 Full Full Full +25°C +25°C MAX 1.7 2.4 ±5 ±5 ±5 8 15 78 74 65 Full Full +25°C POWER SUPPLY Specified Operating Voltage Positive Supply Current(10) Negative Supply Current(10) Total Power Dissipation TEMPERATURE RANGE Specification Storage Thermal Resistance, θJA TYP UNITS VIN = 0V Aperture Delay Aperture Jitter Pedestal Offset over Temperature Transient Amplitude Settling Time to 1mV 100µV HOLD-MODE RESPONSE Spurious Free Dynamic Range (1MHz, 20MSPS) (2MHz, 20MSPS) (5MHz, 20MSPS) (10MHz, 20MSPS) (10MHz, 20MSPS) Hold Noise(8) Droop Rate Hold Time(9) Feedthrough Rejection (20MHz) MIN Ambient 15 90 86 77 60 72 400xtH ±1 ±8 2 85 Full Full Full Full ±4.50 Full –40 –55 Full ±20 ±25 ±5 34 33 335 ns ps rms mV mV mV ns ns dBc dBc dBc dBc dBc V/s rms mV/µs µs dB ±5.50 39 39 390 V mA mA mW +85 +150 °C °C °C/W 100 NOTE: (1) Select (Pin 10) connected to +VS for TTL threshold voltage on Pin 11. (2) Select (Pin 10) connected to –VS for ECL threshold voltage on Pin 11. (3) Output voltage on pin 11. (4) Pin 10 (Select) connected to +VS. (5) Pin 10 (Select) connected to –VS. (6) Slew rate is rate of change from 10% to 90% of a 2V output step. (7) Acquisition time includes hold-to-track delay switch time. (8) Hold noise is proportional to the time in the hold mode. For example, if the hold time is 25ns, the accumulated noise is 10µVrms. (9) This is the maximum length of time the SHC605 can remain in the hold mode and still maintain a linear droop rate. (10) Select (Pin 10) connected to +VS. ® 3 SHC605 PIN CONFIGURATION PIN DESCRIPTION U Package SO-16 +In 1 16 –VS +VS 2 15 –VS +VS 3 14 Lock DGND 4 13 Lock AGND 5 12 Hold AGND 6 11 Thresh/Hold AGND 7 10 Select –In 8 9 SHC605AU SO-16 Surface-Mount 265 Hold Lock Lock 15 16 –VS –VS ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TEMPERATURE RANGE –40°C to +85°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ® SHC605 12 13 14 Non-Inverting Input +5V Supply +5V Supply Digital Ground Analog Ground Analog Ground Analog Ground Inverting Input Output Voltage +5V Selects TTL; –5V Selects ECL Logic threshold for single-ended operation or complement Hold input for differential operation True Hold input Complement Lock Input True Lock input; Locks SHC605 in Hold-mode regardless of Hold/Hold Inputs –5V Supply –5V Supply This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. PACKAGE/ORDERING INFORMATION PACKAGE DESCRIPTION +In +VS +VS DGND AGND AGND AGND –In VOUT Select Thresh/Hold ELECTROSTATIC DISCHARGE SENSITIVITY Supply ............................................................................................. ±7VDC Input Voltage Range ............................................................................ ±5V Differential Input Voltage .................... ±5.5V (between +In and –In inputs) Storage Temperature Range .......................................... –40°C to +125°C Lead Temperature (soldering, SOIC 3s) ....................................... +260°C Output Short Circuit to Ground (+25°C) ................. Continuous to Ground Junction Temperture (Tj) ............................................................... +175°C PRODUCT SYMBOL 1 2 3 4 5 6 7 8 9 10 11 VOUT ABSOLUTE MAXIMUM RATINGS PACKAGE DRAWING NUMBER(1) PIN # 4 TYPICAL PERFORMANCE CURVES At TA = +25°C, ±VS = ±5V, G = +1V/V, RL = 100Ω, CL = 5pF, and ECL Hold/Hold Inputs, unless otherwise noted. CLOSED-LOOP GAIN = +1V/V vs FREQUENCY (Track Mode) OPEN-LOOP FREQUENCY RESPONSE (Track Mode) –45 80 Phase 60 –90 –135 40 20 0 0 Phase Margin ≈ 65° –1 Gain (dB) 100 Phase Shift (°) Open-Loop Voltage Gain (dB) 120 –180 Gain –4 –6 –20 –7 100 1k 10k 100k 1M 10M 100M 1G 1 10 100 1000 Frequency (Hz) Frequency (MHz) NON-INVERTING CLOSED-LOOP GAIN vs SMALL SIGNAL BANDWIDTH INVERTING CLOSED-LOOP GAIN vs SMALL SIGNAL BANDWIDTH 100 Small Signal Bandwidth (MHz) 200 Small Signal Bandwidth (MHz) –3 –5 –225 0 –2 150 100 50 80 60 40 20 0 0 +1 +2 +5 –1 +10 –2 –5 –10 Inverting Closed-Loop Gain (V/V) Non-Inverting Closed-Loop Gain (V/V) ACQUISITION TIME vs NON-INVERTING CLOSED-LOOP GAIN SNR vs INPUT FREQUENCY 150 75 125 100 70 0.1% SNR (dB) Acquisition Time (ns) 0.01% 75 1% 50 65 25 VOUT = 2.0Vpp 20MSPS 0 +1 +2 +5 60 +10 DC Inverting Closed-Loop Gain (V/V) 2.5 5 7.5 10 Input Frequency (MHz) ® 5 SHC605 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, ±VS = ±5V, G = +1V/V, RL = 100Ω, CL = 5pF, and ECL Hold/Hold Inputs, unless otherwise noted. LARGEST HARMONIC vs INPUT FREQUENCY (Track Mode) LARGEST HARMONIC vs INPUT FREQUENCY (Hold Mode) 100 90 95 85 VO = 2.0Vpp 20MSPS SFDR (dB) SFDR (dB) VOUT = 2.0Vpp 90 Gain = +1 85 Gain = +2 80 75 70 75 65 70 60 DC 2 4 6 8 10 DC 2 4 8 Input Frequency (MHz) FEEDTHROUGH REJECTION vs INPUT FREQUENCY POWER SUPPLY REJECTION vs SUPPLY RIPPLE FREQUENCY (Track Mode) 10 Power Supply Rejection (dB) 120 90 80 70 60 100 80 60 40 20 50 10 20 40 60 100 100 200 1000 10k Input Frequency (MHz) 100k 1M 10M 100M 75 100 Frequency (Hz) DROOP RATE vs TEMPERATURE PEDESTAL vs TEMPERATURE 2.5 0 2.0 2 Pedestal (mV) |Droop Rate (mV/µs)| 6 Input Frequency (MHz) 100 Feedthrough Rejection (dB) 80 1.5 1.0 0.5 4 6 8 0 10 –50 –25 0 25 50 75 100 –50 Temperature (°C) 0 25 50 Temperature (°C) ® SHC605 –25 6 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, ±VS = ±5V, G = +1V/V, RL = 100Ω, CL = 5pF, and ECL Hold/Hold Inputs, unless otherwise noted. HOLD-MODE DISTORTION AT 20MSPS, VIN = 2MHz HOLD-MODE DISTORTION AT 20MSPS, VIN = 5MHz 0 0 VOUT = 2Vpp RL = 100Ω VIN = 2MHz fT/H = 20MHz tTRACK = 35ns –40 –60 –80 VOUT = 2Vpp RL = 100Ω VIN = 5MHz fT/H = 20MHz tTRACK = 35ns –20 Amplitude (dB) Amplitude (dB) –20 2nd –100 –40 –60 2nd 3rd –80 –100 –120 –120 5 0 10 15 0 16 Frequency (MHz) HOLD-MODE DISTORTION AT 20MSPS, VIN = 10MHz 48 64 HOLD-MODE DISTORTION AT 20MSPS, VIN = 10MHz 0 0 VOUT = 1Vpp RL = 100Ω VIN = 10MHz fT/H = 20MHz tTRACK = 35ns –40 –60 2nd VOUT = 2Vpp RL = 100Ω VIN = 10MHz fT/H = 20MHz tTRACK = 35ns –20 Amplitude (dB) –20 Amplitude (dB) 32 Frequency (MHz) 3rd –80 –100 –40 2nd –60 3rd –80 –100 –120 –120 0 16 32 48 64 0 Frequency (MHz) 16 32 48 64 Frequency (MHz) ® 7 SHC605 TIMING DEFINITIONS Acquisition Time is the time it takes to reacquire the input signal when switching from the hold to track mode. This time interval starts at 50% of the clock transition and ends when the input signal is reacquired to within a specified accuracy at the output. This specification does not include the track-to-hold settling time. Feedthrough Rejection is a measure of the amount of the input signal that “feeds through” to the output while the device is in the hold mode. This specification is usually a function of frequency, with degradation at higher frequencies. Hold-to-Track Delay is the time from the track command to the point when the output begins changing to acquire a new signal. This delay is included in the SHC605’s specified acquisition time. Aperture Delay is a measure of the track-to-hold switch delay time. It is the difference between the analog input amplifier’s signal path delay and the digital track-to-hold switch delay. A positive delay indicates the digital switch delay is larger than the analog amplifier delay. Pedestal Offset is the error voltage step incurred at the output when the device is switched from the track to hold mode. Aperture Jitter is random variation in the aperture delay. This specification is measured in ps-rms and results in phase noise on the held signal. A large aperture jitter value can manifest itself by degrading the SNR of a sampling ADC. Track-to-Hold Settling Time is the time for the track to hold transient to settle to within a specified accuracy. Droop Rate is the change of the held output voltage as a function of time. The measurement starts immediately after the device switches from the track to hold mode. Aperture Delay +2V Analog Input 0V Voltage Level Held Acquisition Time –2V Hold to Track Switch Delay Time +2V Analog Output Track to Hold Settling 0V –2V “1” “Hold” Hold Command “Track” “0” FIGURE 1. SHC605 Timing Diagram. ® SHC605 8 “Hold” THEORY OF OPERATION The SHC605 is a monolithic track-and-hold circuit fabricated on an extremely fast complementary bipolar process. Figure 2 provides a simplified circuit diagram of the SHC605. A conventional two-stage operational amplifier is shown with a standard differential phase compensation scheme sometimes referred to as “doublet compensation.” Capacitors C1 and C2 compensate the amplifier in the track-mode and hold the analog output signal in the hold-mode. Switching from track to hold is achieved by turning off the amplifier’s input stage and isolating C1 and C2 from the input signal. swing. In the SHC605 the second gain stage attenuates the signal across the capacitors and greatly reduces the nonlinear capacitance. The SHC605’s second stage has a unitygain bandwidth of approximately 250MHz and its open-loop gain rolls off at –20dB/decade. With a 2.5MHz signal, the voltage across the hold capacitors is 100 times less than the output signal, and therefore, the nonlinear capacitance is greatly reduced. The SHC605’s patented architecture provides users with an extremely accurate high-speed operational track-and-hold amplifier. All common operational amplifier transfer functions can be realized with the SHC605; i.e. unity-gain, noninverting gain, inverting gain, and differential gain. These configurations are shown in Figures 3 through 6. In many instances, the SHC605 provides a superior single-chip solution to applications previously requiring two or more devices. As with any conventional voltage feedback op amp, it is important to consider tradeoffs between noise, bandwidth, and settling time for these applications. Refer to Discussion of Performance and Typical Performance Curves for more details. The differential two-stage amplifier architecture of the SHC605 provides many performance advantages over traditional open-loop designs. The use of differential hold capacitors provides a first-order correction for many errors including distortion, pedestal, and droop. A dominant cause of distortion in high-speed amplifiers is the nonlinear transistor junction capacitance connected to the hold capacitor(s). This parasitic capacitance varies as the voltage across it changes. Most open-loop track-and-hold circuits have a fixed gain of +1V/V, which means the hold capacitor(s) and parasitic junction capacitance sees the full output signal +VS C1 C1 C2 C2 Track/Hold G=1 VOUT C3 +In Comp –In –VS FIGURE 2. SHC605 Simplified Circuit Diagram. ® 9 SHC605 DISCUSSION OF PERFORMANCE DISTORTION Hold-mode distortion is an important specification for a track-and-hold amplifier. This is a measure of the accuracy of the amplifier’s held output while sampling a sinusoidal input signal. It includes errors from both the switching network and the amplifier’s signal path. Hold-mode distortion depends on the input signal’s amplitude and frequency as well as the sampling rate. The biggest cause of distortion in the SHC605 is slew-induced nonlinearity; the higher the amplitude of a high frequency input, the higher the distortion. Hold-mode distortion can also result from sampling too fast or not allowing enough acquisition time or track-to-hold settling time. The SHC605 has a typical 0.01% acquisition time of 30ns for a 2V step, and a typical 100µV track-tohold settling time of 15ns. Thus, for 12-bit accuracy the clock rate should not exceed 22MHz (refer to Typical Performance Curves for details). performance. The SHC605’s noise performance is also affected by holdmode noise and aperture jitter. Hold-mode noise is the result of current noise reacting with the hold capacitors. This noise accumulates on the capacitors at a rate which is proportional to the square root of the hold time. For sample rates above 1MHz this noise is usually insignificant. Aperture jitter describes the random variation in track-to-hold aperture delay, and causes increased hold-mode noise when high slew rate signals are sampled. A differential ECL clock input will provide lower aperture jitter than a single-ended ECL or TTL clock. CHOOSING THE BEST ARCHITECTURE The SHC605 is basically a high-speed operational amplifier which can hold its output on command. Unlike traditional high-speed track-and-hold amplifiers, which have fixed gains of +1V/V, the SHC605 can be used with non-inverting, inverting, or differential gains. In many applications, a single SHC605 can be used to solve a problem that previously required two or more devices. NOISE The SHC605’s noise performance is almost completely determined by track-mode noise. This is the noise sampled by the differential hold capacitors during track-mode, which is greater than the noise measured directly at the output. The input referred noise of the SHC605 is 2.5nV/√Hz. For unitygain this corresponds to an output noise of approximately 35µVrms; which is much lower than the typical 150µVrms noise sampled by the hold capacitors. The track-mode noise sampled by the hold capacitors is independent of closedloop gain, and therefore, the SHC605 can be used with higher closed-loop gain without degrading the overall noise Figures 3 through 6 show the SHC605 connected for noninverting, inverting, and differential gains. As with any op amp, it is important to consider performance tradeoffs for all of these configurations. For gains less than ±10, the SHC605’s track-to-hold settling, pedestal offset, droop, and total holdmode noise remains constant. However, small-signal bandwidth and acquisition time will be compromised as the closed-loop gain is increased (refer to the Typical Performance Curves for details). VIN VIN 1 2 +5V 1µF .01µF –VS 16 +In –VS 15 +VS +5V –5V .01µF 1 1µF 1µF .01µF –VS 16 +In 2 +VS –VS 15 3 +VS Lock 14 DGND Lock 13 3 +VS Lock 14 4 4 DGND Lock 13 5 AGND Hold 12 5 AGND Hold 12 6 AGND Hold 11 NC 6 AGND Hold 11 NC 7 AGND 7 AGND 8 –In 8 –In Select 10 VOUT 9 Hold +5V = TTL –5V = ECL VOUT VOUT 9 Hold +5V = TTL –5V = ECL VOUT R1 R2 50Ω 249Ω 249Ω VOUT VIN FIGURE 3. Gain of +1 Track-and-Hold Amplifier. =1+ R1 R2 FIGURE 4. Gain of +2 Track-and-Hold Amplifier. ® SHC605 Select 10 –5V 1µF .01µF 10 249Ω 125Ω +5V 1µF .01µF R2 VIN 1 +In –VS 16 2 +VS –VS 15 3 +VS Lock 14 4 DGND Lock 13 5 AGND Hold 12 6 AGND Hold 11 NC 7 AGND 8 –5V VOUT V+IN 1 +In –VS 16 +5V 2 +VS –VS 15 3 +VS Lock 14 4 DGND Lock 13 5 AGND Hold 12 6 AGND Hold 11 NC 7 AGND 8 –In 1µF .01µF Hold +5V = TTL –5V = ECL Select 10 –In R2 249Ω 1µF .01µF R1 9 VOUT 249Ω 249Ω V–IN R1 –5V .01µF Hold +5V = TTL –5V = ECL Select 10 VOUT 1µF 9 VOUT R2 R1 249Ω VOUT VIN 249Ω R1 R2 = – VOUT = (V+IN – V–IN) R1 R2 FIGURE 5. Gain of –1 Track-and-Hold Amplifier. FIGURE 6. Differential Gain of 1 Track-and-Hold Amplifier. APPLICATIONS INFORMATION LOCKOUT CIRCUITRY The SHC605 includes additional logic circuitry which allows edge-triggered operation for sampling ADCs. The lockout comparator and Track/Hold comparator form a wiredor mode control circuit as shown in the block diagram on page one. When the Lock input, pin 14, is high with respect to the Lock input, pin 13, the SHC605 is in the Hold-mode regardless of the Hold/Hold inputs. This feature provides more flexibility in the convert command duty cycle and reduces noise resulting from aperture jitter. LOGIC COMPATIBILITY/TRACK-TO-HOLD SWITCHING The SHC605 contains an internal reference circuit which produces either an ECL or TTL logic threshold voltage for single-ended track-to-hold switching. Differential ECL switching is also possible with the SHC605. Table I provides the proper pin connections for all of the possible switching options and the Performance Specifications Table gives the logic levels and input bias currents. LOGIC TYPE Single-ended TTL Single-ended ECL Differential ECL DGND (Pin 4) SELECT (Pin 10) THRESH/HOLD (Pin 11) HOLD (Pin 12) GND GND NC +5V –5V NC NC NC Clock Clock Clock Clock Figure 7 shows how the SHC605 lockout circuit can be used with an ECL one-shot to provide an edge-triggered sampling ADC. An ECL threshold voltage is generated on Thresh/ Hold (Pin 11), which is connected to Lock (Pin 13), to allow a single-ended lockout input on Lock (Pin 14). The ECL convert command is applied directly to the SHC605. The 10ns delay on the ADCs convert signal is to allow for SHC605 track-to-hold settling. The one-shot’s duty cycle TABLE I. Track-to-Hold Switching Options. ECL Convert Command (10ns minimum pulsewidth) VIN 1 +5V 1µF .01µF –VS 16 +In 2 +VS –VS 15 3 +VS Lock 14 4 DGND Lock 13 5 AGND Hold 12 6 AGND Hold 11 7 AGND Select 10 8 –In –5V .01µF 1µF ECL One-Shot LOCK MODE 0 0 1 1 0 1 0 1 Track Hold Hold Hold Convert VOUT VOUT 10ns Delay Line HOLD ADC 9 Digital Output 50Ω FIGURE 7. Edge-Triggered ADC. ® 11 SHC605 damage can cause subtle changes in SHC605 input characteristics without necessarily destroying the device. In precision track-and-hold amplifiers, this may cause a noticeable degradation in performance. Therefore, static protection is recommended when handling the SHC605. will depend on the ADC conversion time. In this application the one-shot is used to set the critical ADC timing which means the user has more freedom in selecting the convert command duty cycle. Since the convert command is applied directly to the SHC605—instead of after additional logic and clock conditioning—aperture jitter noise is minimized. +VCC OFFSET VOLTAGE ADJUSTMENT The SHC605’s input offset voltage is laser-trimmed and will require no further adjustment for most applications. However, if additional adjustment is needed, the circuit in Figure 8 can be used without degrading offset drift with temperature. Avoid external adjustment whenever possible since extraneous noise, such as power supply noise, can be inadvertently coupled into the amplifier’s inverting input. Remember that additional offset errors can be created by the amplifier’s input bias currents. Whenever possible, match the impedance seen by both inputs as is shown with R3. This will reduce input offset voltage errors due to the amplifier’s input offset current, which is typically only 0.2µA. RTRIM –VCC FIGURE 9. Internal ESD Protection. LAYOUT AND BYPASSING For best performance, good high speed design techniques must be applied. The component (top) side ground plane should be as large as possible and continuous (not fragmented). Two ounce copper cladding is recommended. All traces should be as short as possible, especially the output. As much of the ground plane as possible should be removed from around the +In, –In, and VOUT pins to reduce parasitic capacitance and minimize coupling onto the analog signal path. 8 20kΩ 47kΩ 1 SHC605 Power supply decoupling capacitors must be used as shown in Figures 3 through 6. The 0.01µF capacitors should be low inductance surface mount devices and should be connected as close to the SHC605 ±Vs leads as possible (within 30 mils). The 1µF low frequency bypass capacitors should be tantalum capacitors (preferably surface mount) and should be located within one inch of the SHC605. Surface mount resistors are also recommended and should be placed as close to the SHC605 as possible to minimize inductance. 9 –VCC R3 = R1 || R2(1) R1 CAPACITIVE LOADS The SHC605’s output stage has been optimized to drive resistive loads as low as 50Ω. Capacitive loads will decrease the amplifier’s phase margin which may cause high frequency peaking or oscillations. Capacitive loads greater than 10pF should be buffered by connecting a small resistance, usually 20Ω to 50Ω, in series with the output as shown in VIN or Ground Output Trim Range ≈ +VCC Internal Circuitry External Pin R2 +VCC ESD Protection Diodes Internally Connected to All Pins R2 R2 to –VCC RTRIM RTRIM NOTE: (1) R3 is optional and can be used to cancel offset errors due to input bias currents. FIGURE 8. Offset Voltage Trim. INPUT PROTECTION (RS is typically 20Ω to 50Ω) The SHC605 incorporates on-chip ESD protection diodes as shown in Figure 9. All pins on the SHC605 are internally protected from ESD by means of a pair of back-to-back reverse-biased diodes to either power supply as shown. These diodes will begin to conduct when the input voltage exceeds either power supply by about 0.7V. This situation can occur with loss of the amplifier’s power supplies while a signal source is still present. The diodes can typically withstand a continuous current of 30mA without destruction. To insure long term reliability diode current should be externally limited to 10mA or so whenever possible. Static 8 1 9 RL FIGURE 10. Driving Capacitance Load. ® SHC605 RS SHC605 12 CL APPLICATIONS The SHC605’s combination of high speed and accuracy, small size, and low price makes it ideally suited for many data acquisition applications. Its versatile operational amplifier architecture and switching flexibility provides users with an extremely reliable single-chip solution to problems that previously required several components. Figures 11 through 16 show many application circuits using the SHC605. These include high-speed flash and sub-ranging ADC driving, multi-channel simultaneous sampling, DAC deglitching, and peak detecting. Figure 10. This is particularly important when driving high capacitance loads such as flash A/D converters. The series resistor, RS, should be connected as close to the SHC605 as possible. If RS causes excessive output attenuation, add closed-loop gain to the SHC605 as shown in Figures 4 through 6. In general, capacitive loads should be minimized for optimum high frequency performance. Coax lines can be driven if the cable is properly terminated. The capacitance of coaxial cable (29pF/foot for RG-58) will not load the amplifier when the coaxial cable or transmission line is terminated in its characteristic impedance. Analog Input High-speed Sub-ranging or Flash ADC SHC605 Hold Digital Output Convert Timing Circuit Sampling Clock FIGURE 11. Sampling ADC. Analog Input Ch 1 Ch 2 Ch 3 Analog MUX SHC605 Digital Output ADC Hold Ch 4 Convert Channel Select Sampling Clock Timing Circuit FIGURE 12. Traditional Data Acquisition System. ® 13 SHC605 Analog Inputs Ch 1 SHC605 Hold Ch 2 SHC605 Hold Analog MUX SHC605 Digital Output ADC Hold Ch 3 SHC605 Convert Hold Ch 4 Channel Select SHC605 Hold Timing Circuit Sampling Clock FIGURE 13. Multi-Channel Simultaneous Sampling System. 100Ω I Channel SHC605 – +A OPA678 + B – Channel Select Hold Q Channel SHC605 Hold 100Ω Timing Circuit Sampling Clock FIGURE 14. I/Q Channel Simultaneous Sampling. ® SHC605 14 Digital Output ADC Convert Analog Input VOUT SHC605 Hold Comparator with Hysteresis Output Input Hold Track 2µs max FIGURE 15. High-Speed Peak Detector. Digital Input SHC605 DAC VOUT Hold Convert Timing Circuit Sampling Clock DAC Intput 100...0 011...1 DAC Output Hold Track SHC605 Output FIGURE 16. DAC Deglitcher. ® 15 SHC605