® VFC100 FPO Synchronized VOLTAGE-TO-FREQUENCY CONVERTER FEATURES DESCRIPTION ● FULL-SCALE FREQUENCY SET BY SYSTEM CLOCK; NO CRITICAL EXTERNAL COMPONENTS REQUIRED The VFC100 voltage-to-frequency converter is an important advance in VFCs. The well-proven charge balance technique is used; however, the critical reset integration period is derived from an external clock frequency. The external clock accurately sets an output full-scale frequency, eliminating error and drift from the external timing components required for other VFCs. A precision input resistor is provided which accurately sets a 10V full-scale input voltage. In many applications the required accuracy can be achieved without external adjustment. ● PRECISION 10V FULL-SCALE INPUT, 0.5% max GAIN ERROR ● ACCURATE 5V REFERENCE VOLTAGE ● EXCELLENT LINEARITY: 0.02% max at 100kHz FS 0.1% max at 1MHz FS ● VERY LOW GAIN DRIFT: 50ppm/°C The open collector active-low output provides fast fall time on the important leading edge of output pulses, and interfaces easily with TTL and CMOS circuitry. An output one-shot circuit is particularly useful to provide optimum output pulse widths for optical couplers and transformers to achieve voltage isolation. An accurate 5V reference is also provided which is useful for applications such as offsetting for bipolar input voltages, exciting bridges and sensors, and autocalibration schemes. APPLICATIONS ● A/D CONVERSION ● PROCESS CONTROL ● DATA ACQUISITION ● VOLTAGE ISOLATION C INT VOUT 5 4 – Comparator Input Clock Input 14 +VCC 1 10 11 VIN Non-Inverting Input 7 R IN 6 20k Ω Integrator Amplifier fOUT Comparator Clocked Logic Output One-Shot 12 SW1 1mA Digital Common 5V Reference –VCC 13 Analog Common 15 16 + Comparator Input VREF 9 8 C OS –VCC International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1984 Burr-Brown Corporation PDS-547H Printed in U.S.A. June, 1995 SPECIFICATIONS At TA = +25°C and ±15VDC supplies, unless otherwise noted. VFC100AG PARAMETER CONDITIONS TRANSFER FUNCTION Voltage-to-Frequency Mode Gain Error(1) Linearity Error Gain Drift(2) Referred to Internal VREF Offset Referred to Input Offset Drift Power Supply Rejection Response Time Current-to-Frequency Mode Gain Error Gain Drift(2) Frequency-to-Voltage Mode(3) Gain Accuracy(1) Linearity Input Resistor (RIN) Resistance Temperature Coefficient (TC)(2) INTEGRATOR OP AMP VOS(1) VOS Drift IB IOS AOL CMRR CM Range VOUT Range Bandwidth COMPARATOR INPUTS Input Current (Operating) fOUT = fCLOCK x (VIN /20V) FSR = 100kHz FSR = 100kHz, Over Temperature FSR = 500kHz, COS = 60pF FSR = 1MHz, COS = 60pF FSR = 100kHz Full Supply Range To Step Input Change fOUT = fCLOCK x (IIN /1mA) MIN 19.8 ZLOAD = 5kΩ/10,000pF 100 80 –7.5 –0.2 OUTPUT ONE-SHOT Active(6) Pulse Width Out Deactivated(5) Pulse Width Out Pulse Width Out REFERENCE VOLTAGE Accuracy Drift(2) Current Output Power Supply Rejection Output Impedance ±1 ±0.025 ±0.2 ✻ ✻ ✻ ±30 ±30 ±1 ±6.5 ±0.5 ±120 ±1 ±200 ±0.2 ±80 ±0.5 ±140 % of FSR ppm of FSR/°C ±0.5 ±0.01 ±1 ±0.025 ±0.2 ✻ ±0.5 ±0.02 % % 20 ±50 20.2 ±100 ✻ ✻ ✻ ✻ kΩ ppm°C ±150 ±5 ±50 100 120 105 ±1000 ✻ ✻ ±25 50 ✻ ✻ ✻ µV µV/°C nA nA dB dBV V V MHz ✻ ±100 200 +0.1 +12 ✻ ✻ ✻ ✻ ✻ MAX 0.8 –VCC + 2V –VCC < VCLOCK < +VCC 0.5 IOUT = 10mA VOH = 30V 0.01 2 +VCC 5 2 ✻ ✻ ✻ 0.4 15 10 ✻ 1.4 100kHz ≤ FSR < 1MHz ✻ ✻ 2 ✻ ✻ % of FSR(4) % of FSR % of FSR % of FSR ppm of FSR/°C ppm of FSR/°C mV µV/°C %/V µA ✻ ✻ ✻ ✻ MHz V V V µA µs ✻ ✻ ✻ V mA µA ns ns pF ✻ ✻ 1 4 fCLOCK UNITS ✻ ✻ ✻ ✻ 300 100 5 1 ±50 100 ✻ ✻ 4 1.4 COS = 300pF TYP 5 µs sec FSR = 1MHz 250 450 500 ✻ ✻ ✻ ns No Load 4.9 5 ±60 5.1 ±150 4.95 5.05 ±100 Sourcing Capability 10 ✻ ±40 ✻ 0.5 0.015 2 V ppm/°C mA %/V Ω ® VFC100 ±0.5 ±0.01 ±0.015 ±0.025 ±70 ±70 ±1 ±12 –11V < VCOMPARATOR < +VCC – 2V Over Temperature OPEN COLLECTOR OUTPUT (Referred to Digital Common) VOL IOL IOH (Off Leakage) Delay Time, Positive Clock Edge to Output Pulse Fall Time Output Capacitance MIN 14 CLOCK INPUT (Referred to Digital Common) Frequency (Maximum Operating) Threshold Voltage Voltage Range (Operating) Input Current Rise Time MAX ±0.5 ±0.02 ±0.05 ±0.1 ±100 ±50 ±100 ±50 ±3 ±2 ±100 ±25 0.01 ✻ One Period of New Output Frequency Plus One Clock Period VOUT = 20V x (fIN /fCLOCK) FSR = 100kHz FSR = 100kHz ZLOAD = 5kΩ/10,000pF VFC100BG TYP 2 ✻ 0.015 ✻ SPECIFICATIONS (CONT) At TA = +25°C and ±15VDC supplies, unless otherwise noted. VFC100AG PARAMETER CONDITIONS POWER SUPPLY Rated Voltage Operating Voltage Range (See Figure 9) MIN TYP VFC100BG MAX MIN ±15 +VCC –VCC +VCC – (–VCC) Total Supply Digital Common Quiescent Current: +ICC –ICC +7.5 –7.5 15 –VCC + 2 Over Temperature TEMPERATURE RANGE Specification Storage θJA θJC 10.6 9.6 –25 –65 TYP MAX UNITS ✻ +28.5 –28.5 36 +VCC – 4 15 15 ✻ ✻ ✻ ✻ +85 +150 ✻ ✻ V ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V V V mA mA ✻ ✻ °C °C °C/W °C/W ✻ ✻ 150 100 ✻ Specification same as AG grade. NOTES: (1) Offset and gain error can be trimmed to zero. See text. (2) Specified by the box method: (max. – min.) ÷ (FSR x ∆T). (3) Refer to detailed timing diagram in Figure 16 for frequency input signal timing requirements. (4) FSR = Full Scale Range. (5) Pin 9 connected to +VCC. (6) Nominal PWOUT = (5ns/pF) x COS – 90ns. ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Power Supply Voltage (+VCC to –VCC ) ............................................... 36V +VCC to Analog Common ..................................................................... 28V –VCC to Analog Common ..................................................................... 28V Integrator Out Short-Circuit to Ground ........................................ Indefinite Integrator Differential Input ................................................................ ±10V Integrator Common-Mode Input .................................... –VCC +5V to +2V VIN (pin 7) ......................................................................................... ±VCC Clock Input ......................................................................................... ±VCC VREF Out Short-Circuit to Ground ................................................ Indefinite Pin 9 (COS) ................................................................................. 0 to +VCC fOUT (referred to digital common) .......................................... –0.5V to 36V Digital Common ................................................................................. ±VCC Storage Temperature Range .......................................... –65°C to +150°C Lead Temperature (soldering, 10s) ................................................. 300°C Top View DIP +VCC 1 16 V REF NC 2 15 + Comparator In NC 3 14 – Comparator In Integrator Out 4 13 Analog Common C INT 5 12 Digital Common Noninverting In 6 11 f OUT V IN 7 10 Clock Input –VCC 8 9 C OS PACKAGE INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) VFC100AG VFC100BG 16-Pin Ceramic DIP 16-Pin Ceramic DIP 129 129 ELECTROSTATIC DISCHARGE SENSITIVITY NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 VFC100 TYPICAL PERFORMANCE CURVES At +25°C, ±VCC = 15VDC, and in circuit of Figure 1. QUIESCENT CURRENT vs TEMPERATURE REFERENCE VOLTAGE vs REFERENCE LOAD CURRENT 5.01 5 15 Short Circuit Current Limit +I CC VREF (V) Supply Current (mA) 20 10 –I CC 4.99 4.98 5 4.97 0 –75 4.96 –50 –25 0 25 50 75 100 125 0 Ambient Temperature (°C) 5 10 15 20 25 30 Output Current (mA) THEORY OF OPERATION The VFC100 monolithic voltage-to-frequency converter provides a digital pulse train output with an average frequency proportional to the analog input voltage. The output is an active low pulse of constant duration, with a repetition rate determined by the input voltage. Falling edges of the output pulses are synchronized with rising edges of the clock input. for one complete clock cycle, causing the reset current, I1, to switch to the integrator input. Since I1 is larger than the input current, IIN, the output of the integrator ramps positively during the one clock cycle reset period. The clocked logic circuitry also generates a VFC output pulse during the reset period. Operation is similar to a conventional charge balance VFC. An input operational amplifier (Figure 1) is configured as an integrator so that a positive input voltage causes an input current to flow in RIN. This forces the integrator output to ramp negatively. When the output of the integrator crosses the reference voltage (5V), the comparator trips, activating the clocked logic circuit. Once activated, the clocked logic awaits a falling edge of the clock input, followed by a rising edge (see Figure 2). On the rising edge, switch S1 is closed Unlike conventional VFC circuits, the VFC100 accurately derives its reset period from an external clock frequency. This eliminates the critical timing capacitor required by other VFC circuits. One period (from rising edge to rising edge) of the clock input determines the integrator reset period. When the negative-going integration of the input signal crosses the comparator threshold, integration of the input signal will continue until the reset period can start (awaiting ® VFC100 4 C INT FC Clock TTL/CMOS 5 4 14 0.1µF +VCC +VL 1 10 11 +VCC IIN VIN 7 R IN 6 20k Ω Integrator 0.1µF fOUT Comparator Output One-Shot Clocked Logic 12 S1 1mA 5V Reference I1 Digital Ground –VCC –VCC 13 15 16 Analog Ground 9 8 +VCC –VCC 0.1µF FIGURE 1. Circuit Diagram for Voltage-to-Frequency Mode. Clock Integrator 5V fO FIGURE 2. Timing Diagram for Voltage-to-Frequency Mode. the necessary transitions of the clock). Output pulses are thus made to align with rising edges of the external clock. This causes the instantaneous output frequency to be a subharmonic of the clock frequency. The average frequency, however, will be an accurate analog of the input voltage. When the input signal returns to within the linear range, the integrator amplifier will recover and begin ramping upward during the reset period. INSTALLATION AND OPERATING INSTRUCTIONS A full scale input of 10V (or an input current of 0.5mA) causes a nominal output frequency equal to half the clock frequency. The transfer function is The integrator capacitor CINT (see Figure 1) affects the magnitude of the integrator voltage waveform. Its absolute accuracy is not critical since it does not affect the transfer function. This allows a wide range of capacitance to produce excellent results. Figure 4 facilitates choosing an appropriate fOUT = (VIN/20V) fCLOCK. Figure 3 shows the transfer function graphically. Note that inputs above 10V (or 0.5mA) do not cause an increase in the output frequency. This is an easily detectable indication of an overrange input. In the overrange condition, the integrator amplifier will ramp to its negative output swing limit. 10µ Integrator Swing* +100mV –75mV 1µ C INT (F) f FS = f CLOCK /2 0.1µ +1V –0.75V 0.01µ +2.5V –1.9V f OUT 1000p 100p 100 1k 10k 100k 1M 10M Full-Scale Frequency (Hz) 0 0 V IN I IN * This is the maximum swing of the integrator output voltage referred to the comparator noninverting input voltage. 10V 0.5mA FIGURE 3. Transfer Function for Voltage-to-Frequency Mode. FIGURE 4. Integrator Capacitor Selection Graph. ® 5 VFC100 standard value to assure that the integrator waveform voltage is within acceptable limits. Good dielectric absorption properties are required to achieve best linearity. Mylar®, polycarbonate, mica, polystyrene, Teflon® and glass types are appropriate choices. The choice in a given application will depend on the particular value and size considerations. Ceramic capacitors vary considerably from type to type and some produce significant nonlinearities. Polarized capacitors should not be used. “Shortened Output Pulses”). This minimizes power dissipation over the full frequency range and provides the fastest logic edge at the beginning of the output pulse, where it is most desirable. Interface to a logic circuit would normally be made using a pull-up resistor to the logic power supply. Selection of the pull-up resistor should be made such that no more than 15mA flows in the output transistor. The actual choice of the pull-up resistor may depend on the full-scale frequency and the stray capacitance on the output line. The rising edge of an output pulse is determined by the RC time constant of the pull-up resistor and the stray capacitance. Excessive capacitance will produce a rounding of the output pulse rising edge, which may create problems driving some logic circuits. If long lines must be driven, a buffer or digital line transmitter circuit should be used. Deviation from the nominal recommended +1V to –0.75V integrator voltage (as controlled by the integrator capacitor value) is permissible and will have a negligible effect on VFC operation. Certain situations may make deviations from the suggested integrator swing highly desirable. Smaller integrator voltages, for instance, allow more “headroom” for averaging noisy input signals. The VFC is a fully integrating input converter, able to reject large levels of interfering noise. This ability is limited only by the output voltage swing range of the integrator amplifier. By setting a small integrator voltage swing using a large CINT value, larger levels of noise can be integrated without integrator output saturation and loss of accuracy. For instance, with a 50kHz full-scale output and CINT = 0.1µF, the circuit in Figure 1 can accurately average an input through the full 0 to 10V input range with 1Vp-p superimposed 60Hz noise. The synchronized nature of the VFC100 makes viewing its output on an oscilloscope somewhat tricky. Since all output pulses align with the clock, it is best to trigger and view the clock on one of the input channels; the output can then be viewed on another oscilloscope channel. Depending on the VFC input voltage, the output waveform may appear as if the oscilloscope is not properly triggered. The output might best be visualized by imagining a constant output frequency which is locked to a submultiple of the clock frequency with occasional extra pulses or missing pulses to create the necessary average frequency. It is these extra or missing pulses that make the output waveform appear as if the oscilloscope is not properly triggered. This is normal. Experimentation with the input voltage and oscilloscope triggering generally allows a stable view of the output and provides an understanding of its nature. The integrator output voltage should not be allowed to exceed +12V or –0.2V, otherwise saturation of the operational amplifier could cause inaccuracies. Operation with positive power supplies less than +15V will limit the output swing of the integrator operational amplifier. Smaller integrator voltage waveforms may be required to avoid output saturation of the integrator amplifier. See “Power Supply Considerations” for information on low voltage operation. SHORTENED OUTPUT PULSES In normal operation, the negative output pulse duration is equal to one period of the clock input. Shorter output pulses may be useful in driving optical couplers or transformers for voltage isolation or noise rejection. This can be accomplished by connecting capacitor COS as shown in Figure 5. Pin 9 may be connected to +VCC, deactivating the output one-shot circuit. The value of COS is chosen according to the curve in Figure 6. Output pulses cannot be made to exceed one clock period in duration. Thus, a COS value which would create an output pulse which is longer than one period of the clock will have the same effect as disabling the one-shot, causing the output pulse to last one clock period. The minimum practical pulse width of the one-shot circuit is approximately 100ns. Using COS to generate shorter output pulses does not affect the output frequency or the gain equation. The maximum integrator voltage swing requirement is nearly symmetrical about the comparator threshold voltage (see Figure 12). One-third greater swing is required above the threshold than below it. Maximum demand on positive integrator swing occurs at low scale, while the negative swing is greatest just below full scale. CLOCK INPUT The clock input is TTL and CMOS-compatible. Its input threshold is approximately 1.4V (two diode voltage drops) referenced to digital ground (pin 12). The clock “high” input may be standard TLL or may be as high as +VCC – 2V. A CMOS clock should be powered from a voltage source at least 2V below the VFC100’s +VCC to prevent overdriving the clock input. Alternatively, a resistive voltage divider may be used to limit the clock voltage swing to +VCC – 2V maximum. The clock input has a high input impedance, so no special drivers are required. Rise time in the transition region from 0.8V to 2V must be less than 2µs for proper operation. REFERENCE VOLTAGE Excellent gain drift is achieved by use of a precision internal 5V reference. This reference is brought to an external pin and can be used for a variety of purposes. It is used to offset the noninverting comparator input in voltage-to-frequency mode (although a precise voltage is not required for this function). The reference is very useful for handling bipolar OUTPUT The frequency output is an open collector current-sink transistor. Output pulses are active low such that the output transistor is on only during the reset integration period (see ® VFC100 6 C INT 5 14 4 VL +VCC = 15VDC Clock 1 10 0.1µF 0.1µF 11 +VCC VIN 7 R IN Clocked Logic f OUT Output One-Shot 6 12 5V Reference –VCC 13 15 16 –VCC COS +VCC 9 8 –VCC = 15VDC 0.1µF Clock tO f OUT Output Pulse Width Without C OS FIGURE 5. Circuit and Timing Diagram for Shortened Output Pulses. The reference output amplifier is specifically designed for excellent transient response, to provide precision in a noisy environment. One-Shot Capacitor Value, C OS 1µF 0.1µF OTHER INPUT VOLTAGE RANGES The internal input resistor, RIN = 20kΩ, sets a full-scale input of 10V. Other input ranges can be created by using an external gain set resistor connected to pin 5. Since the excellent temperature drifts of the VFC100 are achieved by careful matching of internal temperature coefficients, use of an external gain set resistor will generally degrade this drift. Using an external resistor to set the gain, the resulting gain drift would be equal to the sum of the external resistor drift and the specified current gain drift of the VFC100. Different voltage input ranges are best implemented by using the internal input resistor, RIN, in series or parallel with a high quality external resistor, thus maintaining as much of the precision temperature tracking as possible. 0.01µF 1000pF tO 100pF 10pF 100ns 1µs 10µs 100µs 1ms 10ms Nominal Output Pulse Width, t O FIGURE 6. Output One-Shot Capacitor Selection. input signals in many other applications, such as offsetting the input. It can source up to 10mA and sink 100µA. Heavy loading of the reference will change the gain of the VFC and affect the external reference voltage. For instance, a 10mA load interacting with a 0.5Ω typical output impedance will change the VFC gain equation and reference voltage by 0.1%. For best drift performance, the adjustment range of a fine gain trim should be made as narrow as practical. R1 and R2 in Figure 9 allow gain adjustments over a ±1% range (adequate to trim the 100kHz FS gain error to zero) and will not significantly affect the drift performance of the VFC100. R3, R4 and R5 allow trimming of the integrator amplifier input offset voltage. The adjustment range is determined by the ratio of R4 to R5. Accurate end-point calibration would be performed by first adjusting the offset trim so that zero volts input just causes all output pulses to cease. The gain trim is then adjusted for the proper full-scale output frequency with an accurate full-scale input voltage. Figure 7 shows the reference used to offset the VFC transfer function, to convert a –5V to +5V input to 0–500kHz output. The circuit in Figure 8 uses the reference to excite a 300Ω bridge transducer. R1 provides the majority of the current to the bridge while the VREF output supplies the balance and accurately controls the bridge voltage. The VFC gain is inversely proportional to the reference voltage, VREF. Since the bridge gain is directly proportional to its excitation voltage, the two equal and opposite effects cancel the effect of reference voltage drift on gain. A different input voltage range could also be made by using only a portion of the normal input range of the VFC. For instance, a 2V full-scale input could be created by using the ® 7 VFC100 5 14 4 1 10 0.1µF 470Ω 11 +VCC 7 VIN –5 to +5V R IN 0.1µF +5VDC +15VDC 1MHz Clock 0.01µF f OUT TTL (or 5V CMOS) 0 to 500kHz PW ≈ 300ns Output One-Shot Clocked Logic 6 12 R1 20kΩ 5V Reference –VCC 13 15 –VCC 9 16 8 60pF +VCC –15VDC 0.1µF FIGURE 7. Circuit Diagram for Bipolar Input Voltages. 16.7mA 8.5mA to 15.9mA INA101 Instrumentation Amplifier 300Ω 0.1µF 0.1µF 5 820Ω 14 4 50kHz Clock 1 10 11 +VCC 7 R IN Clocked Logic f OUT 0 to 25kHz Output One-Shot 6 0.8mA to 8.2mA +VL +12 to +18VDC R1 12 5V Reference –VCC 13 15 16 –VCC 9 8 0.05µF 0.1µF +VCC –VCC FIGURE 8. Circuit Diagram for Bridge Excitation Using VREF. The best linearity performance at high full-scale frequencies (above 500kHz) is obtained by using short output pulses with a one-shot capacitor of 60pF. As with any highfrequency circuit, careful attention to good power supply bypassing techniques (see “Power Supplies and Grounding”) is also required. internal input resistor and a clock frequency of 10 times the desired full-scale output frequency. LINEARITY PERFORMANCE The linearity of the VFC100 is specified as the worst-case deviation from a straight line defined by low scale and high scale end point measurements. This worst-case deviation is expressed as a percentage of the 10V full-scale input. All units are tested and guaranteed for the specified level of performance. TEMPERATURE DRIFT Conventional VFC circuits are affected significantly by external component temperature drift. Drift of the external input resistor and timing capacitor required with these devices may easily exceed the specified drift of the VFC itself. Linearity performance and gain error change with full-scale operating frequency as shown in Figure 10. Figure 11 shows the typical shape of the nonlinearity at 100kHz full scale. Integrator voltage swing (determined by CINT) has a minor effect on linearity. A small integrator voltage swing typically leads to best linearity performance. When used with its internal input resistor, the gain drift of the complete VFC100 circuit is totally determined by the performance of the VFC100. Gain drift is specified at a fullscale output frequency of 100kHz. Conventional VFC circuits usually specify drift at 10kHz and degrade significantly ® VFC100 8 R2 5 2MΩ CINT 14 4 +VL +15VDC Clock 0.1µF 0.1µF 1 10 11 +VCC R1 7 VIN R IN Output One-Shot Clocked Logic 6 500Ω ±1% Gain Trim R3 f OUT 12 5V Reference 20kΩ –VCC 13 15 –VCC 9 16 8 R5 ±3.75mV Offset Trim R4 500Ω 0.1µF 350kΩ +15VDC –15VDC FIGURE 9. Circuit Diagram for Fine Offset and Gain Trim. 0.03 3 0.02 2 0.015 0.01 1 Nonlinearity (%) Nonlinearity Gain Error (%) Nonlinearity (%) 0.01 Gain Error 0 0 0 0 500k 0.005 –0.005 1M 0 fFS – Full Scale Frequency (Hz) 2 4 6 8 10 VIN (V) FIGURE 10. Typical Nonlinearity and Gain Error vs Full Scale Frequency. FIGURE 11. Typical Nonlinearity vs VIN. (fFS = 0.1MHz) at higher operating frequency. The VFC100’s gain drift remains excellent at higher operating frequency, typically remaining within specifications at fFS = 1MHz. VREF pin is referenced to analog ground. The power supplies should be well bypassed using capacitors with low impedance at high frequency. A value of 0.1µF is adequate for most circuit layouts. Drift of the external clock frequency directly affects the output frequency, but by using a common clock for the VFC and counting circuitry, this drift can be cancelled (see “Counting the Output”). The VFC100 is specified for a nominal supply voltage of ±15V. Supply voltages ranging from ±7.5V to ±18V may be used. Either supply can be up to 28V as long as the total of both does not exceed 36V. Steps must be taken, however, to assure that the integrator output does not exceed its linear range. Although the integrator output is capable of 12V output swing with 15V power supplies, with 7.5V supplies, output swing will be limited to approximately 4.5V. In this case, the comparator input cannot be offset by directly connecting to the 5V reference output pin. The comparator input must be connected to a lower voltage point (approximately 2V). This allows the integrator output to operate around a lower voltage point, assuring linear operation. This threshold voltage does not affect the accuracy or drift of the VFC as long as it is not noisy. It should not be made too POWER SUPPLIES AND GROUNDING Separate analog and digital grounds are provided on the VFC100 and it is important to separate these grounds to attain greatest accuracy. Logic sink current flowing in the fOUT pin is returned to the digital ground. If this “noisy” current were allowed to flow in analog ground, errors could be created. Although analog and digital grounds may eventually be connected together at a common point in the circuitry, separate circuit connections to this common point can reduce the error voltages created by varying currents flowing through the ground return impedance. The +5V ® 9 VFC100 clock period of the counting gate period. The quantizing error can be made arbitrarily small by counting with long gate times. For instance, a one-second counter gate period with a 100kHz full-scale frequency has a resolution of one part in 100,000. Many of the more sophisticated laboratory frequency counters, however, use period measurement schemes to count the input frequency quickly. These instruments work equally well, but the gate period must be set appropriately to achieve the desired count resolution. Short gate periods will produce many digits of “accuracy” in the display, but the results may be very inaccurate. small, however, or the negative output limitation of the integrator (–0.2V) may cause saturation. Additionally, a large integrator capacitor may be used to limit the required integrator waveform swing to approximately 100mV (see “Integrator Capacitor”). Figure 12 shows a circuit for operating from the minimum power supplies, avoiding saturation of the integrator amplifier and loss of accuracy. CINT is chosen for a +100mV to –75mV integrator voltage swing (referred to the noninverting comparator input). The offset voltage applied to the comparator’s noninverting input is derived from a resistive voltage divider from VREF. Figure 14 is a typical system application showing a basic counting technique. A 0 to 10V input is converted to a 0 to 100kHz frequency output. The VFC’s clock is divided by M = 4000 to produce a gate period for the counter circuit. The resulting VFC count, N, is insensitive to variations in the actual clock frequency. The input voltage represented by the resulting count is VIN = (N/M) 20V. The relationship of the allowable operating voltage ranges on important pins is show in Figure 13. Note that the integrator amplifier output cannot swing more than 0.2V below ground. Although this is not “normal” for an operational amplifier, a special internal design of this type optimizes high frequency performance. It is this characteristic which necessitates the offsetting of the noninverting comparator input in voltage-to-frequency mode to avoid negative output swing. Resolution is related to the number of counts at full scale, or half the number of clock pulses in the gate period. The integrating nature of the VFC is important in achieving accurate conversions. The integrating period is equal to the counting period. This can be used to great advantage to reject unwanted signals of a known frequency. Figure 15 shows that response nulls occur at the inverse of the integration period and its multiples. If 60Hz is to be rejected, for instance, the counting period should be made equal to, or a multiple of, 1/60 of a second. COUNTING THE OUTPUT In evaluation and use of the VFC100, you may want to measure the output frequency with a frequency counter. Since synchronization of the VFC100 causes it to await a clock edge for any given output pulse, the output frequency is essentially quantized. The quantized steps are equal to one Clock 100kHz C INT 5 0.1µF 4 14 +VL +8V 0.1µF 0.1µF 1 10 11 +VCC VIN 7 0 to 10V 6 R IN f OUT 0 to 50kHz Output One-Shot Clocked Logic 12 5V Reference –VCC 13 15 –VCC 9 16 8 2.2kΩ VTH 2.25V 0.1µF 0.05µF 1.8kΩ +8V –8V Integrator Voltage Waveform (Pin 4) VTH + 100mV VTH 2.25V High Scale (VIN ≈ 8.3V) Fast Oscilloscope Sweep Low Scale (VIN ≈ 120mV) Slow Oscilloscope Sweep VTH – 75mV FIGURE 12. Circuit Diagram and Integrator Voltage Waveform Power Supply Voltage Operation. ® VFC100 10 FREQUENCY-TO-VOLTAGE MODE The VFC100 can also function as a frequency-to-voltage converter by supplying an input frequency to the comparator input as shown in Figure 16. The input resistor, RIN, is connected as a feedback resistor. The voltage at the integrator amp output is proportional to the ratio of the input frequency to the clock frequency. The transfer function is VOUT = (FIN/fCLOCK) 20V. Direct coupling of the input frequency to the comparator is easily accomplished by driving both comparators with complementary frequency input signals. Alternatively, one of the comparator inputs can be biased at half the logic voltage (using VREF and a voltage divider) and the other input driven directly. The proper timing of the input frequency waveform is shown in Figure 16. The input pulse should go low for one clock cycle, centered around a falling edge of the clock. The minimum acceptable input pulse width must fall no later than 200ns before a negative clock edge and rise no sooner This transfer function is complementary to the voltage-tofrequency mode transfer function, making voltage-to-frequency-to-voltage conversions simple and accurate. +VCC –VCC + 4 to +VCC – 2 > 3V –VCC + 2 to +VCC – 2 5 14 4 1 10 R IN 7 7.5V to 28.5V –0.5V to 30V Output One-Shot Clocked Logic > 4V 11 +VCC 6 12 > –0.2V 15V to 36V < 0.1V > 7.5V > –7.5V 5V Reference –VCC 13 15 –VCC 9 16 > 2V 8 5V +VCC or C OS –VCC + 4 to +VCC – 2 7.5V to 28.5V –VCC FIGURE 13. Relationships of Allowable Voltages. 4000 Counts CMOS Inverters fC ≈ 200kHz ÷ 4000 D Q C Q 22kΩ 22Ω (M = 4000) 68pF C1 0.1µF 4 14 5 +15VDC +VL 0.1µF 1 10 Reset 11 +VCC 0 to 10V Input 7 To Processor µP or Display 0.1µF Counter “N” fO = 0 to 100kHz RIN Clocked Logic Output One-Shot Maximum Count: N = M/2 = 2000 6 12 Logic Ground 5V Reference Computed Result VIN' = 20V x (N/M) –VCC –VCC 13 15 9 16 0.05µF +15VDC 8 0.1µF –15VDC FIGURE 14. Diagram of a Voltage-to-Frequency Converter and Counter System. ® 11 VFC100 than 200ns after the falling clock edge. An input pulse which remains low for more than one falling edge of the clock will produce incorrect output voltages. Positive (active high) input pulses can be accepted by reversing the connections to pins 14 and 15. Figure 17 shows a digital conditioning circuit which will accept any input duty cycle and provide the proper pulse width to the comparator. Each rising edge at this circuit’s input generates the required negative pulse at the inverting comparator input. The noninverting comparator is driven by a complementary signal. tor. Figure 18 shows the output ripple and settling time as a function of the CINT value. The ripple frequency is equal to the input frequency. Its magnitude can be reduced by using a large integrator capacitor value, but at the sacrifice of slow settling time at the voltage output in response to an input frequency change. The settling time constant is equal to RIN x CINT. A better compromise between output ripple and settling time can be achieved by using a moderately low integrator capacitor value and adding a low-pass filter on the analog output. The cutoff frequency of the filter should be made below the lowest expected input frequency to the frequency-to-voltage converter. The integrator amplifier output is designed to drive up to 10,000pF and 5kΩ loads in frequency-to-voltage mode. This allows driving long lines in a large system. Ripple voltage in the voltage output is unavoidable and is inversely proportional to the value of the integrator capaci- The system in Figure 20 makes use of both voltage-tofrequency and frequency-to-voltage modes to send a signal across an optically isolated barrier. This technique is useful not only for providing safety in the presence of high voltages, but also for creating high noise rejection in electrically noisy environments. The use of a common clock frequency causes the two devices to have complementary transfer functions, which minimizes errors. Frequency Response (dB) 0 –10 –20dB/decade slope –20 Optical coupling is facilitated by use of the output one-shot feature. The output pulse is shortened (see “Shortened Output Pulses”) to allow for the relatively slow turn-off time of the LED. The timing diagram in Figure 19 shows how the accumulated delay of both optical couplers could produce too long an input pulse for the frequency-to-voltage converter, VFC2, of Figure 20. –30 –40 ●●● –50 1/10T 1/T 10/T Frequency (T = Integrating Period) An output filter is used to reduce the ripple in the output of VFC2. In order to most effectively filter the output, both input and output VFCs are offset. By connecting R1 to VREF, FIGURE 15. Frequency Response of an Integrating Analogto-Digital Converter. VOUT C INT 5 4 Clock Input f IN 14 +15VDC 1 10 11 +VCC R IN 7 Clocked Logic No Connection Required Output One-Shot 6 12 5V Reference –VCC 13 15 –VCC 9 16 +15VDC Clock 8 –15VDC +VCC 0V– +VCC f IN (Preferred) 0V– 200ns 200ns f IN (Limits) Minimum Input Pulse 200ns Maximum Input Pulse FIGURE 16. Circuit and Timing Diagram of a Frequency-to-Voltage Converter. ® VFC100 12 200ns 4013 Dual “D” (VIN =13V max) Logic “1” f IN 0–100kHz D Q D Q C C Q Clock +15VDC R VOUT 5 1nF 14 4 0.1µF 10 1 11 +VCC 7 R IN Clocked Logic Output One-Shot 6 12 5V Reference –VCC 13 15 –VCC 9 16 +VCC 8 –15VDC 0.1µF Clock f IN Q1 Q2 FIGURE 17. Digital Timing Input Conditioning Circuit for Frequency-to-Voltage Operation. 100 f FS = 100kHz f FS 10kHz 100 Settling Time 1 10 f FS 1MHz 0.1 1 0.01 0.001 100pF 0.1 1000pF 0.01µF 0.1µF 1µF Settling Time to 0.1% (ms) Ripple Voltage (Vp-p) 10 a high speed clock so that available clock edges come more frequently. This would also create a high full-scale frequency, but the technique shown in Figure 21 offers an alternative. A high speed clock is used to produce high resolution of the output pulse position, but a low full-scale frequency can be programmed. 1000 When an output pulse is generated, the next rising edge of the high frequency clock is delayed for a programmable number of clock counts. Since the integrator reset period (which sets the full-scale range) is determined by the time from rising edge to rising edge at the VFC’s clock input once the comparator is tripped, the effective clock frequency is fCLOCK/16. The circuit shown can be programmed for an N from 2 to 16. Since an output pulse must propagate through the VFC before the next rising edge of the clock arrives, maximum clock frequency is limited by the delay time shown in the timing diagram. 0.01 10µF C INT FIGURE 18. Frequency-to-Voltage Mode Output Ripple and Settling Time vs Integrator Capacitance. an accurate offset is created in the voltage-to-frequency function. Zero volts input now creates a 10kHz output. This offset is subtracted in the frequency-to-voltage conversion on the output side, by VREF and R5. With output pulses now able to align with greater resolution, the output has lower phase jitter. Using this technique, the output is suitable for ratiometric (period measurement) type counting. This counting technique achieves the maximum possible resolution for short gate periods (see Burr-Brown Application Note AN-130). MORE PULSE POSITION RESOLUTION Since output pulses must always align with clock edges, the instantaneous output frequency is quantized and appears to have phase jitter. This effect can be greatly reduced by using Mylar®, Teflon® Du Pont Co. ® 13 VFC100 CK 0 CK 1 f0 f1 Input Pulse Loaded Here Must Be High Here FIGURE 19. Timing Diagram and Oscilloscope Trace of Isolated Voltage-to-Frequency/Frequency-to-Voltage System. C4 200kHz Clock CK0 0.02µF R6 R7 11.3kΩ 11.3kΩ 1kHz Low-Pass Filter A1 OPA111 C5 0.01µF +15VDC C3 0.1µF 4 14 5 0.1µF 1 10 11 +VCC +15VDC +8V VOUT 0 to 5V 2.2kΩ 7 NC R IN Output One-Shot Clocked Logic 6 1.8kΩ 12 R5 100kΩ 5V Reference OC1 HCPL-2731 –VCC –VCC Optical Coupler 13 15 9 16 +15VDC 0.05µF 8 0.1µF –15VDC CK1 +15VDC VIN = 0 to 5V +8V 0.1µF C1 2.2kΩ 1.8kΩ 0.1µF 4 14 5 1 10 11 +VCC f1 7 RIN Clocked Logic Output One-Shot 10kΩ 6 12 OC 2 HCPL-2731 Optical Coupler RIN 100kΩ 5V Reference –VCC –VCC 13 15 16 C2 250pF 9 8 0.1µF –8V +8V FIGURE 20. Circuit Diagram of Isolated Voltage-to-Frequency/Frequency-to-Voltage System. ® VFC100 14 Data “16” Logic “1” 5 ±1% Range 7 CK 1 10 11 f OUT 0 to 50kHz Output One-Shot Clocked Logic 20kΩ 6 12 5V Reference –VCC 13 15 –VCC 9 16 8 +15VDC 1.6MHz Clock +VL 0.1µF +VCC R1 500Ω 14 U/D RC Load +15VDC 0.1µF 4 74LS191 C C1 0.1µF R2 2MΩ 0 to 10V Input Data TTL 1.6MHz Clock 1 2 3 4 5 6 7 8 9 10 11 12 0.1µF –15VDC 13 14 15 16 CK fO ≈ 300ns FIGURE 21. Circuit Diagram for Increased Pulse Position Resolution. ® 15 VFC100