® VFC121 Precision Single Power Supply VOLTAGE-TO-FREQUENCY CONVERTER FEATURES APPLICATIONS ● SINGLE SUPPLY OPERATION: +4.5V to +36V ● fO = 1.5MHz max ● INTEGRATING A/D CONVERSION ● ANALOG SIGNAL TRANSMISSION ● PHASE-LOCKED LOOP VCO ● LOW NONLINEARITY: 0.03% max at 100kHz, 0.1% max at 1MHz ● GALVANICALLY ISOLATED SYSTEMS ● HIGH INPUT IMPEDANCE ● VOLTAGE REFERENCE OUTPUT ● THERMOMETER OUTPUT: 1mV/°K DESCRIPTION 36V may be used. A 2.6V reference voltage output may be used to excite sensors or bias external circuitry. A thermometer output voltage proportional to absolute temperature (°K) may be used as a temperature sensor or for temperature compensation of applications circuits. The VFC121 is a monolithic voltage-to-frequency converter consisting of an integrating amplifier, voltage reference, and one-shot charge pump circuitry. High-frequency complementary NPN/PNP circuitry is used to implement the charge-balance technique, achieving speed and accuracy far superior to previous single power supply VFCs. Frequency output is an open-collector transistor. A disable pin forces the output to the high impedance state, allowing multiple VFCs to share a common transmission path. The high-impedance input accepts signals from ground potential to VS – 2.5V. Power supplies from 4.5V to +5V +VS C INT = 2700pF 12 10 9 Ground (Optional) 13 2 RPULL UP Integrator Comparator VIN = 0 to +2V VPULL UP 14 11 RBIAS = 8kΩ (Optional) One Shot VREF f OUT = 0 to 100kHz 8 IREF R TRIM VREF RIN = 8kΩ RIN 4 6 3 5 COS = 1200pF 2.6V VT International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1989 Burr-Brown Corporation PDS-971A Printed in U.S.A. March, 1992 SPECIFICATIONS ELECTRICAL At TA = +25°C, VS = +5V, and RIN = 8kΩ, unless otherwise noted. VFC121AP PARAMETER CONDITIONS ACCURACY Nonlinearity: fFS = 100kHz fFS = 1MHz Gain Error: fFS = 100kHz Gain Drift: fFS = 100kHz Relative to VREF PSRR MIN COS 1200pF, CINT = 2700pF COS 68pF, CINT = 270pF COS 1200pF, CINT = 2700pF TMIN to TMAX +VS = +5V to +36V INPUT Minimum Input Voltage Maximum Input Voltage Impedance IBIAS VOS VOS Drift TYP VFC121BP MAX MIN TYP 0.05 0.1 10 80 100 0.025 0 VS – 2.5 10 TMIN to TMAX OPEN COLLECTOR OUTPUT VSAT ILEAKAGE VS – 2 100 150 300 10 IPULL UP = 10mA VPULL UP = 5V VPULL UP = 36V Fall Time Delay to Rise Settling Time 2.6 IO = 0 to 10mA VS = +5V to +36V RL = 100kΩ 0.8 COMPARATOR INPUT IBIAS Trigger Voltage Input Voltage Range 2.61 * 100 10 10 Short Circuit Protected 2.9 0 DISABLE INPUT VHIGH (Disabled) VLOW I HIGH (Disabled) I LOW 0.03 0.1 * 40 40 * %FS %FS %FS ppm/°C ppm/°C %/V * V V MΩ nA µV µV/°C * 400 * * * * * V µA µA ns ns * 50 * * V ppm/°C mV mV * V * µA V V * * 2.9 TA = +25°C TMIN to TMAX * * +1 2.6 THERMOMETER VT VT Slope UNITS (1) 2.59 INTEGRATOR AMPLIFIER OUTPUT Output Voltage Range 300 800 * * * 100 * 0.4 1 10 100 100 RPULL UP = 470Ω To Specified Linearity for Full Scale Input Step REFERENCE VOLTAGE Voltage Voltage Drift Load Regulation PSRR Current Limit * * MAX * 298 1 * * 2 * 0.8 VHIGH = 2V VLOW = 0.8V 4.5 TEMPERATURE RANGE Specified Storage 5 7.5 –25 –40 V V µA µA * 10 10 POWER SUPPLY Voltage Current mV mV/°K * * 36 10 * +85 +125 * * * * * * V mA * * °C °C * Same specification as VFC121AP. NOTE: (1) One pulse of new frequency plus 1µs. ORDERING INFORMATION MODEL PACKAGE LINEARITY ERROR, MAX (fS = 100kHz) VFC121AP VFC121BP Plastic DIP Plastic DIP 0.05% 0.03% TEMPERATURE RANGE –25°C to +85°C –25°C to +85°C 1–24 25–99 100+ The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® VFC121 2 PIN CONFIGURATION PIN CONFIGURATION PIN # Top View NC 1 14 f OUT Disable 2 13 +VS VT 3 12 –V IN Gnd Sense 4 11 +V IN C OS 5 10 Int Out VREF 6 9 Comp In NC 7 8 NAME DESCRIPTION 1 NC Not Connected 2 Disable Input logic Low for normal operation. Input logic High to disable the VFC121. Has internal pulldown, for normal operation if not connected. 3 VT Temperature compensation voltage proportional to absolute temperature. Typically 298mV at room temperature (298°K), with a change of 1mV per °C (°K). 4 Gnd Sense Defines ground for the internal voltage reference. 5 COS One-shot capacitor is connected between here and ground to set full scale output frequency. 6 VREF Output from the internal band-gap voltage reference, typically 2.6V. Can be used externally to set levels or excite sensors. 7 NC Not Connected 8 Gnd Ground Gnd ABSOLUTE MAXIMUM RATINGS Power Supply Voltage (+VS) ................................................................ 40V fOUT Sink Current ............................................................................... 20mA Comparator In Voltage .......................................................... –0.5V to +3V Enable Input ........................................................................... –0.3V to +VS Integrator Common-Mode Voltage ..................................... 0V to +VS – 2V Integrator Differential Input Voltage ................................... –0.3V to +0.3V VREF Out (short-circuit) ................................................................. Indefinite Operating Temperature Range ......................................... –40°C to +85°C Storage Temperature ...................................................... –40°C to +125°C Lead Temperature (soldering, 10s) ................................................ +300°C Stresses above these ratings may permanently damage the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 9 Comp In Comparator In 10 Int Out Integrator Out 11 +VIN Non-inverting input of the integrating op amp. The input signal is applied here. 12 –VIN Inverting input of the integrating op amp. CINT is connected between here and the integrator output (pin 10), and RIN is connected between here and ground. 13 +VS Supply voltage connected here. Range is +4.5V to +36V. 14 fOUT Frequency output pin. This is the output of an open-collector transistor, and an external pullup circuit should be used to generate the appropriate logic levels. PACKAGE INFORMATION MODEL VFC121AP VFC121BP PACKAGE PACKAGE DRAWING NUMBER(1) 14-Pin Plastic DIP 14-Pin Plastic DIP 010 010 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ® 3 VFC121 TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = +5V, and RIN = 8kΩ, unless otherwise noted. FREQUENCY COUNT REPEATABILITY vs COUNTER GATE TIME JITTER vs FULL SCALE FREQUENCY 700 Frequency Repeatability (%) 0.001% Jitter (ppm) 600 500 400 300 fFS = 100kHz fFS = 1MHz 0.0001% 0.00001% 10 4 10 5 10 6 10 7 10 1 100 FULL SCALE FREQUENCY vs EXTERNAL ONE-SHOT CAPACITOR NON-LINEARITY vs FULL-SCALE FREQUENCY 1 Non-Linearity (% of FSR) Full Scale Frequency (Hz) 10 7 10 6 10 5 10 4 0.1 0.01 0.001 10 100 1000 10000 10 4 10 External One-Shot Capacitor (pF) 0.1 500kHz 0 250kHz 10kHz 0.2 0.4 0.6 1 1.2 1.4 1.6 1.8 2.58 2.56 NOTE: The VREF output is short-circuit protected. 2.54 0 2 Input Voltage (V) 2 4 6 8 10 12 Output Current (mA) ® VFC121 7 2.52 –0.1 0.8 10 2.6 VREF (V) 1MHz 0.02 Linearity Error (% of FSR) for 1.5MHz Full Scale Frequency 0.2 0 6 2.62 0.04 –0.02 10 REFERENCE VOLTAGE vs REFERENCE LOAD CURRENT 1.5MHz 0 5 Full-Scale Frequency (Hz) NON-LINEARITY vs INPUT VOLTAGE Linearity Error (% of FSR) 1000 Time (ms) Full Scale Frequency (Hz) 4 14 16 18 20 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = +5V, and RIN = 8kΩ, unless otherwise noted. QUIESCENT CURRENT vs TEMPERATURE FULL SCALE GAIN DRIFT vs TEMPERATURE 10 6 9.5 5 9 4 fFS = 1MHz 8.5 Change (%) Quiescent Current (mA) fFS = 1.5MHz VS = +36V 8 fFS = 500kHz 3 fFS = 200kHz 2 fFS = 100kHz VS = +12V 7.5 1 fFS = 10kHz VS = +5V 7 –50 0 –25 0 25 50 75 100 125 0 –25 Ambient Temperature (°C) 25 50 75 100 Ambient Temperature (°C) THEORY OF OPERATION for the duration of the one-shot period, TOS. This switched current causes the output of the integrator to ramp negative. The VFC121 uses a charge-balance technique to achieve high accuracy. The basic architecture is shown in Figure 1. An analog integrator at the front end, consisting of a precision op amp and a feedback capacitor, CINT, provides a true integrating approach for improved noise immunity. Use of the non-inverting input of the op amp for the analog input provides a high input impedance to the user. When the one-shot times out, the output of the VFC121 is reset High, the one-shot is reset, and IREF is switched to the output of the integrating op amp. (This causes the output of VREF (2.6V) Integrator Output (pin 10) The integrator’s output is proportional to the charge stored on CINT plus the analog input voltage. An input voltage, VIN, forces a current through RIN of VIN/RIN, which also flows through CINT. This current through CINT causes the integrator output to ramp positive. (Refer to the timing diagram in Figure 2.) Effect of a smaller CINT 1/ fOUT fOUT When the output of the integrator ramps to VREF, the comparator trips, driving the output of the VFC121 Low, and triggering the one-shot. The tripping of the comparator also connects the reference current, IREF, to the integrator input (pin 14) FIGURE 2. Timing Diagram. +VS C INT 12 10 9 13 2 Integrator Comparator VIN 14 11 One Shot VREF RIN f OUT 8 IREF VREF 4 6 3 5 COS VREF VT FIGURE 1. VFC121 Architecture. ® 5 VFC121 +5V +VS C INT = 2700pF 12 10 9 Ground (Optional) 13 2 RPULL UP Integrator Comparator VIN = 0 to +2V VPULL UP 14 11 RBIAS = 8kΩ (Optional) One Shot VREF f OUT = 0 to 100kHz 8 IREF R TRIM VREF RIN = 8kΩ RIN 4 6 3 5 COS = 1200pF 2.6V VT FIGURE 3. 2V Full Scale Input, 100kHz Full Scale Output. the integrating op amp to see a constant current, reducing errors that might occur if the load were unbalanced.) In this state, the output of the integrator resumes a positive ramp, restarting the cycle. tor output. Since the one-shot period is unchanged, the duty cycle of the output increases. Stray capacitance at the COS pin typically adds about 60pF to the capacitance of the external COS, which accounts for the adjustment in the above equation. This usually becomes negligible as the required output frequency is reduced, and COS is increased. The output frequency is regulated by the balance of current (or charge) between the current VIN/RIN and the timeaveraged reset current. The size of the integrating capacitor, CINT, determines the slew rate of the integrator, and thus how far down the integrator ramps during the one-shot period, but has no effect on the output frequency of the VFC121. RBIAS is included in the circuit in Figure 3 to compensate for the effects of bias currents at the input of the integrating op amp. It is optional in most applications, but when needed, RBIAS should equal RIN. The reference voltage used internally is generated from a bandgap reference, which is actively trimmed to achieve the low drift characteristics of the VFC121. To maximize flexibility of designs using the VFC121, both the bandgap reference voltage and a thermometer voltage are available externally. Table 1 indicates standard external component values for common input voltage ranges and output frequency ranges. COMPONENT SELECTION Selection of the external resistor and capacitor type is important. Temperature drift of the external input resistor and one-shot capacitor will affect temperature stability of the output frequency. NPO ceramic capacitors will normally produce the best results. Silver-mica types will result in slightly higher drift, but may be adequate in many applications. A low temperature coefficient film resistor should be used for RIN. INSTALLATION AND OPERATING INSTRUCTIONS BASIC OPERATION The VFC121 allows users a wide range of input voltages and supply voltages, and easy control of the full scale output frequency. The basic connections are shown in Figure 3, with components that generate a 100kHz output with a 2V full scale input. The integrator capacitor, CINT, serves as a “charge bucket,” where charge accumulation is induced by the input, VIN, and For other input and output ranges, the full scale input voltages and full scale output frequencies can be calculated VFS as follows: fFS = 2(RIN)(COS + 60) The full scale input current of 250µA was chosen to provide a 25% duty cycle in the output frequency. The VFC121 is designed to give optimum linearity under these conditions, but other current levels can be used without significantly degrading linearity. By reducing RIN, the integrating current is increased, increasing the positive ramp rate of the integra- RIN + RTRIM (kΩ) 2 5 10 8 20 40 FULL SCALE OUTPUT FREQUENCY (kHz) COS (pF) CINT (pF) 1500 1000 500 250 125 25 22 68 180 470 1000 4700 150 270 470 1000 2200 10,000 NOTE: Higher output frequencies can be achieved by reducing RIN. TABLE 1. Standard External Component Values ® VFC121 FULL SCALE INPUT RANGE (V) 6 When the Enable input receives a logic Low (less than 0.8V), a reset current cycle is initiated, (causing fOUT to go Low). The integrator ramps negatively and normal operation is established. The time required for the output frequency to stabilize is equal to approximately one cycle of the final output frequency plus 1µs. repeatedly reduced during the one-shot period. The size of the bucket (the capacitor value) is not critical, since it primarily determines how far below VREF the output of the integrator ramps during the one-shot period. At the same time, the capacitor used must not leak since capacitor leakage or dielectric absorption can affect the linearity and offset of the transfer function. High-quality ceramic capacitors can be used for values less than 0.01µF, but caution should be used with higher value ceramic capacitors. High-k ceramic capacitors may have voltage non-linearities which can degrade overall linearity. Polystyrene, polycarbonate, or mylar film capacitors are superior for higher capacitance values. Using the Enable input, the outputs from several VFCs can be connected to a single line. All disabled VFCs will have a high output impedance; one active VFC can then transmit on the line. Since disabled VFCs are not oscillating, they cannot interfere or “lock” with the operating VFC. Locking can occur when one VFC operates at nearly the same frequency, or a multiple, as a nearby VFC. Coupling between the two may cause them to lock to the same frequency or an exact multiple. It then takes a small incremental input voltage change on one of the VFCs to unlock them. Locking cannot occur when unneeded VFCs are disabled. During the one-shot period, the output of the integrator is ramping down. To prevent the integrating op amp from being saturated at its minimum output of 0.8V, CINT should be kept at least 1.7 x COS. OUTPUT FREQUENCY ADJUSTMENT The full scale output frequency of the VFC121 can be adjusted using a trim-pot, RTRIM in Figure 3, in series with RIN. For optimum drift vs temperature, a low temperature coefficient fixed resistor of approximately 90% of the calculated RIN requirement should be used in series with a trimpot approximately 20% of the size of the calculated RIN. The low-drift fixed resistor contributes most of the final RIN resistance, so that the effect of higher drift from the trim-pot is attenuated in the total RIN. APPLICATION INFORMATION OPERATION FROM 10kHz TO 210kHz The VFC121 is designed to provide an output frequency starting at 0Hz for a 0V input and increasing linearly to the full scale output frequency, fFS, at the full scale input voltage, VFS. For applications where low level inputs, near 0V, are critical, it may be inconvenient to have an output frequency approaching 0Hz. Figure 4 shows a circuit which transforms a 0V to 2V input level into output frequencies from 10kHz to 210kHz, by placing a resistor divider network between the input source and the VREF output of the VFC121. This produces a positive voltage at +VIN when the input to the circuit is grounded. This circuit makes use of the high input impedance at +VIN. PULL-UP RESISTOR The VFC121’s frequency output is an open-collector transistor. A pull-up resistor should be connected from fOUT to the logic supply, +VL. The output transistor is On during the one-shot period, causing the output to be logic Low. The current flowing in this resistor should be limited to 10mA to assure a 0.4V maximum logic Low. The value chosen for the pull-up resistor may depend on the full-scale frequency and capacitance on the output line. Excessive capacitance on fOUT will cause a slow, rounded rising edge at the end of an output pulse. This effect can be minimized by using a pullup resistor which sets the output current to its maximum of 10mA. The logic power supply can be any positive voltage up to +36V. The transfer function of this circuit is: fOUT – 10kHz VIN = V 100kHz To trim the circuit, first apply 2V to the analog input, and adjust R1 to give a full scale output frequency of 210kHz. Then apply 0V to the analog input, and adjust R2 until the output frequency is 10kHz. For absolute precision, it may be necessary to make several iterations trimming R1 and R2. In most cases, one iteration will be enough, since the effect of R2 on ENABLE PIN 0V to 2V If left unconnected, the Enable input will assume a logic Low level, enabling the output stage, Alternatively, the Enable input may be connected directly to ground. This pin can also be driven by standard TTL or CMOS logic. C INT = 4.99kΩ +V IN 10kHz to 210kHz 2200pF f OUT –V IN A logic High at the Enable input causes output pulses to cease. This is accomplished by interrupting the signal path through the one-shot circuitry. While disabled, all circuitry remains active and quiescent current is unchanged. Since no reset current pulses can occur while disabled, any positive input voltage will cause the integrator op amp to ramp positive and saturate at its most positive output swing of approximately VREF + 0.7V. R2 10kΩ R1 1kΩ Integrator Out 4.53k Ω Comparator In 121kΩ 2.6V V REF C OS = 1000pF C OS VFC121 NOTE: Use 1% metal film fixed resistors, Cermet® trim pots, and NPO ceramic capacitors. FIGURE 4. Offsetting the Output Frequency. ® 7 VFC121 full scale output frequency is attenuated by the divider network, which sees only a 0.6V total delta at full scale (2.6V at VREF minus 2V full scale input) as compared with a 2.6V delta at a 0V input level. IN1 Out IN2 IN3 USING THE VFC121 THERMOMETER VOLTAGE Because of the high input impedance of the VFC121 (which results from using the non-inverting input to the integrating op amp), it is relatively simple to use a standard multiplexer in front of the VFC121. One of the possible reason to multiplex the input to the VFC121 is to use it to track temperature changes in the operating environment of the electronics in a system, in addition to using the VFC121 in its normal mode to measure an analog signal. IN5 IN6 IN7 RIN = 8kΩ +V IN 2700pF –V IN 1kΩ Integrator Out 7.5k Ω Comparator In 2.6V IN8 VT FIGURE 5. Measuring System Temperature. Output Frequency – 13,650 50 ® VFC121 C INT = IN4 Figure 5 shows a way to do this. In this circuit, the normal analog input signals to be multiplexed through the VFC121 have a full scale voltage of 2V, and generate a full scale output frequency of 100kHz. To measure the electronics system temperature, the user selects the multiplexer channel connected to the thermometer voltage on pin 3. A measured output frequency from the VFC121, with the multiplexer on channel 8, now corresponds to the temperature of the electronics as follows: Temp (°C) = VFC121 HI-508A 8 f OUT C OS = 1200pF C OS