VSP2101 ® VSP 210 1 CCD SIGNAL PROCESSOR For Digital Cameras TM FEATURES DESCRIPTION ● CCD SIGNAL PROCESSING: Correlated Double Sampling Black Level Clamping –2 to +34dB Gain Ranging High SNR: 53dB The VSP2101Y is a complete digital camera IC, providing signal conditioning and 10-bit analog-to-digital conversion for the output of a CCD array. The primary CCD channel provides correlated double sampling to extract the video information from the pixels, –2dB to +34dB gain ranging with digital control for varying illumination conditions, and black level clamping for an accurate black reference. ● 10-BIT A/D CONVERSION: Up to 27MHz Conversion Rate No Missing Codes ● PORTABLE OPERATION: Low Voltage: 2.7V to 3.6V Low Power: 190mW at 3.0V ● LOW POWER: 160mW at 2.7V ● POWER-DOWN MODE: 18mW Input signal clamping and offset correction of the CDS is also performed. The stable gain control is linear in dB. Additionally, the black level is quickly recovered after gain change. An on-chip general purpose 10-bit digital-to-analog converter allows you to obtain analog control voltage for iris control. The VSP2101Y is available in a 48-lead LQFP package and operates from a single +3V supply. APPLICATIONS ● ● ● ● VIDEO CAMERAS DIGITAL STILL CAMERAS PC CAMERAS SECURITY CAMERAS REFCK DATCK WRT SD SCLK OB DAC OUT ADCK DRVDD C 10-Bit D/A Converter (DAC1) Serial Port Register A/D Timing Control 10-Bit D/A Converter (DAC0) CCD D Correlated Double Sampling Black Level Auto-Zero Log VCA +6dB +28dB 10-Bit A/D Converter Output Latch 10-Bit Digital Output CCD Out Clamp CCD R Dummy Pixel Auto- Zero A/D Reference DUMC International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1998 Burr-Brown Corporation PDS-1506B Printed in U.S.A. June, 1999 SPECIFICATIONS At TA = +25°C, all power supply voltages = +3.0V, and conversion rate = 18MHz, unless otherwise specified. VSP2101Y PARAMETER CONDITIONS MIN RESOLUTION TYP MAX 10 DIGITAL INPUT Logic Family Logic Levels UNITS Bits CMOS Logic HI Logic LO Logic HI, VIN = +3V Logic LO, VIN = 0V Logic Currents 2.5 +0.4 10 10 A/D Clock Duty Cycle Input Capacitance DIGITAL OUTPUT Logic Family Logic Levels ANALOG OUTPUT General Purpose D/A Converter Output Minimum Output Voltage Maximum Output Voltage DAC Settling TIme TRANSFER CHARACTERISTICS Differential Non-Linearity Integral Non-Linearity No Missing Codes Signal Settling Time Conversion Rate Data Latency Signal-to-Noise Ratio(1) CCD Offset Correction Range Black Clamp Level CDS Data Settling Time to ±0.1% for FS Change with RS = 40 Input Signal Level for FS Out Input Capacitance Input Time Constant 50 5 CMOS Logic HI, CL = 10pF Logic LO, CL = 10pF 2.5 +0.4 Control Data = 1023 Control Data = 0 ±0.5 2.0 Guaranteed LSB LSB 110 ns 27 5.5 53 ±150 32 MHz Clocks dB mV LSB 11 ns 20 300 mV pF ps 3.3 1.2 kΩ V 32 34 –2 ±1.0 10 dB dB dB µs +2.7 +3.0 63 190 18 Grounded Input Cap, Maximum Gain Control Data = 0 Control Data = 1023 POWER SUPPLY Rated Voltage Quiescent Current Power Dissipation Power-Down Mode TEMPERATURE RANGE Specified Range Thermal Resistance, θJA 48-Lead LQFP V V µs 500kHz From Leading Edge of DATCK Minimum Gain DATCK LOW Ambient V V 0.3 2.4 1.0 Black to Full-Scale Change to 1/4 LSB into A/D 600 INPUT CLAMP Clamp-On Resistance Clamp Level GAIN CONTROL CHARACTERISTICS Gain, max Gain, min Gain Control Linearity Gain Control Settling Time V V µA µA % pF –25 100 +3.6 V mA mW mW +85 °C °C/W NOTE: (1) SNR = 20log (full-scale voltage/rms noise). The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® VSP2101 2 ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Power Supply (+VS) ............................................................................. +6V Analog Input .............................................................. –0.3V to (+VS +0.3V) Logic Input ............................................................... –0.3V to (+VS +0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ...................................................... –40°C to +150°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) VSP2101Y " 48-Lead LQFP " 340 " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(2) TRANSPORT MEDIA –25°C to +85°C " VSP2101Y " VSP2101Y VSP2101Y/2K 50-Piece Tray Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “VSP2101Y/2K” will get a single 1000piece Tape and Reel. ® 3 VSP2101 REFP REFN AVSS6 AVSS5 AVDD6 AVDD5 DACOUT RESET AVDD4 AVDD3 CM 2.4V PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 DVSS1 1 36 WRT B10 (LSB) 2 35 SCLK B9 3 34 SD B8 4 33 AVDD2 B7 5 32 LCM B6 6 31 AVSS4 VSP2101Y B5 7 30 TP2 B4 8 29 TP1 B3 9 28 AVSS2 B2 10 27 CCD R B1 (MSB) 11 26 CCD D 17 18 19 20 DVSS3 ADCK DVDD PD PB OB 21 22 23 24 C 16 DUMC 15 DATCK 14 REFCK 13 DVSS2 25 AVSS1 DRVSS DRVDD 12 PIN DESCRIPTIONS PIN DESIGNATOR DESCRIPTION PIN DESIGNATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DVSS1 B10 (LSB) B9 B8 B7 B6 B5 B4 B3 B2 B1 (MSB) DRVDD DRVSS DVSS2 DVSS3 ADCK DVDD PD 19 PB 20 21 22 23 OB REFCK DATCK DUMC Digital Ground Bit 10, ADC Output, Least Significant Bit Bit 9, ADC Output Bit 8, ADC Output Bit 7, ADC Output Bit 6, ADC Output Bit 5, ADC Output Bit 4, ADC Output Bit 3, ADC Output Bit 2, ADC Output Bit 1, ADC Output, Most Significant Bit Digital Power Supply for Digital Outputs (B1-B10) Digital Ground for Digital Outputs (B1-B10) Digital Ground Digital Ground Clock for Digital Data Output Latch Digital Power Supply Power Down: LOW = Normal Operation HIGH = Reduced Power (digital output= 0000000000) Preblanking: LOW = ADC Output: –FS +32LSB HIGH = ADC Output: Normal Optical Black Clamp Pulse, Active LOW CDS Reference Sampling Pulse, Active LOW CDS Data Sampling Pulse, Active LOW Dummy Clamp, Active LOW 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 C AVSS1 CCD D CCD R AVSS2 TP1 TP2 AVSS4 LCM AVDD2 SD SCLK WRT 2.4V CM AVDD3 AVDD4 RESET DACOUT AVDD5 AVDD6 AVSS5 AVSS6 REFN REFP ® VSP2101 4 DESCRIPTION Capacitor for Optical Feedback Loop Analog Ground CCD Signal Input Capacitor for Dummy Feedback Loop Analog Ground Test Pin 1, Open Test Pin 2, Open Analog Ground Attenuator Common-Mode Bypass Analog Power Supply Serial Data Input for D/A Converters Clock for Serial Data Input Write Pulse for Serial Data Input, Rising Edge Trigger Attenuator Ladder Bypass ADC Common-Mode Voltage Analog Power Supply Analog Power Supply Resets DAC Registers, Active LOW D/A Converter (DAC1) Output Analog Power Supply Analog Power Supply Analog Ground Analog Ground ADC Negative Reference, Bypass to Ground ADC Positive Reference, Bypass to Ground SERIAL CONTROL DATA FORMAT FOR DAC0/DAC1 TIMING SPECIFICATIONS FOR SERIAL REGISTERS Timing Specifications = tMIN to tMAX with +3V power supply. BIT NO. DESIGNATOR 1 A1 Start Bit. Either HIGH or LOW will be acceptable. SYMBOL 2 A0 Address Bit. Selects internal DACs. LOW = DAC0, VGA control DAC HIGH = DAC1, general purpose DAC DESCRIPTION PARAMETER MIN TYP MAX UNITS tCKP Serial Clock Period 100 tCKL Serial Clock Pulse Width LOW 50 ns ns 3 D9 Digital Input Data for DAC, Bit 10 (MSB) tCKH Serial Clock Pulse Width HIGH 50 ns 4 D8 Digital Input Data for DAC, Bit 9 tSD Data Setup Time 50 ns 5 D7 Digital Input Data for DAC, Bit 8 tHD Data Hold Time 25 ns 6 D6 Digital Input Data for DAC, Bit 7 tSW Write Pulse Setup Time 100 ns 7 D5 Digital Input Data for DAC, Bit 6 tW Write Pulse Width 50 ns 8 D4 Digital Input Data for DAC, Bit 5 tWD Data Valid Delay Time 50 ns tRS Register Reset Pulse Width 50 ns tRSD Register Reset Delay Time 50 ns 9 D3 Digital Input Data for DAC, Bit 4 10 D2 Digital Input Data for DAC, Bit 3 11 D1 Digital Input Data for DAC, Bit 2 12 D0 Digital Input Data for DAC, Bit 1 (LSB) TIMING FOR SERIAL PORT WRITING tCKH tCKL SCLK tCKP Must be LOW before WRT goes HIGH tSD SD A1 A0 tHD D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 tSW tW WRT tWD Valid DATA TIMING FOR REGISTER RESET tRS RESET tRSD REGISTER DATA All Zeros TIMING FOR PREBLANKING PB Mode 5.5 Clocks ADCK 5.5 Clocks DIGITAL OUTPUT t7 t7 PB Mode ® 5 VSP2101 TIMING DIAGRAMS 9.5MHz 0ns 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns 110ns 120ns 130ns 140ns 150ns 160ns 170ns 180ns 190ns 200ns 106 RESET 56 HI CCD OUT REFCK 26 132 45 80 DATCK 26 151 96 132 79 ADCK 19 OB DUMC 159 24 127 81 OUTPUT DATA 167 88 DATA VALID DATA VALID 14MHz 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns 110ns 120ns 130ns 140ns 150ns 160ns 170ns 180ns 190ns 200ns 0ns RESET 39 HI CCD OUT REFCK 21 37 DATCK 54 69 56 21 91 161 ADCK 69 28 OB 168 208 DUMC –7 33 OUTPUT DATA 58 136 65 DATA VALID DATA VALID ® VSP2101 176 6 TIMING DIAGRAMS (CONT) 18MHz 0ns 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns 110ns 120ns 130ns 140ns 150ns 160ns 170ns 180ns 190ns 200ns RESET 27.7 55.5 HI CCD OUT REFCK 18 32 DATCK 46 18 60 46 130 74 ADCK OB 24 64 DUMC 48 OUTPUT DATA 55 DATA VALID DATA VALID DATA VALID CDS/ADC TIMING DIAGRAM 27MHz Feedthrough Data Output Interval CDS Input (CCD Output) N N+1 N+2 t1 REFCK (Pin 21) t0 t3 DATCK (Pin 22) t2 t6 ADCK (Pin 16) DIGITAL OUTPUT (Pins 2-11) t4 t5 N-7 t7 N-6 N-5 SYMBOL PARAMETER MIN TYP t0 t1 t2 t3 t4, t5 t6 t7 REFCK Pulse Width REFCK Samling Delay DATCK Pulse Width DATCK Sampling Delay ADCK Pulse Width ADCK Delay Output Data Delay(1) 11 1.5 11 1.5 18.5 0 7.1 14 2 14 2 27 13 8.3 MAX UNITS 26 9.5 ns ns ns ns ns ns ns NOTE: (1) CLOAD = 5pF. ® 7 VSP2101 TYPICAL HORIZONTAL INTERVAL TIMING CCD Dummy Pixel Video Video Blanking Interval Optical Black OB DUMC PB OUTPUT Black Level Video Video TYPICAL PERFORMANCE CURVES At TA = +25°C, all power supply voltages = +3.0V, and conversion rate = 18MHz, unless otherwise specified. VCA CHARACTERISTICS QUIESCENT CURRENT vs POWER SUPPLY 40 100 35 Quiescent Current (mA) 30 20 15 10 2.7V 3.0V 3.6V 3.3V 5 0 –5 60 40 20 0 1023 974 926 877 828 779 731 682 633 585 536 487 438 390 341 292 244 195 146 97 49 0 2.7 3.0 Power Supply Voltage (V) DAC0 Code (LSB) DAC1 ANALOG OUTPUT 3.0 2.5 Analog Output (V) Gain (dB) 25 80 2.0 1.5 1.0 .5 1023 768 512 DAC1 Code (LSB) ® VSP2101 8 256 0 3.3 CORRELATED DOUBLE SAMPLER (CDS) THEORY OF OPERATION The CDS removes low frequency noise from the output of the image sensor. Refer to Figure 2 which shows a block diagram of the CDS. The output from the CCD array is sampled during the reference interval as well as during the data interval. Noise that is present at the input and is of a period greater than the pixel interval will be eliminated by subtraction. The VSP2101 is an integrated circuit that contains many of the key features associated with the processing of analog signals in a video camera or a digital-still camera. Figure 1 shows a simplified block diagram of the VSP2101. The output from the CCD array is first sent to a Correlated Double Sampler (CDS), then a voltage-controlled attenuator with a logarithmic control characteristic, and an output amplifier prior to being applied to the input of a 10-bit A/D converter. The VSP2101 employs a three track/hold correlated double sampler architecture. Track/Hold 2 is sampled during the reference interval by the REFCK signal. Track/Hold 3 is resampled at the same time that the data Track/Hold 1 is sampled by the DATCK signal. This is done to remove large transients from Track/Hold 2 that results from a portion of the reset transient being present during the acquisition time of this track and hold. The output of Track/Hold 2 is buffered by a voltage follower. Two calibration cycles are employed to reduce the offset variation of the VSP2101. During the dummy pixel time, an input auto-zero circuit is activated that eliminates the offset of the correlated double sampler. During the optical black timing interval, another auto-zero circuit is employed to eliminate the offset associated with the output amplifier and the remaining offset from the CDS. Dummy Feedback Loop Black Level Auto-Zero Loop ADCK OB DUMC CDS CCD Input 10-Bit 27MHz A/D VCA Digital Output Output Amplifier Clamp REFCK DATCK Gain Control FIGURE 1. Simplified Block Diagram of VSP2101. Data Sampling Channel CCD Input T/H1 To VCA Reference Sampling Channel T/H3 T/H2 1V DUMC REFCK DATCK FIGURE 2. Block Diagram of Correlated Double Sampler. ® 9 VSP2101 DIFFERENCE AMPLIFIER pixel auto-zero loop is in operation. The duty cycle (D) must be considered as the loop operates in a sampled mode. Operation of the dummy auto-zero loop is activated by the DUMC signal that happens once during each horizontal line interval. The correlated double sampler function is completed when the output of the data and reference channel are sent to the difference amplifier where the signals are subtracted. In addition to providing the difference function, the difference amplifier amplifies the signal by a factor of 2 which helps to improve the overall signal-to-noise ratio. The difference amplifier also generates a differential signal to drive the voltage-controlled attenuator. TIMING The REFCK and DATCK signals are used to operate the CDS as previously explained. These same two signals are also used by internal timing circuitry to create the necessary timing signals for the A/D. The output from the A/D is read out to external circuitry by the ADCK signal. DUMC is used to activate the dummy pixel auto-zero loop and OB is used to activate the black level auto-zero loop. The input digital timing signals REFCK, DATCK, DUMC and OB are capable of being driven from either 3V or 5V logic levels. INPUT CLAMP The output from the CCD array is capacitively coupled to the VSP2101. To prevent shifts in the DC level from taking place due to varying input duty cycles, the input capacitor is clamped during the dummy pixel interval by the REFCK signal and the DUMC signal. A P-channel transistor is used for this input clamp switch to allow a 2V negative change at the input that would bring the signal below ground by 1. Under typical conditions, the bias at the input to the VSP2101 is at 1V. VOLTAGE-CONTROLLED ATTENUATOR To maximize the dynamic range of the VSP2101, a voltagecontrolled attenuator is included with a control range from 0dB to –34dB. The gain control has a logarithmic relationship between the control voltage and the attenuation. The attenuator processes a differential signal from the difference amplifier to improve linearity and to reject both power supply and common-mode noise. The output from the attenuator is amplified by 28dB prior to being applied to the A/D. A typical gain control characteristic of the VSP2101 is shown in the typical performance curve, “VCA Characteristics”. DUMMY PIXEL AUTO-ZERO LOOP The output from the data and reference channel is processed by the previously mentioned difference amplifier. The differential output from the difference amplifier is sent to both the voltage-controlled logarithmic attenuator and to an error amplifier. The error amplifier amplifies and feeds a signal to the difference amplifier to drive the offset measured at the output of the difference amplifier to zero. A block diagram of this circuit is shown in Figure 3. This error amplifier serves the purpose of reducing the offset of the CDS to avoid a large offset from being amplified by the output amplifier. BLACK LEVEL AUTO-ZERO LOOP The black level auto-zero loop amplifies the difference between the output of the output amplifier and a reference signal during the optical black timing interval. This difference signal is amplified and fed back into the output amplifier to correct the offset. In doing so, the output level of the entire CCD channel can be controlled to be approximately – FS + 32LSBs under zero input signal conditions. The black level auto-zero loop is activated by the OB timing signal. The effective time constant of this loop is given by: T = RC AD where R is 10kΩ, C is an external capacitor connected to pin 27 (CCD R), A is the gain of the error amplifier with a value of 50, and D is the duty cycle of the time that the dummy Figure 4 shows a block diagram of the black level auto-zero loop. The loop time constant is given by: T= To VCA CCDIN C (GM) (D) CDS Output Amplifier From VCA A To ADS 32LSB Error Amplifier GM R CCD R Error Amplifier C C C DUMCK OB FIGURE 3. Block Diagram of Dummy Pixel Loop. FIGURE 4. Black Level Auto-Zero Loop. ® VSP2101 10 where C is the external filter capacitance applied to pin 24 (C), GM is .001Ω and D is the duty cycle of the time that the black level auto-zero loop is in operation. The duty cycle (D) must be considered as the loop operates in a sampled mode. Operation of the black level auto-zero loop is activated by the OB signal that happens once during each horizontal line interval. DECOUPLING AND GROUNDING CONSIDERATIONS The VSP2101 has several supply pins, one of which is dedicated to supply only the digital output driver (pin 12, DRVDD). The remaining supply pins are not, as is often the case, divided into analog and digital supply pins since they are internally connected on the chip. For this reason, it is recommended that the VSP2101 be treated as an analog component and be powered from the analog supply only. Digital supply lines often carry high levels of wide band noise which can couple back into the VSP2101 and limit performance. A/D CONVERTER The A/D converter utilizes a pipline architecture. The fully differential topology and digital error correction guarantee 10-bit resolution. The A/D converter circuitry includes a reference circuit that provides bias voltages for the entire system. Figure 5 shows the recommended decoupling scheme for the VSP2101. In most cases, 0.1µF ceramic chip capacitors are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual pin. Therefore, they should be located as close as possible to the pins. In addition, one larger capacitor (1µF to 22µF) should be placed on the PC board in proximity of the VSP2101. SERIAL INTERFACE AND DACs The VSP2101 incorporates two identical 10-bit DACs (DAC0 and DAC1). DAC0 is for controlling the amount of attenuation of the log Voltage Controlled Attenuator (VCA) and DAC1 is for user-defineable options such as iris control. The input data for these DACs are set by the written data through the serial interface. The serial port has an 12-bit register which is controlled by four signals (SD, SCLK, WRT, RESET). SD is the serial data input, SCLK is the clock for the serial data, WRT pulse takes the serial register data into another internal parallel register at the rising edge, RESET resets all the registers’ data to zeros asynchronously when RESET = LOW. The serial register uses master-slave dual flip-flops and the master flip-flop receives the input data at the rising edge of SCLK and transmits this data into the slave at the falling edge of SCLK. Therefore, the clock SCLK must be normally LOW. OTHER RECOMMENDATIONS DRVDD is a power supply used exclusively for the digital output driver and should not be connected to AVDD and DVDD, even if the power supply voltage is the same. The voltage level difference between DRVDD, AVDD, and DVDD should be kept less than 0.3V. If your PC board has analog and digital ground, AVSS, DVSS, and DRVSS should be connected to analog ground. DEMONSTRATION BOARD A demonstration board, DEM-VSP2101, is available to assist in the inital evaluation of the circuit performance using the VSP2101. The schematic of the DEM-VSP2101 is shown in Figure 5. When the DAC input data is all zeros, this corresponds to a maximum output voltage of 2.4V. In a similar manner, all ones correspond to a DAC output voltage of 0.3V. The VCA attenuation is at a minimum—which is the same as the channel gain being a maximum—when the DAC voltage is at 2.4V. The serial data format and the related signal timing are shown page 5. When the input serial data is longer than 12 bits, the last 12 bits become effective and the former bits are erased. When the registers are reset, the user should be careful that the channel gain setting becomes maximum and DAC1 output voltage goes to maximum. ® 11 VSP2101 27 28 29 30 TP12 TP9 TP10 21 22 19 20 TP11 VCC 15 16 C5 0.1µF 8 10 9 TP2 ADCCK VSP2101Y C9 0.1µF 8 7 6 5 4 3 2 1 B4 B5 B6 B7 B8 B9 B10 (LSB) DVSS1 2 ADCCK 3 JP1 C8 0.1µF TP13 C6 0.1µF 1 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 R8 1kΩ 10 9 8 7 VCC 1 VCC 2 1 4 37 38 39 40 41 42 43 44 45 46 47 48 C7 0.1µF 9 B3 B2 10 C11 0.1µF C12 10µF CN1 5 6 36 WRT 35 SCLK 34 SD 33 AVDD2 32 LCM 31 AVSS4 30 TP2 29 TP1 28 AVSS2 27 CCD R B1 (MSB) 11 6 7 26 CCD D 4 5 DRVDD 12 2 3 25 AVSS1 DUMC CM 25 26 R1 50Ω PD 13 14 C4 0.1µF DVDD 23 24 2 DATCK AVDD3 C 2.4V JP3 TP3 AVSS5 1 TP4 ADCK 24 23 22 21 20 19 18 17 16 15 14 13 TP5 DVSS3 AVSS6 1 TP1 TP6 OB RESET C3 0.1µF TP7 PB DACOUT 12 AVDD5 BNC CCD D TP8 VCC DVSS2 REFN C10 0.1µF CN3 REFCK AVDD4 DRVSS VSP2101 AVDD6 ® REFP FIGURE 5. DEM-VSP2101Y Schematic. 11 12 17 18 2 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 OE2 VDD IDT74FCT541 GND A8 A7 A6 A5 A4 A3 A2 A1 OE1 U3 C2 0.1µF IDT74FCT541 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 OE2 VDD C1 0.1µF U2 GND A8 A7 A6 A5 A4 A3 A2 A1 OE1 JP2 11 12 13 14 15 16 17 18 19 20 11 12 13 14 15 16 17 18 19 20 C13 10µF 6 8 7 20 22 24 26 21 23 25 39 37 35 33 31 29 40 38 36 34 32 30 28 18 19 27 16 17 14 12 15 13 11 10 4 5 9 2 3 Header 20x2 CN2 1