VSP3100 ® VSP 310 0 For most current data sheet and other product information, visit www.burr-brown.com 14-Bit, 10MHz CCD/CIS SIGNAL PROCESSOR FEATURES DESCRIPTION ● INTEGRATED TRIPLE-CORRELATED DOUBLE SAMPLER ● OPERATION MODE SELECTABLE: 1-Channel, 3-Channel, 10MSPS (typ), CCD/CIS Mode ● PROGRAMMABLE GAIN AMPLIFIER: 0dB to +13dB ● SELECTABLE OUTPUT MODES: Normal/Demultiplexed ● OFFSET CONTROL RANGE: ±400mV ● +3V, +5V Digital Output ● LOW POWER: 450mW (typ) The VSP3100 is a complete CCD/CIS image processor which operates from a single +5V supply. This complete image processor includes three Correlated Double Samplers (CDS) and Programmable Gain Amplifiers (PGA) to process CCD signals. These three channel inputs also allow Contact Image Sensor (CIS) inputs. The VSP3100 is an interface compatible with the VSP3000 which is 12-bit one-chip product. The VSP3100 can be operated from 0°C to +85°C and is available in an LQFP-48 package. ● LQFP-48 SURFACE-MOUNT PACKAGE CLP CK1 CK2 ADCCK TP0 VREF Reference Circuit CM Timing Generator Clamp REFP RINP CDS PGA REFN INN 10 5 10-Bit DAC OE VDRV Clamp GINP CDS 10 PGA 14-Bit A/D MUX 14 Digital Output Control B0-B13 (A0-A2, D0-D9) 5 10-Bit DAC Clamp BINP CDS Offset Register R G 10 PGA 3 Gain Control Register 10-Bit DAC R Configuration Register 5 8 10 P/S G B Register Port WRT B RD 5 SCLK SD VSP3100 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 2000 Burr-Brown Corporation PDS-1583A Printed in U.S.A. April, 2000 SPECIFICATIONS At TA = full specified temperature range, VCC = +5V, fADCCK = 6MHz, fCK1 = 2MHz, fCK2 = 2MHz, PGA gain = 1, normal output mode, no output load, unless otherwise specified. VSP3100Y PARAMETER CONDITIONS MIN TYP RESOLUTION MAX 14 CONVERSION CHARACTERISTICS 1-, 3-Channel CDS Mode 1-, 3-Channel CIS Mode DIGITAL INPUTS Logic Family Convert Command High Level Input Current (VIN = VCC) Low Level Input Current (VIN = 0V) Positive-Going Threshold Voltage Negative-Going Threshold Voltage Positive-Going Threshold Voltage Negative-Going Threshold Voltage Input Capacitance 19, 19, 12, 12, 20, 20, 14, 14, 21, 21, 15, 15, 22, 24 22, 24 16 16 20 20 3.80 1.25 2.20 0.80 5 0.5 DIGITAL OUTPUTS Logic Family Logic Coding Digital Data Output Rate, Max VDRV Supply Range Output Voltage, VDRV = +5V Low Level High Level Low Level High Level Output Voltage, VDRV = +3 Low Level High Level Ouput Enable Time 3-State Enable Time Output Capacitance Data Latency Data Output Delay POWER SUPPLY REQUIREMENTS Supply Voltage: VCC Supply Current: ICC (No Load) Power Dissipation (No Load) µA µA V V V V pF 800 Vp-p pF V V Ω ±4.0 0.5 Guaranteed 0.5 LSB LSB Bits LSBs rms 0.04 % FSR Gain = 0dB Gain = 0dB 0.8 1.5 % FS % FS Normal Mode Demultiplexed Mode TTL/HCT Straight Offset Binary 10 10 AGND – 0.3 0.25 Gain = 0dB, Input Grounded VCC + 0.3 0.3 +2.7 I OL = 50µA IOH = 50µA IOL = 1.6mA IOH = 0.5mA +5.3 +0.1 +4.6 +0.4 +2.4 I OL = 50µA IOH = 50µA Output Enable = LOW Output Enable = HIGH +0.1 +2.5 20 2 5 7 CL = 15pF 4.7 3-Ch 1-Ch 3-Ch 1-Ch 40 10 12 Mode Mode Mode Mode Thermal Resistance, θJA SPECIFIED TEMPERATURE RANGE 5 90 75 450 375 100 0 to +85 NOTE: (1) SNR = 20log (full-scale voltage/rms noise). ® VSP3100 3.5 10 PSRR DC ACCURACY Zero Error Gain Error MSPS MSPS CMOS Rising Edge of ADCCK Clock Start Conversion ANALOG INPUTS Full-Scale Input Range Input Capacitance Input Limits External Reference Voltage Range Reference Input Resistance DYNAMIC CHARACTERISTICS Integral Non-Linearity (INL) Differential Non-Linearity (DNL) No Missing Codes Output Noise Bits 10 10 Pins 18, Pins 18, Pins Pins UNITS 2 5.3 MHz MHz V V V V V V V ns ns pF Clock Cycles ns V mA mA mW mW °C/W °C ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY Supply Voltage(2) .............................................................................................................. +6.5V Supply Voltage Differences(3) ................................................................................... ±0.1V GND Voltage Differences(4) ........................................................................................ ±0.1V Digital Input Voltage ................................................. –0.3V to (VCC + 0.3V) Analog Input Voltage ................................................ –0.3V to (VCC + 0.3V) Input Current (any pins except suppplies) ...................................... ±10mA Operating Temperature ........................................................ 0°C to +85°C Storage Temperature ...................................................... –55°C to +150°C Junction Temperature .................................................................... +150°C Lead Temperature (soldering) ....................................................... +150°C Package Temperature (IR Reflow, peak, 10s) ............................... +260°C Package Temperature (IR Reflow, peak, 5s) ................................. +235°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTES: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) VCC, VDRV. (3) Among VCC. (4) Among AGND. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER VSP3100Y LQFP-48 340 0°C to +85°C " " " " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA VSP3100Y VSP3100Y VSP3100Y VSP3100Y/2K 250-Piece Tray Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “VSP3100Y/2K” will get a single 2000-piece Tape and Reel. DEMO BOARD ORDERING INFORMATION PRODUCT PACKAGE VSP3100Y DEM-VSP3100Y The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 VSP3100 PIN CONFIGURATION VCC VREF TP0 AGND VCC VCC VDRV AGND AGND B13 MSB B12 (A2) LQFP REFN Top View 48 47 46 45 44 43 42 41 40 39 38 37 CM 1 36 B11 (A1) REFP 2 35 B10 (A0) AGND 3 34 B9 (D9) INN 4 33 B8 (D8) RINP 5 32 B7 (D7) AGND 6 31 B6 (D6) VSP3100Y VCC 11 26 B1 (D1) CLP 12 25 B0 (D0) LSB 16 17 18 19 20 21 22 23 24 OE 15 WRT 14 VCC 27 B2 (D2) SCLK AGND 10 SD 28 B3 (D3) 13 30 B5 (D5) P/S 9 RD BINP AGND 29 B4 (D4) CK2 8 CK1 AGND ADCCK 7 VCC GINP PIN DESCRIPTIONS PIN DESIGNATOR TYPE 1 CM AO 2 REFP 3 AGND 4 INN PIN DESIGNATOR TYPE Common-Mode Voltage 25 B0 (D0) LSB DIO A/D Output (Bit 0) and Register Data (Bit 0) AO Top Reference 26 B1 (D1) DIO A/D Output (Bit 1) and Register Data (Bit 1) P Analog Ground 27 B2 (D2) DIO A/D Output (Bit 2) and Register Data (Bit 2) 28 B3 (D3) DIO A/D Output (Bit 3) and Register Data (Bit 3) 29 B4 (D4) DIO A/D Output (Bit 4) and Register Data (Bit 4) 30 B5 (D5) DIO A/D Output (Bit 5) and Register Data (Bit 5) 31 B6 (D6) DIO A/D Output (Bit 6) and Register Data (Bit 6) 32 B7 (D7) DIO A/D Output (Bit 7) and Register Data (Bit 7) AI DESCRIPTION Red/Green/Blue Channel Reference Input 5 RINP AI Red Channel Analog Input 6 AGND P Analog Ground 7 GINP AI Green Channel Analog Input 8 AGND P Analog Ground 9 BINP AI Blue Channel Analog Input 10 AGND P Analog Ground 11 VCC P Analog Power Supply, +5V 12 CLP DI Clamp Enable: “High” = Enable, “Low” = Disable 13 VCC P Analog Power Supply, +5V 14 ADCCK DI Clock for A/D Converter Digital Data Output 15 CK1 DI Sample Reference Clock 16 CK2 DI Sample Data Clock 17 AGND P Analog Ground 18 RD DI Read Signal for Registers 19 WRT DI Write Signal for Registers 20 P/S DI DESCRIPTION 33 B8 (D8) DIO B0: Demiltiplexed Mode A/D Output (Bit 8) and Register Data (Bit 8) A/D Output (Bit 0) when Demultiplexed Output Mode 34 B9 (D9) DIO B1: Demiltiplexed Mode A/D Output (Bit 9) and Register Data (Bit 9) A/D Output (Bit 1) when Demultiplexed Output Mode 35 B10 (A0) DIO B2: Demiltiplexed Mode A/D Output (Bit 10) and Register Address (Bit 0) A/D Output (Bit 2) when Demultiplexed Output Mode 36 B11 (A1) DIO B3: Demiltiplexed Mode A/D Output (Bit 11) and Register Address (Bit 1) A/D Output (Bit 3) when Demultiplexed Output Mode 37 B12 (A2) DIO B4: Demiltiplexed Mode A/D Output (Bit 12) and Register Address (Bit 2) A/D Output (Bit 4) when Demultiplexed Output Mode 38 B13 MSB DO B5: Demiltiplexed Mode A/D Output (Bit 13) A/D Output (Bit 5) when Demultiplexed Output Mode 39 AGND P 40 AGND P Analog Ground Analog Ground 41 VDRV P Digital Output Driver Power Supply Parallel/Serial Port Select 42 VCC P Analog Power Supply, +5V “High” = Parallel Port, “Low” = Serial Port 43 VCC P Analog Power Supply, +5V Analog Ground 21 SD DI Serial Data Input 44 AGND P 22 SCLK DI Serial Data Shift Clock 23 VCC P Analog Power Supply, +5V 45 46 TP0 VREF AO AIO 24 OE DI Output Enable ® VSP3100 4 47 VCC P 48 REFN AO A/D Converter Input Monitor Pin (single-ended output) Reference Voltage Input/Output Analog Power Supply, +5V Bottom Reference TIMING DIAGRAMS Timing Specifications: VCC = +5V supply and normal output mode with the specified temperature range, unless otherwise noted. 1-Channel CCD Mode Timing Pixel 1 Pixel 2 CCD Output tS tCK1W-1 tS tCK1P-1 CK1 tCK2W-1 tCK1CK2-1 tCK2CK1-1 CK2 tSET tCK1ADC tADCCK2-1 ADCCK tCNV Pixel 1 tADCW tADCW tADCP SYMBOL PARAMETER MIN TYP t CK1W-1 tCK1P-1 t CK2W-1 CK1 Pulse Width 1-Channel Mode Conversion Rate CK2 Pulse Width CK1 Falling to CK2 Rising CK2 Falling to CK1 Rising CK1 Rising to ADCCK Falling ADCCK Falling to CK2 Falling ADCCK Pulse Width ADCCK Period Sampling Delay ADCCK Rising to CK1 Rising Conversion Delay 20 100 20 15 40 20 15 41 83 10 10 40 40 166 40 tCK1CK2-1 tCK2CK1-1 tCK1ADC tADCCK2-1 tADCW tADCP tS tSET tCNV MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns 83 166 1-Channel CIS Mode Timing Pixel 1 CIS Output Pixel 2 tS tCK1W-1 tCK1P-1 CK1 tSET ADCCK tSET tCNV Pixel 1 tADCW Pixel 2 tADCW tADCP SYMBOL PARAMETER MIN TYP t CK1W-1 tCK1P-1 tADCW tADCP tS tSET tCNV CK1 Pulse Width 1-Channel Mode Conversion Rate ADCCK Pulse Width ADCCK Period Sampling Delay ADCCK Falling to CK1 Rising Conversion Delay 20 100 41 83 10 10 40 40 166 83 166 MAX UNITS ns ns ns ns ns ns ns ® 5 VSP3100 TIMING DIAGRAMS (Cont.) Timing Specifications: VCC = +5V supply and normal output mode with the specified temperature range, unless otherwise noted. 3-Channel CCD Mode Timing Pixel 1 (R/G/B) Pixel 2 (R/G/B) CCD Output tS tS tCK1W-3 tCK1P-3 CK1 tCK2W-3 tCK1CK2-3 tSET tCK2CK1-3 CK2 tSET tADCCK2-3 tCNV ADCCK (G) (R) tADCW (B) Pixel 1 (R) Pixel 1 (G) Pixel 1 (B) tADCW tADCP SYMBOL PARAMETER MIN TYP tCK1W-3 tCK1P-3 tCK2W-3 CK1 Pulse Width 3-Channel Mode Conversion Rate CK2 Pulse Width CK1 Falling to CK2 Rising CK2 Falling to CK1 Rising ADCCK Falling to CK2 Falling ADCCK Pulse Width ADCCK Period Sampling Delay ADCCK Rising to CK1 Rising Conversion Delay 20 300 20 15 70 5 41 83 10 10 40 125 500 125 tCK1CK2-3 tCK2CK1-3 tADCCK2-3 tADCW tADCP tS tSET tCNV ® VSP3100 6 83 166 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns TIMING DIAGRAMS (Cont.) Timing Specifications: VCC = +5V supply and normal output mode with the specified temperature range, unless otherwise noted. 3-Channel CIS Mode Timing CIS Output Pixel 1 (R/G/B) Pixel 2 (R/G/B) tS tCK1W-3 tCK1P-3 CK1 tADCCK1 tSET tSET tCNV ADCCK (G) (R) tADCW (B) Pixel 1 (R) tADCW Pixel 1 (G) Pixel 1 (B) tADCP SYMBOL PARAMETER MIN TYP t CK1W-3 tCK1P-3 tADCCK1 tADCW tADCP tS tSET tCNV CK1 Pulse Width 3-Channel Mode Conversion Rate ADCCK Falling to CK1 Falling ADCCK Pulse Width ADCCK Period Sampling Delay ADCCK Falling to CK1 Rising Conversion Delay 20 300 5 41 83 10 10 40 125 500 Timing for Parallel Port Writing MAX UNITS ns ns ns ns ns ns ns ns 83 166 Timing for Reading P/S P/S tPR tPR Stable A2-A0 Valid Register tDA tRW D9-D0 A2-A0 Stable tDA Stable tRW tW RD WRT tWD tRD Valid Register SYMBOL PARAMETER MIN tPR tW tWD tRW tDA Parallel Ready Time WRT Pulse Width Data Valid Time Address Setup Time Data Setup Time 20 30 TYP 50 20 30 50 50 tRH Valid D7-D0 MAX UNITS SYMBOL PARAMETER MIN TYP 30 ns ns ns ns ns tPR tDA tRW tRD tRH Parallel Ready Time Data Setup Time Address Setup Time Readout Delay Data Hold Time 20 30 20 50 50 MAX UNITS 20 1 ns ns ns ns ns ® 7 VSP3100 TIMING DIAGRAMS (Cont.) Timing Specifications: VCC = +5V supply and normal output mode with the specified temperature range, unless otherwise noted. Timing for Serial Port Writing P/S tSS tSCK tSCK ••• SCLK tSCKP tSD A2 A2-A0 A1 A0 D9 ••• D1 D0 tW tSW WRT tWD Valid Register SYMBOL PARAMETER MIN TYP tW WRT Pulse Width 30 50 tWD Data Valid Time tSD Data Ready Time UNITS ns 30 15 ns 50 ns tSCK Serial Clock Pulse Width 30 50 ns tSCKP Serial Clock Period 60 100 ns tSS Serial Ready Time 100 200 tSW WRT Pulse Setup Time 50 Timing for A/D Output (Normal Operation Mode) ns ns Timing for A/D Output (Demultiplexed Operation Mode) P/S P/S tOES tOES tOEP tOEW tOEP tOEW OE OE tOER ADCCK tDOD (n+1) tDOD Data n (14-Bit) DOUT tOER t3E (n) tDOD Data n+1 ADCCK (n+2) PARAMETER A/D Output Enable Setup Time Output Enable Time 3-State Enable Time OE Pulse Width Data Output Delay Parallel Port Setup Time TYP MAX 20 20 2 40 10 100 12 10 tDODL n (B0-B5) n+1 (B6-B13) (Hi-Z) NOTE: It is Inhibit Operation Mode that OE sets “Low” during P/S = “High” period. UNITS SYMBOL PARAMETER MIN ns ns ns ns ns ns tOES tOER t3E tOEW tDODH tDODL tOEP A/D Output Enable Setup Time Output Enable Time 3-State Enable Time OE Pulse Width Data Output Delay, High Byte Data Output Delay, Low Byte Parallel Port Setup Time 20 ® VSP3100 (n+1) (Hi-Z) (Hi-Z) MIN (n) tDODH n (B6-B13) DOUT NOTE: It is Inhibit Operation Mode that OE sets “Low” during P/S = “High” period. SYMBOL t3E (n) tDODH Data n+2 (Hi-Z) tOES tOER t3E tOEW tDOD tOEP MAX 8 TYP MAX 20 2 40 10 100 12 12 10 UNITS ns ns ns ns ns ns ns TIMING DIAGRAMS (Cont.) Timing Specifications: VCC = +5V supply and normal output mode with the specified temperature range, unless otherwise noted. Digital Data Output Sequence; 1-ch CCD Mode (B-ch: D4 = 1 and D5 = 0) Pixel (n+1) Pixel (n) Pixel (n+7) CCD Output ••• ••• CK1 tSET tSET ••• CK2 tCNV tCNV ••• ADCCK (n) CDS Output B (n) A/D Input (n+1) ••• (n+6) B (n+1) ••• B (n+6) (n+7) B (n+7) B (n) A/D Output (Normal Mode) Digital Data Output Sequence; 1-ch CIS Mode (B-ch: D4 = 1 and D5 = 0) Pixel (n+1) Pixel (n) Pixel (n+7) ••• CIS Output ••• CK1 tSET tSET tCNV tCNV ••• ADCCK S/H Output (n) A/D Input B (n) (n+1) ••• (n+6) B (n+1) ••• B (n+6) (n+7) B (n+7) B (n) A/D Output (Normal Mode) ® 9 VSP3100 TIMING DIAGRAMS (Cont.) Timing Specifications: VCC = +5V supply and normal output mode with the specified temperature range, unless otherwise noted. Digital Data Output Sequence; 3-ch CCD Mode, R > G > B Sequence Pixel (n+1) Pixel (n) Pixel (n+2) CCD Output CK1 tSET CK2 tCNV tSET tCNV ADCCK CDS Output (n+1) (n) R (n) A/D Input G (n) B (n) (n+2) R (n+1) G (n+1) B (n+1) R (n+2) R (n) A/D Output (Normal Mode) G (n) B (n) R (n+1) G (n) B (n) R (n+1) Digital Data Output Sequence; 3-ch CIS Mode, R > G > B Sequence Pixel (n+2) Pixel (n+1) Pixel (n) CIS Output CK1 tSET tCNV tSET tCNV ADCCK S/H Output (n+1) (n) R (n) A/D Input G (n) B (n) R (n+1) G (n+1) B (n+1) R (n+2) R (n) A/D Output (Normal Mode) ® VSP3100 (n+2) 10 TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = +5V supply, tADCCK = 6MHz, fCK1 = 2MHz, fCK2 = 2MHz, PGA Gain = 1, normal output mode, no load, unless otherwise specified. PGA TRANSFER FUNCITON SAMPLE QUALITY, N = 100 POWER DISSIPATION vs POWER SUPPLY 1 CH MODE 5.0 500 4.5 450 Power Dissipation (mW) 4.0 3.5 2.5 2.0 1.5 1.0 400 350 300 250 0.5 0 200 0 5 10 15 20 PGA Gain Setting 25 30 35 4.7 5 Power Supply Voltage (V) 5.3 POWER DISSIPATION vs POWER SUPPLY 3 CH MODE 500 450 Power Dissipation (mW) Gain 3.0 400 350 300 250 200 4.7 5 Power Supply Voltage (V) 5.3 ® 11 VSP3100 THEORY OF OPERATION 1-CHANNEL CIS MODE In this mode, the VSP3100 operates as a 1-channel sampler and digitizer. Unlike CDS modes, the VSP3100 takes only one sample on the falling edge of the CK1. Since only one sample is taken, CK2 is grounded in this operation. The input signal is DC coupled in most cases. Here, VSP3100 inputs are differential input. Using the Red channel as an example, RINP is the CIS input signal, and INN is the CIS common reference signal input. The same applies to the Green channel (GINP and INN) and Blue channel (BINP and INN). VSP3100 can be operated in one of the following four modes: (1) 1-Channel CCD (2) 1-Channel CIS (3) 3-Channel CCD (4) 3-Channel CIS 1-CHANNEL CCD MODE In this mode, CDS becomes CIS (act like sample-and-hold). Each channel consists of a 10-bit Offset DAC (range from –400mV to +400mV). A 3-to-1 analog MUX is inserted between the CISs and a high-performance, 14-bit A/D converter. The outputs of the CIS are then multiplexed to the A/D converter for digitization. The analog MUX is not cycling between channels in this mode. Instead, the analog MUX is connected to a specific channel, depending on the contents of D4 and D5 in the Configuration Register. In this mode, the VSP3100 processes only one CCD signal (D3 of the Configuration Register sets to “1”). The CCD signal is AC-coupled to RINP, GINP, or BINP (depending on D4, D5 of the Configuration Register). The CLP signal enables internal biasing circuitry to clamp this input to a proper voltage, so that internal CDS circuitry can work properly. The VSP3100 input may be applied as a DCcoupled input, which needs to be level-shifted to a proper DC level. The CDS takes two samples of the incoming CCD signals. The CCD reset signal is taken on the falling edge of CK1 and the CCD information is taken on the falling edge of CK2. These two samples are then subtracted by the CDS and the result is stored as a CDS output. The VSP3100 allows two types of output modes: 1) Normal (D7 of Configuration Register sets to “0”). 2) Demultiplexed (D7 of Configuration Register sets to “1”). As specified in the “1-Channel CIS Mode” timing diagram, the active period of both CK1 (tCK1B) and CK2 (tCK2B) must be in the LOW period of ADCCK. If it is in the HIGH period of ADCCK, the VSP3100 will not function properly. In this mode, only one of the three channels is enabled. Each channel consists of a 10-bit Offset DAC (range from –400mV to +400mV). A 3-to-1 analog MUX is inserted between the CDSs and a high-performance 14-bit analog-todigital converter. The outputs of the CDSs are then multiplexed to the A/D converter for digitization. The analog MUX is not cycling between channels in this mode. Instead, it is connected to a specific channel, depending on the contents of D4 and D5 in the Configuration Register. The VSP3100 allows two types of output modes: 1) Normal (D7 of Configuration Register sets to “0”). 2) Demultiplexed (D7 of Configuration Register sets to “1”). As specified in the “1-Channel CCD Mode” timing diagram, the rising edge of CK1 must be in the HIGH period of ADCCK, and at the same time, the falling edge of the CK2 must be in the LOW period of ADCCK. Otherwise, the VSP3100 will not function properly. 3-CHANNEL CCD MODE In this mode, the VSP3100 can simultaneously process triple output CCD signals. CCD signals are AC coupled to the RINP, GINP, and BINP inputs. The CLP signal enables internal biasing circuitry to clamp these inputs to a proper voltage so that internal CDS circuitry can work properly. VSP3100 inputs may be applied as a DC-coupled inputs, which need to be level-shifted to a proper DC level. The CDSs take two samples of the incoming CCD signals. The CCD reset signals are taken on the falling edge of CK1 and the CCD information is taken on the falling edge of CK2. These two samples are then subtracted by the CDSs and the results are stored as a CDS output. ® VSP3100 12 In this mode, three CDSs are used to process three inputs simultaneously. Each channel consists of a 10-bit Offset DAC (range from –400mV to +400mV). A 3-to-1 analog MUX is inserted between the CDSs and a high-performance, 14-bit A/D converter. The outputs of the CDSs are then multiplexed to the A/D converter for digitization. The analog MUX is switched at the falling edge of CK2, and can be programmed to cycle between the Red, Green, and Blue channels. When D6 of the Configuration Register sets to “0”, the MUX sequence is Red > Green > Blue. When D6 of the Configuration Register sets to “1”, the MUX sequence is Blue > Green > Red. +400mV). A 3-to-1 analog MUX is inserted between the CISs and a high-performance, 14-bit A/D converter. The outputs of the CIS are then multiplexed to the A/D converter for digitization. The analog MUX is switched at the falling edge of CK2, and can be programmed cycling between the Red, Green, and Blue channels. When D6 of the Configuration Register sets to “0”, the MUX sequence is Red > Green > Blue. When D6 of the Configuration Register sets to “1”, the MUX sequence is Blue > Green > Red. MUX resets at the falling edge of CK1. In the case of a Red > Green > Blue sequence, it resets to “R”, and in the case of a Blue > Green> Red sequence, it resets to “B”. MUX resets at the falling edge of CK1. In the case of a Red > Green > Blue sequence, it resets to “R”, and in the case of a Blue > Green > Red sequence, it resets to “B”. The VSP3100 allows two types of output modes: 1) Normal (D7 of Configuration Register sets to “0”). 2) Demultiplexed (D7 of Configuration Register sets to “1”). The VSP3100 allows two types of output modes: 1) Normal (D7 of Configuration Register sets to “0”). 2) Demultiplexed (D7 of Configuration Register sets to “1”). As specified in the “3-Channel CIS Mode” timing diagram, the falling edge of CK1 must be in the LOW period of ADCCK. If the falling edge of CK1 is in the HIGH period of ADCCK (in the timing diagram, ADCCK for sampling B-channel), the VSP3100 will not function properly. As specified in the “3-Channel CCD Mode” timing diagram, the falling edge of CK2 must be in the LOW period of ADCCK. If the falling edge of CK2 is in the HIGH period of ADCCK (in the timing diagram, ADCCK for sampling B-channel), the VSP3100 will not function properly. DIGITAL OUTPUT FORMAT The Digital Output Format is shown in Table I. The VSP3100 can be operated in one of the following two digital output modes: (1) Normal output. 3-CHANNEL CIS MODE In this mode, the VSP3100 is operated as 3-channel samplers and a digitizer. Unlike CCD modes, VSP3100 takes only one sample on the falling edge of CK1 for each input. Since only one sample is taken, CK2 is grounded in this operation. The input signals are DC coupled in most cases. Here, the VSP3100 inputs allow differential inputs. Using the Red channel as an example, RINP is the CIS input signal, and INN is the CIS common reference signal input. The same applies to the Green channel (GINP and INN) and Blue channel (BINP and INN). (2) Demultiplexed (B13-based Big Endian Format). In Normal mode, the VSP3100 outputs the 14-bit data by B0 (pin 25) through B13 (pin 38) simultaneously. In Demultiplexed mode, VSP3100 outputs the high byte (upper 8 bits) by B6 (pin 31) through B13 (pin 38) at the rising edge of ADCCK “HIGH”, then outputs the low byte (lower 6 bits) by B8 (pin 33) through B13 (pin 38) at the falling edge of ADCCK. An 8-bit interface can be used between the VSP3100 and the Digital Signal Processor, allowing for a low-cost system solution. In this mode, three CDSs become CISs (act like sample-andhold) to process three inputs simultaneously. Each channel consists of a 10-bit Offset DAC (range from –400mV to BIT B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 High Byte B13 B12 B11 B10 B9 B8 B7 B6 Low Low Low Low Low Low Low Byte B5 B4 B3 B2 B1 B0 Low Low Low Low Low Low Low Low TABLE I. Digital Output Format. ® 13 VSP3100 DIGITAL OUTPUTS The transfer function of the PGA is: The digital outputs of the VSP3100 are designed to be compatible with both high-speed TTL and CMOS logic families. The driver stage of the digital outputs is supplied through a separate supply pin, VDRV (pin 41), which is not connected to the analog supply pins (VCC). By adjusting the voltage on VDRV, the digital output levels will vary respectively. Thus, it is possible to operate the VSP3100 on a +5V analog supply while interfacing the digital outputs to 3V logic. It is recommended to keep the capacitive loading on the data lines as low as possible (typically less than 15pF). Larger capacitive loads demanding higher charging current surges can feed back to the analog portion of the VSP3100 and influence the performance. If necessary, external buffers or latches may be used, providing the added benefit of isolating the VSP3100 from any digital noise activities on the bus, coupling back high-frequency noise. In addition, resistors in series with each data line may help minimize the surge current. Their use depends on the capacitive loading seen by the converter. As the output levels change from low to high and high to low, values in the range of 100Ω to 200Ω will limit the instantaneous current the output stage has to provide for recharging the parasitic capacitances. Gain = 4/(4 – 0.1 • x) where, x is the integer representation of the 5-bit PGA gain register. Figure 1 shows the PGA transfer function plot. INPUT CLAMP The input clamp should be used for 1-channel and 3-channel CCD mode, and it will be enabled when both CLP and CK1 are set to HIGH. Bit Clamp: the input clamp is always enabled. Line Clamp: enables during the dummy pixel interval at every horizontal line, and disables during the effective pixel interval. Generally, “Bit Clamp” is used for many scanner applications, however, “Line Clamp” is used instead of “Bit Clamp” when the clamp noise is impressive. CHOOSING THE AC INPUT COUPLING CAPACITORS The purpose of the Input Coupling Capacitor is to isolate the DC offset of the CCD array from affecting the VSP3100 input circuitry. The internal clamping circuitry is used to restore the necessary DC bias to make the VSP3100 input circuitry functional. Internal clamp voltage, VCLAMP, is set when both the CLP pin and CK1 are set high. VCLAMP changes depending on the value of VREF. VCLAMP is 2.5V if VREF is set to 1V (D1 of the Configuration Register set to “0”), and VCLAMP is 3V if VREF is set to 1.5V (D1 of the Configuration Register set to “1”). PROGRAMMABLE GAIN AMPLIFIER VSP3100 has one Programmable Gain Amplifier (PGA), and it is inserted between the CDSs and the 3:1 MUX. The PGA is controlled by a 5-bit of Gain Register and each channel (Red, Green, and Blue) has its own Gain Register. The gain varies from 1 to 4.44 (0dB to 13dB), and the curve has log characteristics. Gain Register Code all “0” corresponds to minimum gain, and Code all “1” corresponds to maximum gain. PGA TRANSFER FUNCTION 14 4.0 12 3.5 10 Gain (dB) Gain PGA TRANSFER FUNCTION 4.5 3.0 2.5 8 6 2.0 4 1.5 2 0 1.0 0 5 10 15 20 PGA Gain Setting 25 0 31 FIGURE 1. PGA Transfer Plot. ® VSP3100 14 5 10 15 20 PGA Gain Setting 25 31 CHOOSE CMAX AND CMIN There are many factors that decide what size of Input Coupling Capacitor is needed. Those factors are CCD signal swing, voltage difference between the Input Coupling Capacitor, leakage current of the VSP3100 input circuitry, and the time period of CK1. Figure 2 shows the equivalent circuit of the VSP3100 inputs. As mentioned, a large CIN is better if there is enough time for the CLP signal to charge up CIN so that the input circuitry of the VSP3100 can work properly. Typically, 0.01µF to 0.1µF of CIN can be used for most cases. In order to optimize CIN, the following two equations can be used to calculate the maximum (CMAX) and minimum (CMIN) values of CIN: CMAX = (tCK1 • N)/[RSW • ln(VD/VERROR)] CK1 where tCK1 is the time when both CK1 and CLP go HIGH, and N is the number of black pixels; RSW is the switch resistance of the VSP3100 (typically, driver impedance + 4kΩ); VD is the droop voltage of CIN; VERROR is the voltage difference between VS and VCLAMP. C1 4pF CIN OP AMP VIN C2 4pF CLP CMIN = (I/VERROR) • t CK2 CK1 where I is the leakage current of the VSP3100 input circuitry (10nA is a typical number for this leakage current); t is the clamp pulse period. VCLAMP PROGRAMMING VSP3100 The VSP3100 consists of 3 CCD/CIS channels and a 14-bit A/D. Each channel (Red, Green, and Blue) has its own 10-bit Offset and 5-bit Gain Adjustable Registers to be programmed by the user. There is also an 8-bit Configuration Register, on-chip, to program the different operation modes. Those registers are shown in Table II. FIGURE 2. Equivalent Circuit of VSP3100 Inputs. In this equivalent circuit, Input Coupling Capacitor CIN, and Sampling Capacitor C1, are constructed as a capacitor divider (during CK1). For AC analysis, OP inputs are grounded. Therefore, the sampling voltage, VS, (during CK1) is: ADDRESS A2 A1 A0 VS = (CIN/(CIN + C1)) • VIN 0 0 0 0 1 1 1 1 From the above equation, we know that a larger CIN makes VS close to VIN. In other words, input signal, VIN, will not be attenuated if CIN is large. However, there is a disadvantage of using a large CIN. It will take longer for the CLP signal to charge up CIN so that the input circuitry of the VSP3100 can work properly. 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 POWER-ON DEFAULT VALUE REGISTER Configuration Register (8-bit) Red Channel Offset Register (10-bit) Green Channel Offset Register (10-bit) Blue Channel Offset Register (10-bit) Red Channel Gain Register (5-bit) Green Channel Gain Register (5-bit) Blue Channel Gain Register (5-bit) Reserved All All All All All All All “0s” “0s” “0s” “0s” “0s” “0s” “0s” TABLE II. On-Chip Registers. ® 15 VSP3100 These registers can be accessed by the following two programming modes: Power-on default value is all “0s”, set to 3-channel CCD mode with 1V internal reference, R > G > B MUX sequence, and normal output mode. (1) Parallel Programming Mode using digital data output pins, with the data bus assigned as D0 to D9 (pins 25 to 34), and the address bus as A0 to A2 (pins 35 to 37). It can be used for both reading and writing operations. However, it cannot be used by the Demultiplexed mode (when D7 of the Configuration Register is set to “1”). (2) Serial Programming Mode using a serial port, Serial Data (SD), the Serial Shift Clock (SCLK), and Write Signal (WRT) assigned. For reading/writing to the Configuration Register, the address will be A2 = “0”, A1 =“0”, and A0 = “0”. For Example: A 3-channel CCD with internal reference VREF = 1V (2V full-scale input), R > G > B sequence and normal output mode will be D0 = “0”, D1 = “0”, D2 =“0”, D3 = “0”, D4 = “x (don’t care)”, D5 = “x (don’t care)”, D6 = “0”, and D7 = “0”. For this example, bypass VREF with an appropriate capacitor (for example, 10µF to 0.1µF) when internal reference mode is used. It can be used only for writing operations; reading operations via the serial port are prohibited. Table III shows how to access these modes. OE P/S 0 0 Digital data output enabled, Serial mode enabled 0 1 Prohibit mode 1 0 Digital data output disabled, Serial mode enabled 1 1 Digital data output disabled, Parallel mode enabled Another Example: A 1-channel CIS mode (Green channel) with an external 1.2V reference (2.4V full-scale input), Demultiplexed Output mode will be D0 = “1”, D1 = “x (don’t care)”, D2 = “1”, D3 = “1”, D4 = “0”, D5 = “1”, D6 = “x (don’t care)”, and D7 = “1”. MODE TABLE III. Access Mode for Serial and Parallel Port. For this example, VREF will be an input pin applied with 1.2V. CONFIGURATION REGISTER The Configuration Register design is shown in Table IV. OFFSET REGISTER BIT LOGIC ‘0’ D0 D1 D2 D3 CCD mode VREF = 1V Internal Reference 3-channel Mode, D4 and D5 disabled D4,D5 (disabled when 3-channel) D6 D7 MUX Sequence Red > Green > Blue Normal output mode Offset Registers control the analog offset input to channels prior to the PGA. There is a 10-bit Offset Register on each channel. The offset range varies from –400mV to +400mV. The Offset Register uses a straight binary code. All “0s” corresponds to –400mV, and all “1s” corresponds to +400mV of the offset adjustment. The register code 200H corresponds to 0mV of the offset adjustment. The Power-on default value of the Offset Register is all ”0s”, so the offset adjustment should be set to –400mV. LOGIC ‘1’ CIS mode VREF =1.5V External Reference 1-channel Mode, D4 and D5 enabled D4 D5 0 0 1-channel mode, Red channel 0 1 1-channel mode, Green channel 1 0 1-channel mode, Blue channel MUX Sequence Blue > Green >Red Demultiplexed output mode PGA GAIN REGISTER PGA Gain Registers control the gain to channels prior to the digitization by the A/D converter. There is a 5-bit PGA Gain Register on each channel. The gain range varies from 1 to 4.44 (from 0dB to 13dB). The PGA Gain Register is a straight binary code. All “0s” corresponds to an analog gain of 0dB, and all “1s” corresponds to an analog gain of 13dB. PGA Transfer function is log gain curve. Power-on default value is all “0s”, so that it sets the gain of 0dB. TABLE IV. Configuration Register Design. ® VSP3100 16 OFFSET AND GAIN CALIBRATION SEQUENCE RECOMMENDATION FOR POWER SUPPLY AND GROUNDING Proper grounding, bypassing, short lead length, and the use of ground planes are particularly important for high-frequency designs. Multi-layer PC boards are recommended for the best performance since they offer distinct advantages such as minimization of ground impedance, separation of signal layers by ground layers, etc. When the VSP3100 is powered on, it will be initialized as a 3-Channel CCD, 1V internal reference mode (2V full-scale) with an analog gain of 1, and normal output mode. This mode is commonly used for CCD scanner applications. The calibration procedure is done at the very beginning of the scan. To calibrate the VSP3100, use the following procedure: It is recommended that analog and digital ground pins of the VSP3100 be joined together at the IC and connected only to the analog ground of the system. The VSP3100 has several analog supply pins (VCC), so the VSP3100 should be treated as an analog component, and all supply pins should be powered by the analog supply on your system. This will ensure the most consistent results since digital supply lines often carry high levels of noise that would otherwise be coupled into the converter and degrade the achievable performance. As the result of the high operation speed, the converter also generates high-frequency current transients and noise that are fed back into the supply and reference lines. This requires that the supply and reference pins be sufficiently decoupled with ceramic capacitors. 1. Set the VSP3100 to the proper mode. 2. Set Offset to 0mV (control code: 00H), and PGA gain to 1 (control code: 200H). 3. Scan dark line. 4. Calculate the pixel offsets according to the A/D Converter output. 5. Readjust input Offset Registers. 6. Scan white line. 7. Calculate gain. It will be the A/D Converter full-scale divided by the A/D Converter output when the white line is scanned. 8. Set the Gain Register. If the A/D Converter output is not close to full-scale, go back to item 3. Otherwise, the calibration is done. The calibration procedure is started at the very beginning of the scan. Once calibration is done, registers on the VSP3100 will keep this information (offset and gain for each channel) during the operation. ® 17 VSP3100 FIGURE 3. Demo Board Schematic (DEM-VSP3100). ® VSP3100 18