VSP VSP3200 VSP3210 320 0 www.ti.com CCD SIGNAL PROCESSOR FOR SCANNER APPLICATIONS FEATURES DESCRIPTION F INTEGRATED TRIPLE-CORRELATED DOUBLE SAMPLER F OPERATION MODE SELECTABLE: 1-Channel, 3-Channel CCD Mode, 8Msps F PROGRAMMABLE GAIN AMPLIFIER: 0dB to +13dB F SELECTABLE OUTPUT MODES: Normal/Demultiplexed F OFFSET CONTROL RANGE: ±500mV F +3V, +5V Digital Output F LOW POWER: 300mW (typ) The VSP3200 and VSP3210 are complete CCD image processors that operate from single +5V supplies. This complete image processor includes three Correlated Double Samplers (CDSs) and Programmable Gain Amplifiers (PGAs) to process CCD signals. The VSP3200 is interface compatible with the VSP3210, which is a 16-bit, one-chip product. The VSP3210 is pin-to-pin compatible with VSP3100, when in demultiplexed output mode. The VSP3200 and VSP3210 can be operated from 0°C to +85°C, and are available in LQFP-48 packages. F LQFP-48 SURFACE-MOUNT PACKAGE CLP CK1 CK2 ADCCK TP0 VREF Reference Circuit CM Timing Generator Clamp REFP RINP CDS PGA REFN AGND 10 6 10-Bit DAC OE VDRV Clamp 16-Bit A/D Converter GINP CDS 10 PGA MUX 16 Digital Output Control B0-B15 (A0-A2, D0-D9) 6 10-Bit DAC Clamp BINP PGA CDS Offset Register 10 3 Gain Control Register 10-Bit DAC R G R Configuration Register B 8 10 P/S G 6 Register Port WRT B RD 6 SCLK SD VSP3200 Copyright © 2000, Texas Instruments Incorporated SBMS012A Printed in U.S.A. November, 2000 SPECIFICATIONS At TA = 25°C, VCC = +5.0V, VDRV = +3.0V, Conversion Rate (fADCCK) = 6MHz, fCK1 = 2MHz, fCK2 = 2MHz, PGA Gain = 1, normal output mode, no output load, unless otherwise specified. VSP3200Y VSP3210Y PARAMETER CONDITIONS MIN TYP RESOLUTION MAX 16 Bits CONVERSION CHARACTERISTICS 1-Channel CCD Mode, Max 3-Channel CCD Mode, Max DIGITAL INPUTS Logic Family Convert Command High-Level Input Current (VIN = VCC) Low-Level Input Current (VIN = 0V) Positive-Going Threshold Voltage Negative-Going Threshold Voltage Input Limit Input Capacitance 0.80 AGND – 0.3 20 20 2.20 µA µA V V V pF VCC + 0.3 0.5 3.5 10 VCC + 0.3 1.75 AGND – 0.3 0.25 800 VIN = 500mV (VREF = 1.0V) PGA Gain = 0dB, Input Grounded PSRR VCC = +5V, ±0.25V DC ACCURACY Zero Error Gain Error Offset Control Range 10-Bit Control DAC Output Voltage Range DIGITAL OUTPUTS Logic Family Logic Coding Digital Data Output Rate, Max Vp-p pF V V W ±8 ±1.5 Guaranteed 8.0 LSB LSB LSBs rms 0.04 % FSR 0.8 1.5 % FS % FS ±500 mV CMOS Straight Binary Normal Mode Demultiplexed Mode VDRV Supply Range Output Voltage, VDRV = +5V Low Level High Level Low Level High Level Output Voltage, VDRV = +3V Low Level High Level Output Enable Time 3-State Enable Time Output Capacitance Data Latency Data Output Delay IOL = 50µA IOH = 50µA IOL = 1.6mA IOH = 0.5mA IOL = 50µA IOH = 50µA Output Enable = LOW Output Enable = HIGH 8 8 +2.7 +5.3 +0.1 +4.6 +0.4 +2.4 +0.1 +2.5 20 2 5 8 CL = 15pF POWER-SUPPLY REQUIREMENTS Supply Voltage: VCC Supply Current: ICC (No Load) CCD CCD CCD CCD Mode Mode Mode Mode LQFP-48 θJA 40 10 12 4.7 3-Ch 1-Ch 3-Ch 1-Ch Power Dissipation (No Load) 2 MHz MHz 5 DYNAMIC CHARACTERISTICS Integral Non-Linearity (INL) Differential Non-Linearity (DNL) No Missing Codes Output Noise TEMPERATURE RANGE Operation Temperature Thermal Resistance 8 8 CMOS Rising Edge of ADCCK Clock Start Conversion ANALOG INPUTS Full-Scale Input Range Input Capacitance Input Limits External Reference Voltage Range Reference Input Resistance UNITS 5 70 60 350 300 0 100 MHz MHz V V V V V V V ns ns pF Clock Cycles ns 5.3 V mA mA mW mW +85 °C °C/W VSP3200, 3210 SBMS012A ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage: VCC, VDRV ............................................................... +6.5V Supply Voltage Differences: Among VCC ......................................... ±0.1V GND Voltage Differences: Among GNDA ........................................ ±0.1V Digital Input Voltage ............................................... –0.3V to (VCC + 0.3V) Analog Input Voltage .............................................. –0.3V to (VCC + 0.3V) Input Current (Any Pins Except Supplies) ..................................... ±10mA Ambient Temperature Under Bias ................................. –40°C to +125°C Storage Temperature .................................................... –55°C to +125°C Junction Temperature .................................................................... +150°C Lead Temperature (soldering, 5s) ................................................. +260°C Package Temperature (IR Reflow, peak, 10s) ............................. +235°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER VSP3200Y LQFP-48 340 0°C to +85°C VSP3200Y " " " " LQFP-48 340 0°C to +85°C VSP3210Y " " " " " VSP3210Y " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA VSP3200Y VSP3200Y/2K VSP3210Y VSP3210Y/2K 250-Piece Tray Tape and Reel 250-Piece Tray Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “VSP3200Y/2K” will get a single 2000-piece Tape and Reel. DEMO BOARD ORDERING INFORMATION PRODUCT PACKAGE VSP3200Y DEM-VSP3200Y VSP3200, 3210 SBMS012A 3 PIN CONFIGURATION B10 (A0) B9 (D9) B8 (D8) B7 (D7) B6 (D6) B5 (D5) B4 (D4) B3 (D3) B2 (D2) B1 (D1) B0 (D0) LSB LQFP B11 (A1) Top View 36 35 34 33 32 31 30 29 28 27 26 25 B12 (A2) 37 24 OE B13 38 23 VCC B14 39 22 SCLK B15 (MSB) 40 21 SD VDRV 41 20 P/S VCC 42 19 WRT VSP3200Y VCC 43 18 RD AGND 44 17 AGND TP0 45 16 CK2 VREF 46 15 CK1 VCC 47 14 ADCCK AGND AGND RINP AGND 7 8 9 10 11 12 CLP 6 VCC 5 AGND 4 BINP 3 AGND 2 GINP 1 REFP 13 VCC CM REFN 48 PIN DESCRIPTIONS (VSP3200Y) 4 PIN DESIGNATOR TYPE 1 2 3 4 5 6 7 8 9 10 11 12 CM REFP AGND AGND RINP AGND GINP AGND BINP AGND VCC CLP AO AO P P AI P AI P AI P P DI 13 14 15 16 17 18 19 20 VCC ADCCK CK1 CK2 AGND RD WRT P/S P DI DI DI P DI DI DI 21 22 23 24 25 26 27 28 SD SCLK VCC OE B0 (D0) LSB B1 (D1) B2 (D2) B3 (D3) DI DI P DI DIO DIO DIO DIO DESCRIPTION Common-Mode Voltage Upper-Level Reference Analog Ground Analog Ground Red Channel Analog Input Analog Ground Green Channel Analog Input Analog Ground Blue Channel Analog Input Analog Ground Analog Power Supply, +5V Clamp Enable HIGH = Enable, LOW = Disable Analog Power Supply, +5V Clock for A/D Converter Digital Data Output Sample Reference Clock Sample Data Clock Analog Ground Read Signal for Registers Write Signal for Registers Parallel/Serial Port Select HIGH = Parallel Port, LOW = Serial Port Serial Data Input Serial Data Shift Clock Analog Power Supply, +5V Output Enable A/D Output (Bit 0) and Register Data (D0) A/D Output (Bit 1) and Register Data (D1) A/D Output (Bit 2) and Register Data (D2) A/D Output (Bit 3) and Register Data (D3) PIN DESIGNATOR TYPE 29 30 31 32 33 41 42 43 44 45 46 B4 (D4) B5 (D5) B6 (D6) B7 (D7) B8 (D8) B0 LSB B9 (D9) B1 B10 (A0) B2 B11 (A1) B3 B12 (A2) B4 B13 B5 B14 B6 B15 MSB B7 MSB VDRV VCC VCC AGND TP0 VREF DIO DIO DIO DIO DIO DO DIO DO DIO DO DIO DO DIO DO DO DO DO DO DO DO P P P P AO AIO 47 48 VCC REFN P AO 34 35 36 37 38 39 40 DESCRIPTION A/D Output (Bit 4) and Register Data (D4) A/D Output (Bit 5) and Register Data (D5) A/D Output (Bit 6) and Register Data (D6) A/D Output (Bit 7) and Register Data (D7) A/D Output (Bit 8) and Register Data (D8) A/D Output (Bit 0) when Demultiplexed Output Mode A/D Output (Bit 9) and Register Data (D9) A/D Output (Bit 1) when Demultiplexed Output Mode A/D Output (Bit 10) and Register Address (A0) A/D Output (Bit 2) when Demultiplexed Output Mode A/D Output (Bit 11) and Register Address (A1) A/D Output (Bit 3) when Demultiplexed Output Mode A/D Output (Bit 12) and Register Address (A2) A/D Output (Bit 4) when Demultiplexed Output Mode A/D Output (Bit 13) A/D Output (Bit 5) when Demultiplexed Output Mode A/D Output (Bit 14) A/D Output (Bit 6) when Demultiplexed Output Mode A/D Output (Bit 15) A/D Output (Bit 7) when Demultiplexed Output Mode Digital Output Driver Power Supply Analog Power Supply, +5V Analog Power Supply, +5V Analog Ground A/D Converter Input Monitor Pin (single-ended output) Reference Voltage Input/Output INT Ref: Bypass to GND with 0.1µF EXT Ref: Input Pin for Ref Voltage Analog Power Supply, +5V Lower-Level Reference VSP3200, 3210 SBMS012A PIN CONFIGURATION B4, B12 B3, B11 B2, B10 B1, B9 B0, B8 (LSB) NC NC NC NC NC NC LQFP B5, B13 Top View 36 35 34 33 32 31 30 29 28 27 26 25 B6, B14 37 24 OE B7, B15 (MSB) 38 23 VCC NC 39 22 SCLK NC 40 21 SD VDRV 41 20 AGND VCC 42 19 WRT VSP3210Y VCC 43 18 AGND AGND 44 17 AGND TP0 45 16 CK2 VREF 46 15 CK1 VCC 47 14 ADCCK RINP 8 9 10 11 12 CLP AGND 7 VCC AGND 6 AGND 5 BINP 4 AGND 3 GINP 2 AGND 1 REFP 13 VCC CM REFN 48 PIN DESCRIPTIONS (VSP3210Y) PIN DESIGNATOR TYPE 1 2 3 4 5 6 7 8 9 10 11 12 CM REFP AGND AGND RINP AGND GINP AGND BINP AGND VCC CLP AO AO P P AI P AI P AI P P DI 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 VCC ADCCK CK1 CK2 AGND AGND WRT AGND SD SCLK VCC OE NC NC NC NC NC P DI DI DI P P DI P DI DI P DI – – – – – VSP3200, 3210 SBMS012A DESCRIPTION Common-Mode Voltage Upper-Level Reference Analog Ground Analog Ground Red Channel Analog Input Analog Ground Green Channel Analog Input Analog Ground Blue Channel Analog Input Analog Ground Analog Power Supply, +5V Clamp Enable HIGH = Enable, LOW = Disable Analog Power Supply, +5V Clock for A/D Converter Digital Data Output Sample Reference Clock Sample Data Clock Analog Ground Analog Ground Write Signal for Registers Analog Ground Serial Data Input Serial Data Shift Clock Analog Power Supply, +5V Output Enable Should Be Left OPEN Should Be Left OPEN Should Be Left OPEN Should Be Left OPEN Should Be Left OPEN PIN DESIGNATOR TYPE 30 31 39 40 41 42 43 44 45 46 NC B0 LSB B8 B1 B9 B2 B10 B3 B11 B4 B12 B5 B13 B6 B14 B7 B15 MSB NC NC VDRV VCC VCC AGND TP0 VREF – DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO – – P P P P AO AIO 47 48 VCC REFN P AO 32 33 34 35 36 37 38 DESCRIPTION Should Be Left OPEN A/D Output (Bit 0) LSB A/D Output (Bit 8) A/D Output (Bit 1) A/D Output (Bit 9) A/D Output (Bit 2) A/D Output (Bit 10) A/D Output (Bit 3) A/D Output (Bit 11) A/D Output (Bit 4) A/D Output (Bit 12) A/D Output (Bit 5) A/D Output (Bit 13) A/D Output (Bit 6) A/D Output (Bit 14) A/D Output (Bit 7) A/D Output (Bit 15) MSB Should Be Left OPEN Should Be Left OPEN Digital Output Driver Power Supply Analog Power Supply, +5V Analog Power Supply, +5V Analog Ground A/D Converter Input Monitor Pin (single-ended output) Reference Voltage Input/Output INT Ref: Bypass to GND with 0.1µF EXT Ref: Input Pin for Ref Voltage Analog Power Supply, +5V Lower-Level Reference 5 TIMING SPECIFICATIONS VSP3200 AND VSP3210 1-CHANNEL CCD MODE TIMING Pixel 1 Pixel 2 CCD Output tS tS tCK1W-1 tCK1P-1 CK1 tCK2W-1 tCK1CK2-1 tCK2CK1-1 CK2 tCK1ADC tSET tCNV tADCCK2-1 ADCCK Pixel 1 tADCW tADCW tADCP SYMBOL PARAMETER MIN tCK1W-1 tCK1P-1 tCK2W-1 CK1 Pulse Width 1-Channel Mode Conversion Rate CK2 Pulse Width CK1 Falling to CK2 Rising CK2 Falling to CK1 Rising CK1 Rising to ADCCK Falling ADCCK Falling to CK2 Falling ADCCK Pulse Width ADCCK Period Sampling Delay ADCCK Rising to CK1 Rising Conversion Delay Data Latency, Normal Operation Mode 20 125 20 15 50 10 15 62 125 10 40 10 tCK1CK2-1 tCK2CK1-1 tCK1ADC tADCCK2-1 tADCW tADCP tS tSET tCNV DL VSP3200 TIMING FOR PARALLEL PORT READING TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns Clock Cycles 166 83 166 8 (fixed) VSP3200 TIMING FOR PARALLEL PORT WRITING P/S P/S tPR tPR Valid Register Data Stable A2-A0 tDA tRW A2-A0 Stable Stable D9-D0 tRW tDA tW RD tRD tRH WRT tWD Valid D9-D0 Valid Register Data SYMBOL PARAMETER MIN TYP tPR tDA tRW tRD tRH Parallel Ready Time Data Setup Time Address Setup Time Read Out Delay Data Hold Time 20 30 20 50 50 MAX UNITS 20 1 ns ns ns ns ns NOTES: (1) This feature is for the VSP3200 only. (2) Reading out register data through the serial port is prohibited. 6 SYMBOL PARAMETER MIN TYP tPR tW tWD tRW tDA Parallel Ready Time WRT Pulse Width Data Valid Time Address Setup Time Data Setup Time 20 30 50 20 30 50 50 MAX UNITS 30 ns ns ns ns ns NOTE: (1) This feature is for the VSP3200 only. VSP3200, 3210 SBMS012A VSP3200 AND VSP 3210 3-CHANNEL CCD MODE TIMING Pixel 1 (R/G/B) Pixel 2 (R/G/B) CCD Output tS tS tCK1W-3 tCK1P-3 CK1 tCK2W-3 tCK1CK2-3 tSET tCK2CK1-3 CK2 tSET tADCCK2-3 tCNV ADCCK (G) (R) tADCW (B) Pixel 1 (R) Pixel 1 (G) Pixel 1 (B) tADCW tADCP SYMBOL PARAMETER MIN tCK1W-3 tCK1P-3 tCK2W-3 CK1 Pulse Width 3-Channel Mode Conversion Rate CK2 Pulse Width CK1 Falling to CK2 Rising CK2 Falling to CK1 Rising ADCCK Falling to CK2 Falling ADCCK Pulse Width ADCCK Period Sampling Delay ADCCK Rising to CK1 Rising Conversion Delay Data Latency, Normal Operation Mode 20 375 20 15 112 5 62 125 10 10 40 tCK1CK2-3 tCK2CK1-3 tADCCK2-3 tADCW tADCP tS tSET tCNV DL VSP3200, 3210 SBMS012A TYP 500 83 166 8 (fixed) MAX UNITS ns ns ns ns ns ns ns ns ns ns ns Clock Cycles 7 DIGITAL DATA OUTPUT SEQUENCE: 1-Ch CCD Mode, (B-Ch: D4 = 1 and D5 = 0) Pixel (n) Pixel (n+1) Pixel (n+8) CCD Output ••• ••• CK1 tSET tSET ••• CK2 tCNV tCNV ••• ADCCK (n) CDS Output B (n) A/D Input (n+1) ••• (n+7) B (n+1) ••• B (n+7) (n+8) B (n+8) B (n) Digital Output (Normal Mode) DIGITAL DATA OUTPUT SEQUENCE: 3-Ch CCD Mode, R > G > B Sequence Pixel (n+1) Pixel (n) Pixel (n+2) CCD Output CK1 tSET CK2 tSET tCNV tCNV ADCCK CDS Output A/D Input Digital Output (Normal Mode) 8 (n+1) (n) R (n) G (n) B (n) (n+2) R (n+1) G (n+1) B (n+1) R (n+2) R (n) G (n) B (n) R (n+1) VSP3200, 3210 SBMS012A VSP3200 TIMING FOR DIGITAL DATA OUTPUT (NORMAL OUTPUT MODE) VSP3200 AND VSP3210 TIMING FOR DIGITAL DATA OUTPUT (DEMULTIPLEXED OUTPUT MODE) P/S P/S(1) tOES tOES tOEP tOEW OE OE tOER ADCCK t3E (n) (n) tDODH tOER (n+1) ADCCK tDODH tDOD n (B6-B13) n (B0-B5) PARAMETER MIN A/D Output Enable Setup Time Output Enable Time 3-State Enable Time OE Pulse Width Digital Data Output Delay, High-Byte Digital Data Output Delay, Low-Byte Parallel Port Setup Time 20 (n+2) tDOD tDOD TYP MAX 20 2 40 10 Data n (14-Bit) Digital Output B[15:0] (Hi-Z) tOES tOER t3E tOEW tDODH tDODL tOEP (n+1) n+1 (B6-B13) (Hi-Z) SYMBOL t3E (n) tDODL Digital Output B[15:0] tOEP tOEW Data n+1 Data n+2 (Hi-Z) (Hi-Z) UNITS ns ns ns ns ns ns ns 100 12 12 10 NOTES: (1) The VSP3210 has no P/S signal; tOES and tOEP specs. are not needed. (2) When in inhibit operation mode, OE sets LOW during P/S = HIGH period. SYMBOL PARAMETER MIN tOES tOER t3E tOEW tDOD tOEP A/D Output Enable Setup Time Output Enable Time 3-State Enable Time OE Pulse Width Digital Data Output Delay Parallel Port Setup Time 20 TYP MAX 20 2 40 10 100 12 10 UNITS ns ns ns ns ns ns NOTES: (1) This feature is for the VSP3200 only. (2) When in inhibit operation mode, OE sets LOW during P/S = HIGH period. VSP3200 AND VSP3210 TIMING FOR SERIAL PORT WRITING P/S(1) tSS tSCK tSCK SCLK tSCKP tSD SD A2 A1 A0 D9 • • • D1 D0 tSW WRT tW tWD Valid Register Data SYMBOL PARAMETER MIN TYP tW tWD tSD tSCK tSCKP tSS tSW WRT Pulse Width Data Valid Time Data Ready Time Serial Clock Pulse Width Serial Clock Period Serial Ready WRT Pulse Setup Time 30 50 MAX UNITS 30 15 30 60 100 50 50 50 100 200 ns ns ns ns ns ns ns NOTE: (1) VSP3210 has no P/S signal; tSS spec. is not needed. VSP3200, 3210 SBMS012A 9 THEORY OF OPERATION INTRODUCTION The VSP3200 and VSP3210 are complete mixed-signal ICs that contain all of the key features associated with the processing of the CCD line sensor output signal in scanners, photo copiers, and similar applications. See the simplified block diagram on page 1 for details. The VSP3200 and VSP3210 include Correlated Double Samplers (CDSs), Programmable Gain Amplifiers (PGAs), Multiplexer (MUX), Analog-to-Digital (A/D) converter, input clamp, offset control, serial interface, timing control, and reference control generator. The VSP3200 and VSP3210 can be operated in one of the following two modes: • 1-Channel CCD mode • 3-Channel CCD mode 1-CHANNEL CCD MODE In this mode, the VSP3200 and VSP3210 process only one CCD signal (D3 of the Configuration Register sets to “1”). The CCD signal is AC-coupled to RINP, GINP, or BINP (depending on D4 and D5 of the Configuration Register). The CLP signal enables internal biasing circuitry to clamp this input to a proper voltage, so that internal CDS circuitry can work properly. The VSP3200 and VSP3210 inputs may be applied as DC-coupled inputs, which needs to be level-shifted to a proper DC level. The CDS takes two samples of the incoming CCD signals: the CCD reset signal is taken on the falling edge of CK1, and the CCD information is taken on the falling edge of CK2. These two samples are then subtracted by the CDS and the result is stored as a CDS output. In the 1-Channel CCD mode, only one of the three channels is enabled. Each channel consists of a 10-bit offset Digital-toAnalog Converter (DAC) with a range from –500mV to +500mV. A 3-to-1 analog MUX is inserted between the CDSs and a high-performance, 16-bit A/D converter. The outputs of the CDSs are then multiplexed to the A/D converter for digitization. The analog MUX is not cycling between channels in this mode. Instead, it is connected to a specific channel, depending on the contents of D4 and D5 in the Configuration Register. The VSP3200 allows two types of output modes: • Normal (D7 of Configuration Register sets to “0”). • Demultiplexed (D7 of Configuration Register sets to “1”). The VSP3210 allows one type of output mode: • Demultiplexed (D7 of Configuration Register sets to “1”). As specified in the “1-Channel CCD Mode” timing diagram, the rising edge of CK1 must be in the HIGH period of ADCCK, and at the same time, the falling edge of the CK2 must be in the LOW period of ADCCK. Otherwise, the VSP3200 and VSP3210 will not function properly. 10 3-CHANNEL CCD MODE In the 3-Channel CCD mode, the VSP3200 and VSP3210 can simultaneously process triple output CCD signals. CCD signals are AC coupled to the RINP, GINP, and BINP inputs. The CLP signal enables internal biasing circuitry to clamp these inputs to a proper voltage so that internal CDS circuitry can work properly. The VSP3200 and VSP3210 inputs may be applied as DC-coupled inputs, which need to be level-shifted to a proper DC level. The CDSs take two samples of the incoming CCD signals: the CCD reset signals are taken on the falling edge of CK1, and the CCD information is taken on the falling edge of CK2. These two samples are then subtracted by the CDSs and the results are stored as a CDS output. In this mode, three CDSs are used to process three inputs simultaneously. Each channel consists of a 10-bit Offset DAC (range from –500mV to +500mV). A 3-to-1 analog MUX is inserted between the CDSs and a high-performance, 16-bit A/D converter. The outputs of the CDSs are then multiplexed to the A/D converter for digitization. The analog MUX is switched at the falling edge of CK2, and can be programmed to cycle between the Red, Green, and Blue channels. When D6 of the Configuration Register sets to “0”, the MUX sequence is Red > Green > Blue. When D6 of the Configuration Register sets to “1”, the MUX sequence is Blue > Green > Red. MUX resets at the falling edge of CK1. In the case of a Red > Green > Blue sequence, it resets to “R”, and in the case of a Blue > Green > Red sequence, it resets to “B”. The VSP3200 allows two types of output modes: • Normal (D7 of Configuration Register sets to “0”). • Demultiplexed (D7 of Configuration Register sets to “1”). The VSP3210 allows one type of output mode: • Demultiplexed (D7 of Configuration Register sets to “1”). As specified in the “3-Channel CCD Mode” timing diagram, the falling edge of CK2 must be in the LOW period of ADCCK. If the falling edge of CK2 is in the HIGH period of ADCCK (in the timing diagram, ADCCK for sampling B-channel), the VSP3200 and VSP3210 will not function properly. DIGITAL OUTPUT FORMAT See Table I for the Digital Output Format. The VSP3200 and VSP3210 can be operated in one of the following two digital output modes: • Normal output. • Demultiplexed (B15-based Big Endian Format). In Normal mode, the VSP3200 outputs the 16-bit data by B0 (pin 25) through B15 (pin 40) simultaneously. In Demultiplexed mode, the VSP3200 outputs the high byte (upper 8 bits) by B8 (pin 33) through B15 (pin 40) at the rising edge of ADCCK HIGH, then outputs the low byte (lower 8 bits) by B8 (pin 33) through B15 (pin 40) at the falling edge of ADCCK. VSP3200, 3210 SBMS012A The VSP3210 can be operated in Demultiplexed mode as the digital output (B13-based Big Endian Format), as shown in Table I. The VSP3210 outputs the high byte (upper 8 bits) by pin 31 through pin 38 at the rising edge of ADCCK HIGH, then outputs the low byte (lower 8 bits) by pin 31 through pin 38 at the falling edge of ADCCK (as shown in Table II). An 8-bit interface can be used between the VSP3200 and the Digital Signal Processor, allowing for a low-cost system solution. VSP3200 and VSP3210 from any digital noise activities on the bus coupling back high-frequency noise. In addition, resistors in series with each data line may help minimize the surge current. Their use depends on the capacitive loading seen by the converter. As the output levels change from LOW to HIGH and HIGH to LOW, values in the range of 100W to 200W will limit the instantaneous current the output stage has to provide for recharging the parasitic capacitances. DIGITAL OUTPUTS The digital outputs of the VSP3200 and VSP3210 are designed to be compatible with both high-speed TTL and CMOS logic families. The driver stage of the digital outputs is supplied through a separate supply pin, VDRV (pin 41), which is not connected to the analog supply pins (VCC). By adjusting the voltage on VDRV, the digital output levels will vary respectively. Thus, it is possible to operate the VSP3200 and VSP3210 on +5V analog supplies while interfacing the digital outputs to 3V logic. It is recommended to keep the capacitive loading on the data lines as low as possible (typically less than 15pF). Larger capacitive loads demanding higher charging current surges can feed back to the analog portion of the VSP3200 and VSP3210 and influence the performance. If necessary, external buffers or latches may be used, providing the added benefit of isolating the PROGRAMMABLE GAIN AMPLIFIER (PGA) The VSP3200 and VSP3210 have one PGA which is inserted between the CDSs and the 3:1 MUX. The PGA is controlled by a 6-bit of Gain Register; each channel (Red, Green, and Blue) has its own Gain Register. The gain varies from 1 to 4.8 (0dB to 14dB), and the curve has log characteristics. Gain Register Code all “0” corresponds to minimum gain, and Code all “1” corresponds to maximum gain. The transfer function of the PGA is: PIN Gain = 80/(80 – GC) where, GC is the integer representation of the 6-bit PGA gain register. Figure 1 shows the PGA transfer function plots. 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 High Byte B15 B14 B13 B13 B11 B10 B9 B8 Low Low Low Low Low Low Low Low Low Byte B7 B6 B5 B4 B3 B2 B1 B0 Low Low Low Low Low Low Low Low 31 30 29 28 27 26 25 TABLE I. Output Format for VSP3200 (Demultiplexed Mode). PIN 40 39 38 37 36 35 34 33 32 High Byte – – B15 B14 B13 B12 B11 B10 B9 B8 – – – – – – Low Byte – – B7 B6 B5 B4 B3 B2 B1 B0 – – – – – – TABLE II. Output Format for VSP3210. 5 14 4.5 12 4 10 Gain (dB) 3 2.5 8 6 PGA Gain Code (0 to 3) 60 56 52 48 44 40 36 32 28 24 20 16 8 12 60 56 52 48 44 40 36 32 28 24 20 16 8 0 12 1 4 2 0 1.5 4 4 2 0 Gain 3.5 PGA Gain Code (0 to 63) FIGURE 1. PGA Transfer Function Plots. VSP3200, 3210 SBMS012A 11 INPUT CLAMP The input clamp should be used for 1-Channel and 3-Channel CCD mode, and enabled when both CLP and CK1 are set to HIGH. Bit Clamp: the input clamp is always enabled. Line Clamp: enables during the dummy pixel interval at every horizontal line, and disables during the effective pixel interval. Generally, “Bit Clamp” is used for many scanner applications, however “Line Clamp” is used instead of “Bit Clamp” when the clamp noise is impressive. CHOOSING THE AC INPUT COUPLING CAPACITORS The purpose of the Input Coupling Capacitor is to isolate the DC offset of the CCD array from affecting the VSP3200 and VSP3210 input circuitry. The internal clamping circuitry is used to restore the necessary DC bias to make the VSP3200 and VSP3210 input circuitry functional. Internal clamp voltage, VCLAMP, is set when both the CLP pin and CK1 are set HIGH. VCLAMP changes depending on the value of VREF. VCLAMP is 2.5V if VREF is set to 1V (D1 of the Configuration Register set to “0”), and VCLAMP is 3V if VREF is set to 1.5V (D1 of the Configuration Register set to “1”). There are many factors that decide what size of Input Coupling Capacitor is needed. Those factors are CCD signal swing, voltage difference between the Input Coupling Capacitor, leakage current of the VSP3200 and VSP3210 input circuitry, and the time period of CK1. Figure 2 shows the equivalent circuit of the VSP3200 and VSP3210 inputs. In this equivalent circuit, Input Coupling Capacitor CIN, and Sampling Capacitor C1, are constructed as a capacitor divider during CK1. For AC analysis, OP inputs are grounded. Therefore, the sampling voltage, VS, during CK1 is: VS = (CIN/(CIN + C1)) • VIN From the above equation, we know that a larger CIN makes VS close to VIN. In other words, the input signal (VIN) will not be attenuated if CIN is large. However, there is a disadvantage of using a large CIN: it will take longer for the CLP signal to charge up CIN so that the input circuitry of the VSP3200 and VSP3210 can work properly. CHOOSING CMAX AND CMIN As mentioned before, a large CIN is better if there is enough time for the CLP signal to charge up CIN so that the input circuitry of the VSP3200 and VSP3210 can work properly. Typically, 0.01µF to 0.1µF of CIN can be used for most cases. In order to optimize CIN, the following two equations can be used to calculate the maximum (CMAX) and minimum (CMIN) values of CIN: CMAX = (tCK1 • N)/[RSW • ln(VD/VERROR)] where tCK1 is the time when both CK1 and CLP go HIGH, and N is the number of black pixels; RSW is the switch resistance of the VSP3200 and VSP3210 (typically, driver impedance + 4kW); VD is the droop voltage of CIN; VERROR is the voltage difference between VS and VCLAMP. CMIN = (II/VERROR) • t CK1 C1 4pF CIN Op Amp VIN C2 4pF CLP CK2 CK1 VCLAMP FIGURE 2. Equivalent Circuit of VSP3200 and VSP3210 Inputs. 12 where II is the leakage current of the VSP3200 and VSP3210 input circuitry (10nA is a typical number for this leakage current); t is the clamp pulse period. SETTING FOR FULL-SCALE INPUT RANGE The input range of the internal 16-bit A/D converter can be set in two ways: • Internal reference: to set the internal reference mode, D2 of the configuration register must be set to “0” and the reference voltage set through D1. The full-scale input voltage setting is twice the reference voltage. When the reference voltage is set at 1V (D1 = “0”), the full-scale voltage is 2Vp-p. However, when the reference voltage is set at 1.5V (D1 = “1”), the full-scale voltage is 3Vp-p. In internal reference mode, VREF should be connected to GND with a 0.1µF capacitor. Do not use VREF voltages in VSP3200, 3210 SBMS012A other system circuits, as it would affect the reference voltage of the A/D converter and prevent proper A/D conversion. • External Reference: to set the external reference mode, D2 of the configuration register must be set to “1”. In external reference mode, VREF operates as an analog voltage input pin. Inputting half the voltage necessary for the full-scale voltage range (e.g.: 1.7V applied for a necessary 3.4Vp-p input range), with a reference voltage range from 0.25V to 1.75V, will create the full-scale range. Thus, when VREF is 0.5V, the full-scale range will be 0.5Vp-p, and when VREF is 1.75V, the full-scale range will be 3.5Vp-p. PROGRAMMING THE VSP3200 AND VSP3210 The VSP3200 and VSP3210 consist of three CCD channels and a 16-bit A/D. Each channel (Red, Green, and Blue) has its own 10-bit Offset and 6-bit Gain Adjustable Registers to be programmed by the user. There is also an 8-bit Configuration Register, on-chip, to program the different operation modes. Those registers are shown in Table III. ADDRESS A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 REGISTER Configuration Register (8-bit) Red Channel Offset Register (10-bit) Green Channel Offset Register (10-bit) Blue Channel Offset Register (10-bit) Red Channel Gain Register (6-bit) Green Channel Gain Register (6-bit) Blue Channel Gain Register (6-bit) Reserved POWER-ON DEFAULT VALUE All All All All All All All “0s” “0s” “0s” “0s” “0s” “0s” “0s” TABLE III. On-Chip Registers. These registers can be accessed by the following two programming modes: • Parallel Programming Mode (VSP3200 only) using digital data output pins, with the data bus assigned as D0 to D9 (pins 25 to 34), and the address bus as A0 to A2 (pins 35 to 37). It can be used for both reading and writing operations. However, it cannot be used by the Demultiplexed mode (when D7 of the Configuration Register is set to “1”). • Serial Programming Mode using a serial port, Serial Data (SD), the Serial Shift Clock (SCLK), and Write Signal (WRT) assigned. It can be used only for writing operations; reading operations via the serial port are prohibited. Table IV shows how to access these modes (VSP3200 only). VSP3200, 3210 SBMS012A OE P/S MODE 0 0 Digital data output enabled, Serial mode enabled 0 1 Prohibit mode (can not set this mode) 1 0 Digital data output disabled, Serial mode enabled 1 1 Digital data output disabled, Parallel mode enabled TABLE IV. Access Mode for Serial and Parallel Port (VSP3200 Only). CONFIGURATION REGISTER The Configuration Register design is shown in Table V. BIT LOGIC ‘0’ D0 D1 D2 D3 CCD mode VREF = 1V Internal Reference 3-channel Mode, D4 and D5 disabled D4, D5 (disabled when 3-channel) D6 D7(1) MUX Sequence Red > Green > Blue Normal output mode LOGIC ‘1’ CIS mode VREF =1.5V External Reference 1-channel Mode, D4 and D5 enabled D4 D5 0 0 1-channel mode, Red channel 0 1 1-channel mode, Green channel 1 0 1-channel mode, Blue channel MUX Sequence Blue > Green >Red Demultiplexed output mode NOTE: (1) D7 of the configuration register should always be set to “1” for the VSP3210. Power-on default value is “0”; initial write operation for “1” is also needed for the VSP3210, when in power-on. TABLE V. Configuration Register Design. Power-on default value is all “0s”, set to 3-Channel CCD mode with 1V internal reference, R > G > B MUX sequence, and normal output mode. For reading/writing to the Configuration Register, the address will be A2 = “0”, A1 = “0”, and A0 = “0”. For Example: A 3-Channel CCD with internal reference VREF = 1V (2V full-scale input), R > G > B sequence and normal output mode will be D0 = “0”, D1 = “0”, D2 =“0”, D3 = “0”, D4 = “x (don’t care)”, D5 = “x (don’t care)”, D6 = “0”, and D7 = “0”. For this example, bypass VREF with an appropriate capacitor (e.g.:, 10µF to 0.1µF) when internal reference mode is used. Another Example: A 1-Channel CCD mode (Green channel) with an external 1.2V reference (2.4V full-scale input), Demultiplexed Output mode will be D0 = “0”, D1 = “x (don’t care)”, D2 = “1”, D3 = “1”, D4 = “0”, D5 = “1”, D6 = “x (don’t care)”, and D7 = “1”. For this example, VREF will be an input pin applied with 1.2V. 13 OFFSET REGISTER Offset Registers control the analog offset input to channels prior to the PGA. There is a 10-bit Offset Register on each channel. The offset range varies from –500mV to +500mV. The Offset Register uses a straight binary code. All “0s” corresponds to –500mV, and all “1s” corresponds to +500mV of the offset adjustment. The register code (200H) corresponds to 0mV of the offset adjustment. The Power-on default value of the Offset Register is all ”0s”, so the offset adjustment should be set to –500mV. PGA GAIN REGISTER PGA Gain Registers control the gain to channels prior to the digitization by the A/D converter. There is a 6-bit PGA Gain Register on each channel. The gain range varies from 1 to 4.8 (from 0dB to 13dB). The PGA Gain Register is a straight binary code. All “0s” corresponds to an analog gain of 0dB, and all “1s” corresponds to an analog gain of 13dB. PGA Transfer function is log gain curve. Power-on default value is all “0s”, so that it sets the gain of 0dB. OFFSET AND GAIN CALIBRATION SEQUENCE When the VSP3200 and VSP3210 are powered on, they will be initialized as 3-Channel CCDs, 1V internal reference mode (2V full-scale) with an analog gain of 1, and normal output mode. This mode is commonly used for CCD scanner applications. The calibration procedure is done at the very beginning of the scan. To calibrate the VSP3200, use the following procedures: 1) Set the VSP3200 to the proper mode. 2) Set Offset to 0mV (control code: 00H), and PGA gain to 1 (control code: 200H). 3) Scan dark line. 4) Calculate the pixel offsets according to the A/D Converter output. 5) Readjust input Offset Registers. 6) Scan white line. 7) Calculate gain. It will be the A/D Converter full-scale divided by the A/D Converter output when the white line is scanned. 8) Set the Gain Register. If the A/D Converter output is not close to full-scale, go back to item 3. Otherwise, the calibration is done. The calibration procedure is started at the very beginning of the scan. Once calibration is done, registers on the VSP3200 will keep this information (offset and gain for each channel) during the operation. 14 RECOMMENDATION FOR POWER SUPPLY, GROUNDING, AND DEVICE DECOUPLING The VSP3200 and VSP3210 incorporate a very-high precision, high-speed A/D converter and analog circuitry vulnerable to any extraneous noise from the rails, etc. Therefore, it should be treated as an analog component and all supply pins, except VDRV, should be powered by the only analog supply in the system. This will ensure the most consistent results, since digital power lines often carry high levels of wideband noise that otherwise would be coupled into the device and degrade the achievable performance. Proper grounding, bypassing, short lead length, and the use of ground planes are particularly important for high-frequency designs. Multilayer PC boards are recommended for the best performance since they offer distinct advantages such as minimization of ground impedance, separation of signal layers by ground layers, etc. It is recommended that all ground pins of the VSP3200 and VSP3210 be joined together at the IC and connected only to the analog ground of the system. The driver stage of the digital outputs (B[15:0]) is supplied through a dedicated supply pin, VDRV, and should be completely separated from other supply pins with at least a ferrite bead. Keeping the capacitive loading on the output data lines as low as possible (typically less than 15pF) is also recommended. Larger capacitive loads demand higher charging current surges that can feed back into the analog portions of the VSP3200 and VSP3210, affecting device performance. If possible, external buffers or latches should be used, providing the added benefit of isolating the VSP3200 and VSP3210 from any digital noise activity on the data lines. In addition, resistors in series with each data line may help minimize surge currents. Values in the range of 100W to 200W will limit the instantaneous current the output stage requires from recharging parasitic capacitances as output levels change from LOW to HIGH or HIGH to LOW. As the result of the high operation speed, the converter also generates high-frequency current transients and noises that are fed back into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed. In most cases, 0.1µF ceramic chip capacitors are adequate in decoupling reference pins. Supply pins should be decoupled to the ground plane with a parallel combination of tantalum (1µF to 22µF) and ceramic (0.1µF) capacitors. Decoupling effectiveness largely depends upon the proximity to the individual pins. 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