SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 D 4.5-V to 5.5-V VCC Operation D Wide Operating Temperature Range of −55°C to 125°C CD54HCT573 . . . F PACKAGE CD74HCT573 . . . DB, E, OR M PACKAGE (TOP VIEW) D Balanced Propagation Delays and D D D OE 1D 2D 3D 4D 5D 6D 7D 8D GND Transition Times Standard Outputs Drive Up To 10 LS-TTL Loads Significant Power Reduction Compared to LS-TTL Logic ICs Inputs Are TTL-Voltage Compatible description/ordering information 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE The ’HCT573 devices are octal transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION PACKAGE† TA −55°C 125°C −55 C to 125 C ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − E Tube CD74HCT573E CD74HCT573E SSOP − DB Tape and reel CD74HCT573DBR HK573 Tube CD74HCT573M Tape and reel CD74HCT573M96 Tube CD54HCT573F3A SOIC − M CDIP − F HCT573M CD54HCT573F3A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated !"# $"%&! '#( '"! ! $#!! $# )# # #* "# '' +,( '"! $!#- '# #!#&, !&"'# #- && $##( $'"! !$& ./0 && $## # ##' "&# )#+# #'( && )# $'"! $'"! $!#- '# #!#&, !&"'# #- && $##( POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) OE LE 1 11 C1 1D 2 19 1Q 1D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output drain current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous output source or sink current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 recommended operating conditions (see Note 3) VCC VIH Supply voltage VIL VI Low-level input voltage VO ∆t/∆v Output voltage TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C MIN MAX MIN MAX MIN MAX 4.5 5.5 4.5 5.5 4.5 5.5 High-level input voltage 2 2 Input voltage Input transition rise or fall rate 2 UNIT V V 0.8 0.8 0.8 V VCC VCC VCC VCC VCC VCC V 500 500 500 ns V NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH VI = VIH or VIL IOH = −20 µA IOH = −6 mA 4.5 V VOL VI = VIH or VIL IOL = 20 µA IOL = 6 mA 4.5 V II IOZ VI = VCC or 0 VO = VCC or 0 ICC VI = VCC or 0, ∆ICC† IO = 0 TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C MIN MIN MIN MAX 4.4 4.4 4.4 3.98 3.7 3.84 UNIT MAX V 0.1 0.1 0.1 0.26 0.4 0.33 5.5 V ±0.1 ±1 ±1 µA 5.5 V ±0.5 ±10 ±5 µA 5.5 V 8 160 80 µA 360 490 450 µA 10 10 10 pF 4.5 V to 5.5 V One input at VCC − 2.1 V, Other inputs at 0 or VCC MAX Ci V Co 20 20 20 pF † Additional quiescent supply current per input pin, TTL inputs high, 1 unit load. For dual-supply systems, theoretical worst-case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA. HCT INPUT LOADING TABLE INPUT UNIT LOAD OE 1.25 Any D 0.3 LE 0.65 Unit load is ∆ICC limit specified in electrical characteristics table (e.g., 360 µA max at 25°C). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 timing requirements over recommended operating free-air temperature range, VCC = 4.5 V (unless otherwise noted) (see Figure 1) TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C MIN MIN MIN MAX MAX UNIT MAX tw Pulse duration, LE high 16 24 20 ns tsu Setup time, data before LE↓ 13 20 16 ns th Hold time, data after LE↓ 10 15 13 ns switching characteristics over recommended operating free-air temperature range, VCC = 4.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C MIN MIN MIN TO (OUTPUT) LOAD CAPACITANCE 35 53 44 Q CL = 50 pF 35 53 44 D MAX MAX UNIT MAX tpd LE ten OE Q CL = 50 pF 35 53 44 ns tdis OE Q CL = 50 pF 35 53 44 ns Q CL = 50 pF 12 18 15 ns tt ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 TYP Power dissipation capacitance 53 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT pF SCLS455C − FEBRUARY 2001 − REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION VCC Test Point From Output Under Test PARAMETER S1 ten 1 kΩ tdis CL (see Note A) S2 S1 S2 tPZH Open Closed tPZL Closed Open tPHZ Open Closed tPLZ Closed Open Open Open tpd or tt tw LOAD CIRCUIT 3V 1.3 V Input 1.3 V 0V VOLTAGE WAVEFORMS PULSE DURATION CLR Input 3V Reference Input 3V 1.3 V 1.3 V 0V 0V tsu trec Data 1.3 V Input 0.3 V 3V 1.3 V CLK th 2.7 V 2.7 V tr 0V VOLTAGE WAVEFORMS RECOVERY TIME 3V 1.3 V 0.3 V 0 V tf VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 3V Input 1.3 V 1.3 V 0V tPLH In-Phase Output 1.3 V 10% 90% tPHL 90% 1.3 V 1.3 V 0V tPHL 90% tr Out-of-Phase Output 3V Output Control VOH 1.3 V 10% tf VOL tPLH 1.3 V 10% tf 1.3 V 10% 90% tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES ≈VCC 1.3 V Output Waveform 2 (see Note B) 10% VOL tPHZ tPZH VOH VOL tPLZ tPZL Output Waveform 1 (see Note B) 1.3 V 90% VOH ≈0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time, with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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