CM3107 2 Amp Source/ Sink Bus Termination Regulator for DDR Memory and Front Side Bus Applications Features Product Description • The CM3107 is a sinking and sourcing regulator specifically designed for series-parallel bus termination for high-speed chip set busses as well as DDR memory systems. It can source and sink current up to 2.0A with a load regulation of 0.5%. The VTT output voltage is selectable by VDDQSEL and FSBSEL pins. The VDDQSEL pin controls whether the CM3107 is in DDR memory mode with VTT=VDDQ/2, or in FSB mode. In FSB mode, FSBSEL controls whether VTT is 1.225V or 1.45V. This allows the same chip to be used in two different circuits on an Intel 865-based motherboard. • • • • • • • • Ideal for Intel 865 Front Side Bus VTT and DDR VTT applications Sinks and sources 2 Amps Over current protection Over temperature protection Integrated power MOSFETs Excellent accuracy (0.5% load regulation) Selectable output (1.225V/1.45V or VDDQ/2) 8-lead SOIC and PSOP packages Lead-free versions available Applications • • • • The CM3107 provides over current and over temperature protection, which protect the chip from excessive heating due to high current and high temperature. A shutdown capability using an external transistor reduces power consumption and provides a high impedance output. Intel 865/845 Front Side Bus termination Single and dual DDR memory termination Active termination buses Graphics card DDR memory termination The CM3107 is housed in 8-lead SOIC and PSOP packages and is available with optional lead-free finishing. Simplified Electrical Schematic VDDQSEL FSBSEL Over Temp Over Current Reference 50K VCC VDDQ Output Select Driver OUT Buffer VTT IN 50K VREF VSENSE GND © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 1 CM3107 PACKAGE / PINOUT DIAGRAM TOP VIEW VDDQ VTT GND 1 8 2 7 3 6 VSENSE 4 5 TOP VIEW VCC VDDQSEL VREF FSBSEL VDDQ V TT GND 1 VSENSE 4 8-lead SOIC 2 3 VCC VDDQSEL VREF FSBSEL 8 7 GND 6 5 8-lead PSOP Note: This drawing is not to scale. PIN DESCRIPTIONS SOIC-8 LEAD(S) NAME DESCRIPTION 1 VDDQ VDDQ 2 VTT Outputs either 1.225V/1.45V FSB or VDDQ/2 DDR (See note 1) 3 GND Ground 4 VSENSE Feedback voltage input 5 FSBSEL Selects FSB output for either VTT=1.225V or 1.45V 6 VREF 7 VDDQSEL 8 VCC 1.25V reference voltage input for DDR bus Select output to support FSB or DDR applications Power for internal control circuits Note 1: Assumes VDDQ and VDDQSEL are tied together in DDR application. Ordering Information PART NUMBERING INFORMATION Standard Finish Lead-free Finish Ordering Part Ordering Part Pins Package Number1 Part Marking Number1 Part Marking 8 PSOP-8 CM3107-00SB CM3107-00SB CM3107-12SH CM3107-00SH 8 SOIC-8 CM3107-00SN CM310701S CM3107-00SM CM3107-00SM Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. © 2004 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 02/02/04 CM3107 Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS VCC Operating Supply Voltage 7 V VDDQ Input Voltage 7 V Pin Voltages VTT Output Any other pins 7 7 V V ±2000 V Storage Temperature Range -40 to +150 °C Operating Temperature Range Ambient Junction -40 to +85 -40 to +150 °C °C Power Dissipation (see note 1) Internally Limited W ESD (HBM) Note 1: These devices must be derated based on thermal resistance at elevated temperatures. The device packaged in a 8-lead SOIC leadframe must be derated at θJA = 151°C/W . θ JA of the 8-lead PSOP is 40°C/W. STANDARD OPERATING CONDITIONS PARAMETER VALUE UNITS VDDQ 2.5 to 3.3 V VCC 2.5 to 3.3 V Ambient Operating Temperature CVOUT 0 to +70 °C 220 ±20% µF © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 3 CM3107 Specifications (cont’d) ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL VIN PARAMETER CONDITIONS Input Voltage Range VDDQ VCC ICC VCC Quiescent Current IVTT = 0A VTT Output Voltage IVTT = 0A, VDDQ = 2.5V, VDDQSEL= logic "1" = 2.5V VDDQSEL= logic "0", FSBSEL= logic "0" VDDQSEL = logic "0", FSBSEL = logic "1" VREF Load Regulation 0A < IVTT < 2.0A or 0A < IVTT < -2.0A Output Reference Voltage VDDQSEL = 2.5V, IVREF=0A VOSVTT Output Offset from V REF ZREF VREF Output Impedance ZVDDQSEL CLVTT VFSBSEL TDISABLE THYST TYP MAX UNITS 2.2 2.2 2.5 2.5 VCC 5.5 V V µA 450 IVTT = 0A, VDDQ = 3.3V, VDDQSEL= logic "0", FSBSEL= logic "0" VDDQSEL = logic "0", FSBSEL = logic "1" VRLOAD MIN 1.225 1.200 1.425 1.250 1.225 1.450 1.275 1.250 1.475 V V V V 1.200 1.425 1.225 1.450 1.250 1.475 V V 6.25 1.225 1.250 -20 -5µA < IVREF < 5µA mV 1.275 V 20 mV 5 kΩ VVDDQSEL Input Impedance 100 kΩ VTT Current Limit 2.5 A Output Selection Logic (FSBSEL) Logic "1" Level Logic "0" Level 1.5 0.4 Shutdown Temperature Thermal Hysteresis 150 50 V V °C °C Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified. © 2004 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 02/02/04 CM3107 Performance Information Typical DC Characteristics (nominal conditions unless otherwise specified) Figure 1. Output Voltage with VCC Supply (VDDQSEL= 2.5V) Figure 3. Reference Voltage with VCC Supply (VDDQSEL= 2.5V) Figure 2. Load Regulation (Sink) Figure 4. Load Regulation (Source) © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 5 CM3107 Performance Information (cont’d) Typical DC Characteristics (nominal conditions unless otherwise specified) Figure 5. Over Current Limit (Sink) Figure 7. Over Current Limit (Source) Figure 6. Output Voltage with VCC Supply Voltage (VDDQSEL = 0V, FSBSEL = 0V) Figure 8. Output Voltage with VCC Supply Voltage (VDDQSEL = 0V, FSBSEL = 2.5V) © 2004 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 02/02/04 CM3107 Performance Information (cont’d) Typical DC Characteristics (nominal conditions unless otherwise specified) Figure 9. VCC Supply Current with Supply Voltage Typical Transient Characteristics (nominal conditions unless otherwise specified) Figure 10. Load Transient (0A to 2.0A Sink) Figure 11. Line Transient (0A to 2.0A Source) © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 7 CM3107 Performance Information (cont’d) Typical Thermal Characteristics The overall junction to ambient thermal resistance (θJA) for device power dissipation (PD) consists primarily of two paths in series. The first path is the junction to the case (θ JC) which is defined by the package style, instantaneous current of 2A should not be exceeded 29% of the time. For CM3107-00SB, the maximum RMS current increases from 1.3A to 2.2A. Thus, the maximum continuous current can be 2A all the time. and the second path is case to ambient (θ CA) thermal resistance which is dependent on board layout. The final operating junction temperature for any set of conditions can be estimated by the following thermal equation: TJUNC = TAMB + PD (θJC) + PD (θCA) = TAMB + PD (θJA) When a CM3107-00SN (SOIC) is mounted on a double sided printed circuit board with two square inches of copper allocated for "heat spreading", the resulting θJA is 151°C/W. Based on the over temperature limit of 150°C with an ambient of 85°C, the available power of this package will be: PD = (150°C -85°C) / 151°C/W = 0.43W For the CM3107-00SB (PSOP), the θJA is 40°C/W and the available power for this package will be: PD = (150°C -85°C) / 40°C/W = 0.1.625W Figure 12. Duty Cycle vs. Ambient Temperature (ILOAD = 2A) DDR Memory Application Since the output voltage is 1.25V, and the device can either source current from VDDQ or sink current to Ground, the power dissipated in the device at any time is 1.25V times the current load. This means the maximum average RMS current (in either direction) is 0.344A for CM3107-00SN and 1.3A for CM3107-00SB. The maximum instantaneous current is specified at 2A, so this condition should not be exceeded 17% and 65% of the time for CM3107-00SN and CM3107-00SB, respectively. It is highly unlikely in most usage of DDR memory that this might occur, because it means the DDR memory outputs are either all high or all low for 17% (SOIC) and 65% (PSOP) of the time.. If the ambient temperature is 40°C instead of 85°C, which is typically the maximum in most DDR memory applications, the power dissipated PD can be 0.73W for CM3107-00SN and 2.75W for CM3107-00SB. So the maximum average RMS current increases from 0.42A to 0.58A for CM3107-00SN and maximum Figure 13. Duty Cycle vs. Output Current (Temp=70°C) © 2004 California Micro Devices Corp. All rights reserved. 8 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 02/02/04 CM3107 Performance Information (cont’d) Typical Thermal Characteristics (cont’d) Front Side Bus Application If the CM3107-00SN is instead used for the Front Side Bus application, where VDDQ could be connected to the 3.3V VCC rail for ease of connectivity, the power dissipated will increase to [3.3V-1.4V] = 1.9V times the sourcing current, or [1.4V - 0V] = 1.4V times the sinking current. So the worst case is with all FSB outputs low for a period of time, such that the maximum average source current at an ambient of 40°C is [0.73W / 1.9V] = 0.38A. If this average current is exceeded, the device will go over-temperature and the output will drop to 0V. If it is likely that this average current will be exceeded for the FSB application, then the version with the heat spreader, CM3107-00SB, should be used, or for commonality of device type for both applications, the VDDQ pin should instead be connected to 2.5V. The maximum average source current at an ambient of 40°C is [2.75W/1.9V] = 1.45A. Measurements showing performance up to a junction temperature of 150°C were performed under light load conditions (5mA). This allows the ambient temperature to be representative of the internal junction temperature. Note: The use of multi-layer board construction with separate ground and power planes will further enhance the overall thermal performance. The theoretical calculations of these relationships show the safe operating area of the CM3107 in the SOIC and PSOP packages. Thermal characteristics were measured using a double sided board with two square inches of copper area connected to the GND pins for "heat spreading". Figure 15. Output Voltage vs. Ambient Temperature (ILOAD=5mA) Figure 14. Reference Voltage vs. Temperature Figure 16. Quiescent Current vs. Temperature Figure 17. © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 9 CM3107 Application Information VCC VDDQ CVDDQ 47µF VDDQ VCC VREF VDDQSEL VREF CVREF VDDQSEL VTT 0.1µF FSBSEL CVCC 47µF VSENSE FSBSEL VTT GND CVTT 220µF Figure 18. Typical Application Circuit Figure 19. Typical Front Side Bus with Suspend to RAM Application Circuit © 2004 California Micro Devices Corp. All rights reserved. 10 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 02/02/04 CM3107 Application Information (cont’d) VCC (CPU Core) GMCH_EN VDDQSEL FSBSEL VTT NOTE "1" Don’t Care VDDQSEL/2 (Note1) For DDR Open or "0" "0" 1.225V For FSB "1" 1.45V For FSB Open or "0" Note 1:Assumes VDDQ and VDDQSEL are tied together in DDR application. GMCHVCCP Figure 20. Front Side Bus Timing diagram Table 1: VTT Output Selection Truth Table. PCB Layout Considerations The CM3107-00SB has a heat spreader attached to the underneath of the PSOP-8 package in order for heat to be transferred much easier from the package to the PCB. The heat spreader is a copper pad of dimensions just smaller than the package itself. By positioning the matching pad on the PCB top layer to connect to the spreader during manufacturing, the heat will be transferred between the two pads. The drawing below shows the recommended PCB layout. Note that there are six vias on either side to allow the heat to dissipate into the ground and power planes on the inner layers of the PCB. Vias can be placed underneath the chip, but this can cause blockage of the solder. The ground and power planes should be at least 2 sq in. of copper by the vias. It also helps dissipation to spread if the chip is positioned away from the edge of the PCB, and not near other heat dissipating devices. A good thermal link from the PCB pad to the rest of the PCB will ensure a thermal link from the CM3107 package to ambient, θ JA, of around 40°C/W. Table 2: Recommended Heat Sink PCB Layout © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 11 CM3107 Mechanical Details The CM3107 is available in an 8-lead SOIC and PSOP package. Mechanical Package Diagrams SOIC-8 Mechanical Specifications TOP VIEW Dimensions for CM3107 devices packaged in 8-pin SOIC packages are presented below. D 8 7 6 5 For complete information on the SOIC-8 package, see the California Micro Devices SOIC Package Information document. H Pin 1 Marking E PACKAGE DIMENSIONS Package SOIC Leads Dimensions 1 3 4 8 Millimeters Inches Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.19 0.150 0.165 e 2 1.27 BSC SIDE VIEW A A1 SEATING PLANE B END VIEW 0.050 BSC H 5.80 6.20 0.228 0.244 L 0.40 1.27 0.016 0.050 # per tube 100 pieces* # per tape and reel 2500 pieces e C L Controlling dimension: inches Package Dimensions for SOIC-8 * This is an approximate number which may vary. © 2004 California Micro Devices Corp. All rights reserved. 12 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 02/02/04 CM3107 Mechanical Details PSOP-8 Mechanical Specifications Dimensions for CM3107 devices packaged in 8-pin PSOP packages with an intagrated heatslug are presented below. Mechanical Package Diagrams TOP VIEW For complete information on the PSOP-8 package, see the California Micro Devices PSOP-8 Package Information document. D 8 PACKAGE DIMENSIONS Package H 6 5 E Pin 1 Marking PSOP-8 Leads Dimensions 7 8 Millimeters Inches Min Max Min Max A 1.30 1.62 0.051 0.064 A1 0.03 0.10 0.001 0.004 B 0.33 0.51 0.013 0.020 C 0.18 0.25 0.007 0.010 D 4.83 5.00 0.190 0.197 E 3.81 3.99 0.150 0.157 e 1.02 1.52 0.040 0.050 H 5.79 6.20 0.228 0.244 L 0.41 1.27 0.016 0.050 x** 3.56 4.06 0.130 0.150 y** 2.29 2.79 0.090 0.110 # per tube 100 pieces* # per tape and reel 2500 pieces 1 2 3 4 BOTTOM VIEW D 1 2 3 4 Heat Slug x H y E x/2 8 7 y/2 6 5 SIDE VIEW Controlling dimension: inches A A1 SEATING PLANE * This is an approximate number which may vary. e B ** Centered on package centerline. END VIEW C L Package Dimensions for PSOP-8 © 2004 California Micro Devices Corp. All rights reserved. 02/02/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 13